path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.172902                       # Number of seconds simulated
sim_ticks                                5172902281500                       # Number of ticks simulated
final_tick                               5172902281500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 117061                       # Simulator instruction rate (inst/s)
host_op_rate                                   230687                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1419746087                       # Simulator tick rate (ticks/s)
host_mem_usage                                 420308                       # Number of bytes of host memory used
host_seconds                                  3643.54                       # Real time elapsed on the host
sim_insts                                   426515724                       # Number of instructions simulated
sim_ops                                     840516219                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2496512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1067840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10426304                       # Number of bytes read from this memory
system.physmem.bytes_read::total             13994560                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1067840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1067840                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9194240                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9194240                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        39008                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           55                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16685                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             162911                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                218665                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          143660                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143660                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       482613                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            680                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             74                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               206430                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2015562                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2705359                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          206430                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             206430                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1777385                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1777385                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1777385                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       482613                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           680                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            74                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              206430                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2015562                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4482745                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        107419                       # number of replacements
system.l2c.tagsinuse                     64844.084797                       # Cycle average of tags in use
system.l2c.total_refs                         3992672                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        171622                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         23.264337                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        50135.967843                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker       12.897301                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker        0.156788                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst           3372.666022                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data          11322.396844                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.765014                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker       0.000197                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker       0.000002                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst             0.051463                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data             0.172766                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.989442                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker        110667                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker          8396                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst             1054432                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data             1345104                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2518599                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         1613189                       # number of Writeback hits
system.l2c.Writeback_hits::total              1613189                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data              337                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 337                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data            163997                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               163997                       # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker         110667                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker           8396                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst              1054432                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data              1509101                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2682596                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker        110667                       # number of overall hits
system.l2c.overall_hits::cpu.itb.walker          8396                       # number of overall hits
system.l2c.overall_hits::cpu.inst             1054432                       # number of overall hits
system.l2c.overall_hits::cpu.data             1509101                       # number of overall hits
system.l2c.overall_hits::total                2682596                       # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker           55                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst             16686                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data             35012                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                51759                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data           1516                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1516                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data          128839                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             128839                       # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker           55                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst              16686                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data             163851                       # number of demand (read+write) misses
system.l2c.demand_misses::total                180598                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker           55                       # number of overall misses
system.l2c.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.l2c.overall_misses::cpu.inst             16686                       # number of overall misses
system.l2c.overall_misses::cpu.data            163851                       # number of overall misses
system.l2c.overall_misses::total               180598                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker      2907000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.itb.walker       312000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.inst    885914499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data   1865182494                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2754315993                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data     39171500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     39171500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data   6715513999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6715513999                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.dtb.walker      2907000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.itb.walker       312000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.inst    885914499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data   8580696493                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      9469829992                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.dtb.walker      2907000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.itb.walker       312000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.inst    885914499                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data   8580696493                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     9469829992                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker       110722                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker         8402                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst         1071118                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data         1380116                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2570358                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1613189                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1613189                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data         1853                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1853                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data        292836                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           292836                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker       110722                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker         8402                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst          1071118                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data          1672952                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2863194                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker       110722                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker         8402                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst         1071118                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data         1672952                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2863194                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000714                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst       0.015578                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data       0.025369                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.020137                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data     0.818133                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.818133                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data     0.439970                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.439970                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker     0.000714                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst        0.015578                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data        0.097941                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.063076                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker     0.000714                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst       0.015578                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data       0.097941                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.063076                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52854.545455                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 53093.281733                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 53272.663487                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 53214.242798                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25838.720317                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 25838.720317                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.301167                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52123.301167                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52854.545455                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 53093.281733                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52368.899140                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52435.962702                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52854.545455                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 53093.281733                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52368.899140                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52435.962702                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               96993                       # number of writebacks
system.l2c.writebacks::total                    96993                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu.data              1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu.data               1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu.data              1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           55                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.inst        16685                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data        35011                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           51757                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data         1516                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         1516                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data       128839                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        128839                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.dtb.walker           55                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.inst         16685                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data        163850                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           180596                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.dtb.walker           55                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.inst        16685                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data       163850                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          180596                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2241000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       240000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.inst    682427500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data   1437356500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   2122265000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data     61068000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     61068000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5163609501                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5163609501                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2241000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.itb.walker       240000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst    682427500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data   6600966001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   7285874501                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2241000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.itb.walker       240000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst    682427500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data   6600966001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   7285874501                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  59192209064                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  59192209064                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1211526000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1211526000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data  60403735064                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  60403735064                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000714                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.015577                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.025368                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.020136                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.818133                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.818133                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.439970                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.439970                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000714                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst     0.015577                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data     0.097941                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.063075                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000714                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst     0.015577                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data     0.097941                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.063075                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40900.659275                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41054.425752                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 41004.405201                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40282.321900                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40282.321900                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.000458                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.000458                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40900.659275                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40286.640226                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40343.498754                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40900.659275                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40286.640226                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40343.498754                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     47565                       # number of replacements
system.iocache.tagsinuse                     0.200108                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47581                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              5000599162000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.200108                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.012507                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.012507                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          900                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              900                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47620                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47620                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47620                       # number of overall misses
system.iocache.overall_misses::total            47620                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    135466932                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    135466932                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6926961160                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   6926961160                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide   7062428092                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   7062428092                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide   7062428092                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   7062428092                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          900                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            900                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47620                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47620                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47620                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47620                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150518.813333                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 150518.813333                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148265.435788                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 148265.435788                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148308.023772                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 148308.023772                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148308.023772                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 148308.023772                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        269004                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   25                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10760.160000                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          900                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          900                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47620                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47620                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47620                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47620                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     88635000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     88635000                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4497207944                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   4497207944                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4585842944                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   4585842944                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4585842944                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   4585842944                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98483.333333                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 98483.333333                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96258.731678                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 96258.731678                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 96300.775808                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 96300.775808                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.numCycles                        472946175                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 90027772                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           90027772                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            1176455                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              84282590                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 81704922                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           31264026                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      446943348                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    90027772                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           81704922                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     169792009                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 5327046                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     167003                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles              104616235                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                37821                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         45804                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          481                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9365381                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                539972                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5058                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          310035010                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.836765                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.376817                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                140677603     45.37%     45.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1773611      0.57%     45.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72784877     23.48%     69.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   988899      0.32%     69.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1639325      0.53%     70.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  3670845      1.18%     71.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1138945      0.37%     71.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1446155      0.47%     72.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 85914750     27.71%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            310035010                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.190355                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.945019                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 36438516                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             100672732                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 164105371                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               4706760                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                4111631                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              876235114                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                  1005                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                4111631                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 40855551                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                44279722                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       10981847                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 163785428                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              46020831                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              872430616                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 10252                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               35253394                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               3952381                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents         31994944                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          1394146617                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            2488353855                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       2488353319                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               536                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1347546781                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 46599829                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             470336                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         478135                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  48126988                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             18909339                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10455877                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1294020                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1017517                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  865756561                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1721302                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 864328719                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            124616                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        26046990                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     53600910                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         205527                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     310035010                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.787842                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.396151                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           102334281     33.01%     33.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            23751530      7.66%     40.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            19011662      6.13%     46.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7830278      2.53%     49.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            80611792     26.00%     75.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3104970      1.00%     76.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72755101     23.47%     99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              522761      0.17%     99.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              112635      0.04%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       310035010                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  164564      7.88%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.88% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1763434     84.48%     92.37% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                159280      7.63%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            297202      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             829439322     95.96%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             25154463      2.91%     98.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9437732      1.09%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              864328719                       # Type of FU issued
system.cpu.iq.rate                           1.827541                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2087278                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.002415                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2041042185                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         893535851                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    853927067                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 224                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                246                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           54                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              866118699                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      96                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1579181                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3618734                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        20083                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        12084                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2054359                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      7821519                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          4487                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                4111631                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                27910035                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1927143                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           867477863                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            297836                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              18909339                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10455877                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             883178                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 975186                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 15536                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          12084                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         697834                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       626380                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1324214                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             862437508                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              24726867                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1891210                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     33920253                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 86495383                       # Number of branches executed
system.cpu.iew.exec_stores                    9193386                       # Number of stores executed
system.cpu.iew.exec_rate                     1.823543                       # Inst execution rate
system.cpu.iew.wb_sent                      861952908                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     853927121                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 669642895                       # num instructions producing a value
system.cpu.iew.wb_consumers                1918737755                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.805548                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.349002                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      426515724                       # The number of committed instructions
system.cpu.commit.commitCommittedOps        840516219                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        26857823                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1515773                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1181578                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    305938932                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.747333                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.861326                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    125006118     40.86%     40.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     14720749      4.81%     45.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4254060      1.39%     47.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     76641454     25.05%     72.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      3896789      1.27%     73.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1794252      0.59%     73.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1101361      0.36%     74.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     71996786     23.53%     97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6527363      2.13%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    305938932                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            426515724                       # Number of instructions committed
system.cpu.commit.committedOps              840516219                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       23692120                       # Number of memory references committed
system.cpu.commit.loads                      15290602                       # Number of loads committed
system.cpu.commit.membars                      781565                       # Number of memory barriers committed
system.cpu.commit.branches                   85505775                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 768334838                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6527363                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1166706140                       # The number of ROB reads
system.cpu.rob.rob_writes                  1738874776                       # The number of ROB writes
system.cpu.timesIdled                         2996123                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       162911165                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9872855838                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   426515724                       # Number of Instructions Simulated
system.cpu.committedOps                     840516219                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             426515724                       # Number of Instructions Simulated
system.cpu.cpi                               1.108860                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.108860                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.901827                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.901827                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2163141042                       # number of integer regfile reads
system.cpu.int_regfile_writes              1362663536                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        54                       # number of floating regfile reads
system.cpu.misc_regfile_reads               281062978                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 403820                       # number of misc regfile writes
system.cpu.icache.replacements                1070658                       # number of replacements
system.cpu.icache.tagsinuse                510.425099                       # Cycle average of tags in use
system.cpu.icache.total_refs                  8224431                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1071170                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.677989                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            56932899000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.425099                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996924                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996924                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      8224431                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8224431                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       8224431                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8224431                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      8224431                       # number of overall hits
system.cpu.icache.overall_hits::total         8224431                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1140947                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1140947                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1140947                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1140947                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1140947                       # number of overall misses
system.cpu.icache.overall_misses::total       1140947                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  18841256486                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  18841256486                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  18841256486                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  18841256486                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  18841256486                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  18841256486                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9365378                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9365378                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9365378                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9365378                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9365378                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9365378                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.121826                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.121826                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.121826                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.121826                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.121826                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.121826                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16513.700011                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16513.700011                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16513.700011                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16513.700011                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16513.700011                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16513.700011                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      3271992                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               399                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  8200.481203                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks         1605                       # number of writebacks
system.cpu.icache.writebacks::total              1605                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        69655                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        69655                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        69655                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        69655                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        69655                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        69655                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1071292                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1071292                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1071292                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1071292                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1071292                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1071292                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14719464992                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  14719464992                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14719464992                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  14719464992                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14719464992                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  14719464992                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114389                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114389                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114389                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.114389                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114389                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.114389                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13739.918708                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13739.918708                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13739.918708                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13739.918708                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13739.918708                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13739.918708                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements        10504                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        6.031363                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs          31807                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs        10516                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         3.024629                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5135227037000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.031363                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.376960                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.376960                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        31848                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        31848                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        31851                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        31851                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        31851                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        31851                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        11386                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        11386                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        11386                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        11386                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        11386                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        11386                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    182254500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    182254500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    182254500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    182254500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    182254500                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    182254500                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        43234                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        43234                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        43237                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        43237                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        43237                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        43237                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.263358                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.263358                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.263339                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.263339                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.263339                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.263339                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16006.894432                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16006.894432                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16006.894432                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16006.894432                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16006.894432                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16006.894432                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1641                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1641                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        11386                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        11386                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        11386                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        11386                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        11386                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        11386                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    147453030                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    147453030                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    147453030                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    147453030                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    147453030                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    147453030                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.263358                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.263358                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.263339                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.263339                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.263339                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.263339                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12950.380292                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12950.380292                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12950.380292                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12950.380292                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12950.380292                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12950.380292                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements       117278                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse       13.523999                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs         136775                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs       117293                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.166097                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5112876101000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    13.523999                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.845250                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.845250                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       136779                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       136779                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       136779                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       136779                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       136779                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       136779                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       118304                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total       118304                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       118304                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total       118304                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       118304                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total       118304                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   2123660000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   2123660000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   2123660000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total   2123660000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   2123660000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total   2123660000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       255083                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       255083                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       255083                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       255083                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       255083                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       255083                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.463786                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.463786                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.463786                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.463786                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.463786                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.463786                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17950.872329                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17950.872329                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17950.872329                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17950.872329                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17950.872329                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17950.872329                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        37674                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        37674                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       118304                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       118304                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       118304                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total       118304                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       118304                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total       118304                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1766049009                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1766049009                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1766049009                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1766049009                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1766049009                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1766049009                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.463786                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.463786                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.463786                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.463786                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.463786                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.463786                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14928.058299                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14928.058299                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14928.058299                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1673136                       # number of replacements
system.cpu.dcache.tagsinuse                511.997556                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 19006106                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1673648                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  11.356095                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               36854000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.997556                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     10928708                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10928708                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8074811                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8074811                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      19003519                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19003519                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19003519                       # number of overall hits
system.cpu.dcache.overall_hits::total        19003519                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2430538                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2430538                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       317333                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       317333                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2747871                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2747871                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2747871                       # number of overall misses
system.cpu.dcache.overall_misses::total       2747871                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  45186101000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  45186101000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10603069990                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10603069990                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  55789170990                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  55789170990                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  55789170990                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  55789170990                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13359246                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13359246                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8392144                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8392144                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21751390                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21751390                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21751390                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21751390                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.181937                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.181937                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037813                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037813                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.126331                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.126331                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.126331                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.126331                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18590.987263                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18590.987263                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33413.070781                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33413.070781                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20302.689242                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20302.689242                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20302.689242                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20302.689242                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     27875990                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              4957                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  5623.560621                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1572269                       # number of writebacks
system.cpu.dcache.writebacks::total           1572269                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1049151                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1049151                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22726                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        22726                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1071877                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1071877                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1071877                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1071877                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1381387                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1381387                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       294607                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       294607                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1675994                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1675994                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1675994                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1675994                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23290713035                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  23290713035                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9337845997                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   9337845997                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  32628559032                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  32628559032                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  32628559032                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  32628559032                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  85207723000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  85207723000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1386731000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1386731000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86594454000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  86594454000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103403                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103403                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035105                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.035105                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077052                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.077052                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077052                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077052                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16860.382380                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16860.382380                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31695.940684                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31695.940684                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19468.183676                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19468.183676                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19468.183676                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19468.183676                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------