path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.140938                       # Number of seconds simulated
sim_ticks                                5140937585000                       # Number of ticks simulated
final_tick                               5140937585000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 121697                       # Simulator instruction rate (inst/s)
host_op_rate                                   240559                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1534230705                       # Simulator tick rate (ticks/s)
host_mem_usage                                 773616                       # Number of bytes of host memory used
host_seconds                                  3350.82                       # Real time elapsed on the host
sim_insts                                   407786881                       # Number of instructions simulated
sim_ops                                     806071515                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2479872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1026240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10765120                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14275328                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1026240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1026240                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9536256                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9536256                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        38748                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           58                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16035                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168205                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                223052                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149004                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149004                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       482377                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            722                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               199621                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2093999                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2776795                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          199621                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             199621                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1854964                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1854964                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1854964                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       482377                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           722                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              199621                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2093999                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4631759                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        223052                       # Total number of read requests seen
system.physmem.writeReqs                       149004                       # Total number of write requests seen
system.physmem.cpureqs                         373790                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     14275328                       # Total number of bytes read from memory
system.physmem.bytesWritten                   9536256                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               14275328                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                9536256                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       71                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               1726                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 13636                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 12914                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 13124                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 16345                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 13470                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 13111                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 13382                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 16266                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 13519                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 13235                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                13394                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                15885                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                13088                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                12601                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                13202                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                15809                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  8837                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  8387                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  8583                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 11810                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  8818                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  8522                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  8723                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 11661                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  8790                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  8601                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 8761                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                11230                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 8431                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 8093                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 8583                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                11174                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           8                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5140937531500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  223052                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 149004                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    172997                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     18175                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      7573                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3487                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3011                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2422                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1913                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1861                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1763                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1672                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1114                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1019                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      962                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      902                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      823                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      817                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      907                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      865                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      412                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      253                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5675                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      6279                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      6374                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      6421                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      6454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      6466                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      6471                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      6479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      804                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        8                       # What write queue length does an incoming req see
system.physmem.totQLat                     4794975750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                9301923250                       # Sum of mem lat for all requests
system.physmem.totBusLat                   1114905000                       # Total cycles spent in databus access
system.physmem.totBankLat                  3392042500                       # Total cycles spent in bank access
system.physmem.avgQLat                       21503.97                       # Average queueing delay per request
system.physmem.avgBankLat                    15212.25                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  41716.21                       # Average memory access latency
system.physmem.avgRdBW                           2.78                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.78                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.85                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                        15.58                       # Average write queue length over time
system.physmem.readRowHits                     191257                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    105612                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   85.77                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  70.88                       # Row buffer hit rate for writes
system.physmem.avgGap                     13817644.47                       # Average gap between requests
system.iocache.replacements                     47576                       # number of replacements
system.iocache.tagsinuse                     0.128763                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47592                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              4991974997000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.128763                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.008048                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.008048                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          911                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              911                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47631                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47631                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47631                       # number of overall misses
system.iocache.overall_misses::total            47631                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    147497397                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    147497397                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10072244306                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10072244306                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  10219741703                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10219741703                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  10219741703                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10219741703                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          911                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            911                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47631                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47631                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47631                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47631                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 161907.131723                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 161907.131723                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215587.420933                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 215587.420933                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214560.721022                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 214560.721022                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214560.721022                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 214560.721022                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        139153                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                12645                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    11.004587                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          911                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          911                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47631                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47631                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47631                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47631                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    100104427                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    100104427                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   7641446543                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   7641446543                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   7741550970                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   7741550970                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   7741550970                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   7741550970                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 109884.113063                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 109884.113063                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163558.359225                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 163558.359225                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 162531.774895                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 162531.774895                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                85620726                       # Number of BP lookups
system.cpu.branchPred.condPredicted          85620726                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            882198                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79268619                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                77534559                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.812426                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1442315                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             180251                       # Number of incorrect RAS predictions.
system.cpu.numCycles                        447791761                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           25559948                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      422856490                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85620726                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           78976874                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     162677741                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4000997                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                      98298                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               65919320                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                43594                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         86507                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          459                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8492083                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                383635                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    2345                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          257461374                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.243647                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.415529                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 95198026     36.98%     36.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1534816      0.60%     37.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 71825104     27.90%     65.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   895357      0.35%     65.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1570607      0.61%     66.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2391332      0.93%     67.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1020158      0.40%     67.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1325162      0.51%     68.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81700812     31.73%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            257461374                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.191207                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.944315                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29461192                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              63064302                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 158550724                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3309649                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3075507                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              832761340                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   863                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3075507                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 32153278                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                38465118                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       12079112                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158824437                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              12863922                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              829829025                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 19879                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                6055166                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4924546                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents            11525                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           991492877                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1800847756                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1800847292                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               464                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             963999366                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 27493506                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             456551                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         462682                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  29304477                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             16752339                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             9837983                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1099709                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           928773                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  825036488                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1186686                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 821069910                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            146070                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        19309743                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     29357166                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         131932                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     257461374                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.189099                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.383585                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            71259249     27.68%     27.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15575755      6.05%     33.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10479111      4.07%     37.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7383615      2.87%     40.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            75752504     29.42%     70.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3772068      1.47%     71.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72307575     28.08%     99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              782694      0.30%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              148803      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       257461374                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  356313     33.63%     33.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                    241      0.02%     33.66% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                    2452      0.23%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 547502     51.68%     85.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                152922     14.43%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            308526      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             793557907     96.65%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               150412      0.02%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                124298      0.02%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             17694567      2.16%     98.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9234200      1.12%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              821069910                       # Type of FU issued
system.cpu.iq.rate                           1.833598                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1059430                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001290                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1900915279                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         845543458                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    817157785                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 194                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                212                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           52                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              821820724                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      90                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1686147                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2748440                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        17101                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11930                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1411969                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1931504                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         11624                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3075507                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                26873503                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2150322                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           826223174                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            241070                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              16752339                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              9837983                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             692103                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1621529                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 12267                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11930                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         498132                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       506603                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1004735                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             819660888                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17391685                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1409021                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26440023                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83107253                       # Number of branches executed
system.cpu.iew.exec_stores                    9048338                       # Number of stores executed
system.cpu.iew.exec_rate                     1.830451                       # Inst execution rate
system.cpu.iew.wb_sent                      819258374                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     817157837                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 638799704                       # num instructions producing a value
system.cpu.iew.wb_consumers                1044337102                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.824861                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611680                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        20042352                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1054753                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            891546                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    254385866                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     3.168696                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.858566                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     82972146     32.62%     32.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11724447      4.61%     37.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3813249      1.50%     38.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74747378     29.38%     68.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2384925      0.94%     69.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1476326      0.58%     69.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       865615      0.34%     69.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70850824     27.85%     97.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5550956      2.18%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    254385866                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407786881                       # Number of instructions committed
system.cpu.commit.committedOps              806071515                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22429911                       # Number of memory references committed
system.cpu.commit.loads                      14003897                       # Number of loads committed
system.cpu.commit.membars                      474463                       # Number of memory barriers committed
system.cpu.commit.branches                   82163817                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735061477                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1156045                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               5550956                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1074870508                       # The number of ROB reads
system.cpu.rob.rob_writes                  1655318425                       # The number of ROB writes
system.cpu.timesIdled                         1256763                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       190330387                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9834088814                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407786881                       # Number of Instructions Simulated
system.cpu.committedOps                     806071515                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             407786881                       # Number of Instructions Simulated
system.cpu.cpi                               1.098102                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.098102                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.910662                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.910662                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1504614065                       # number of integer regfile reads
system.cpu.int_regfile_writes               975429838                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        52                       # number of floating regfile reads
system.cpu.misc_regfile_reads               264130300                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 403010                       # number of misc regfile writes
system.cpu.icache.replacements                 955437                       # number of replacements
system.cpu.icache.tagsinuse                509.903328                       # Cycle average of tags in use
system.cpu.icache.total_refs                  7482159                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 955949                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.826944                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle           146514700000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     509.903328                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.995905                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.995905                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7482159                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7482159                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7482159                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7482159                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7482159                       # number of overall hits
system.cpu.icache.overall_hits::total         7482159                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1009922                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1009922                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1009922                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1009922                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1009922                       # number of overall misses
system.cpu.icache.overall_misses::total       1009922                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  13938284992                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  13938284992                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  13938284992                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  13938284992                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  13938284992                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  13938284992                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8492081                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8492081                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8492081                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8492081                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8492081                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8492081                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.118925                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.118925                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.118925                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.118925                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.118925                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.118925                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.348017                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13801.348017                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.348017                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13801.348017                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.348017                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13801.348017                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         8199                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               203                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    40.389163                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53908                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        53908                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        53908                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        53908                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        53908                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        53908                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       956014                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       956014                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       956014                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       956014                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       956014                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       956014                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11502740492                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11502740492                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11502740492                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11502740492                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11502740492                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11502740492                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.112577                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.112577                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.112577                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.112577                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.112577                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.112577                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.979126                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.979126                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.979126                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.979126                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.979126                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.979126                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements         7960                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        6.326712                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs          20386                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs         7973                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         2.556879                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5107329698000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.326712                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.395420                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.395420                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        20403                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        20403                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        20405                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        20405                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        20405                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        20405                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         8843                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         8843                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         8843                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         8843                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         8843                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         8843                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     96821500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     96821500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     96821500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     96821500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     96821500                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     96821500                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        29246                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        29246                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        29248                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        29248                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        29248                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        29248                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.302366                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.302366                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.302345                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.302345                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.302345                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.302345                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10948.942667                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10948.942667                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10948.942667                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10948.942667                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10948.942667                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10948.942667                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1394                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1394                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         8843                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         8843                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         8843                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         8843                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         8843                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         8843                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     79135500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     79135500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     79135500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     79135500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     79135500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     79135500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.302366                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.302366                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.302345                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.302345                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.302345                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.302345                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8948.942667                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8948.942667                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8948.942667                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8948.942667                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8948.942667                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8948.942667                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements        67560                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse       14.837353                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs          92239                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs        67575                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.364987                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5100574572500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    14.837353                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.927335                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.927335                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        92240                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        92240                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        92240                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        92240                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        92240                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        92240                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        68644                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        68644                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        68644                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        68644                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        68644                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        68644                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    852599000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    852599000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    852599000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    852599000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    852599000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    852599000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       160884                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       160884                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       160884                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       160884                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       160884                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       160884                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.426668                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.426668                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.426668                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.426668                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.426668                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.426668                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12420.590292                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12420.590292                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12420.590292                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12420.590292                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12420.590292                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12420.590292                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        19876                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        19876                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        68644                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        68644                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        68644                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        68644                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        68644                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        68644                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    715311000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    715311000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    715311000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    715311000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    715311000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    715311000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.426668                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.426668                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.426668                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.426668                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.426668                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.426668                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10420.590292                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10420.590292                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10420.590292                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1655094                       # number of replacements
system.cpu.dcache.tagsinuse                511.995445                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 19021390                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1655606                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  11.489080                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               27980000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.995445                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     10917270                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10917270                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8101435                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8101435                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      19018705                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19018705                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19018705                       # number of overall hits
system.cpu.dcache.overall_hits::total        19018705                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2239579                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2239579                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       315092                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       315092                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2554671                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2554671                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2554671                       # number of overall misses
system.cpu.dcache.overall_misses::total       2554671                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  31946998000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  31946998000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9622210995                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9622210995                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  41569208995                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  41569208995                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  41569208995                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  41569208995                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13156849                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13156849                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8416527                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8416527                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21573376                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21573376                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21573376                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21573376                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.170222                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.170222                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037437                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037437                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.118418                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.118418                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118418                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118418                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14264.733684                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14264.733684                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30537.782600                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30537.782600                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16271.844396                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16271.844396                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16271.844396                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16271.844396                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       387071                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             42390                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.131187                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1557214                       # number of writebacks
system.cpu.dcache.writebacks::total           1557214                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       870911                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       870911                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        25892                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        25892                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       896803                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       896803                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       896803                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       896803                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1368668                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1368668                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289200                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       289200                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1657868                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1657868                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1657868                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1657868                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17401159000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17401159000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8794383495                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8794383495                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26195542495                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  26195542495                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26195542495                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26195542495                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97349101500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97349101500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2522345500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2522345500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99871447000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99871447000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104027                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104027                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034361                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034361                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076848                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.076848                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076848                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.076848                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12713.937200                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12713.937200                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30409.348185                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30409.348185                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15800.740768                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15800.740768                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15800.740768                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15800.740768                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                111963                       # number of replacements
system.cpu.l2cache.tagsinuse             64818.241357                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3779325                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                176193                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 21.449916                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50535.271880                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker    14.689116                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.441967                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   3088.733265                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  11179.105128                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.771107                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000224                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000007                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.047130                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.170580                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.989048                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        63019                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         6673                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       939861                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1331810                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2341363                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1578484                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1578484                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          313                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          313                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       154035                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       154035                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        63019                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         6673                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       939861                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1485845                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2495398                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        63019                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         6673                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       939861                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1485845                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2495398                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           58                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16036                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        36136                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        52236                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1469                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1469                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133013                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133013                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           58                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16036                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169149                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        185249                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           58                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16036                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169149                       # number of overall misses
system.cpu.l2cache.overall_misses::total       185249                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4739500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       386000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1102660000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2500024999                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3607810499                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     18004500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     18004500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6917223500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   6917223500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4739500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       386000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1102660000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   9417248499                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10525033999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4739500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       386000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1102660000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   9417248499                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10525033999                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        63077                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         6679                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       955897                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1367946                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2393599                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1578484                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1578484                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1782                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1782                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287048                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287048                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        63077                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         6679                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       955897                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1654994                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2680647                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        63077                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         6679                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       955897                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1654994                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2680647                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000898                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016776                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026416                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021823                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.824355                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.824355                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.463382                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.463382                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000898                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016776                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102205                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.069106                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000898                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016776                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102205                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.069106                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81715.517241                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64333.333333                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68761.536543                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69183.777922                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69067.510893                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12256.296801                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12256.296801                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.116139                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.116139                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81715.517241                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64333.333333                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68761.536543                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55674.278293                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56815.604937                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81715.517241                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64333.333333                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68761.536543                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55674.278293                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56815.604937                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102337                       # number of writebacks
system.cpu.l2cache.writebacks::total           102337                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           58                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16035                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36136                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        52235                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1469                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1469                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133013                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133013                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           58                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16035                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169149                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       185248                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           58                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16035                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169149                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       185248                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4016555                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       310006                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    903103756                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2050826327                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2958256644                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15725947                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15725947                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5276958842                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5276958842                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4016555                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       310006                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    903103756                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7327785169                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8235215486                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4016555                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       310006                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    903103756                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7327785169                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8235215486                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89236811500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89236811500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2357396500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2357396500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91594208000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91594208000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000920                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000898                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016775                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026416                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021823                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.824355                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.824355                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.463382                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.463382                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000920                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000898                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016775                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102205                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.069106                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000920                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000898                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016775                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102205                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.069106                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 51667.666667                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56320.783037                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56752.997758                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56633.610491                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10705.205582                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10705.205582                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39672.504507                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39672.504507                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 51667.666667                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56320.783037                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43321.480878                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44455.084460                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 51667.666667                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56320.783037                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43321.480878                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44455.084460                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------