path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.132866                       # Number of seconds simulated
sim_ticks                                5132865528000                       # Number of ticks simulated
final_tick                               5132865528000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  61482                       # Simulator instruction rate (inst/s)
host_op_rate                                   121532                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              773550742                       # Simulator tick rate (ticks/s)
host_mem_usage                                 771808                       # Number of bytes of host memory used
host_seconds                                  6635.46                       # Real time elapsed on the host
sim_insts                                   407963797                       # Number of instructions simulated
sim_ops                                     806422961                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2435200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1080768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10867584                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14387264                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1080768                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1080768                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9583040                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9583040                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        38050                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           52                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16887                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             169806                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                224801                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149735                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149735                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       474433                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            648                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               210558                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2117255                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2802969                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          210558                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             210558                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1866996                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1866996                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1866996                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       474433                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           648                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              210558                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2117255                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4669965                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        224801                       # Total number of read requests seen
system.physmem.writeReqs                       149735                       # Total number of write requests seen
system.physmem.cpureqs                         378687                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     14387264                       # Total number of bytes read from memory
system.physmem.bytesWritten                   9583040                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               14387264                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                9583040                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       88                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4143                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 14181                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 13154                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 13072                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 16238                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 13617                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 13098                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 13611                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 16569                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 13873                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 13226                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                13363                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                15769                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                13267                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                12663                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                13279                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                15733                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  9192                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  8646                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  8408                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 11578                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  8737                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  8467                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  8901                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 11873                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  9014                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  8670                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 8751                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                11255                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 8399                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 8107                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 8591                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                11146                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           8                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5132865474500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  224801                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 149735                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    174182                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     19233                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      7394                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3462                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2978                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2373                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1871                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1802                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1730                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1664                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1011                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      945                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      877                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      806                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      787                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      920                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      857                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      409                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      232                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5387                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5729                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      6323                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      6403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      6452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      6475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      6492                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      6496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      6498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      782                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       12                       # What write queue length does an incoming req see
system.physmem.totQLat                     4748150250                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                9279735250                       # Sum of mem lat for all requests
system.physmem.totBusLat                   1123565000                       # Total cycles spent in databus access
system.physmem.totBankLat                  3408020000                       # Total cycles spent in bank access
system.physmem.avgQLat                       21129.84                       # Average queueing delay per request
system.physmem.avgBankLat                    15166.10                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  41295.94                       # Average memory access latency
system.physmem.avgRdBW                           2.80                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.87                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.80                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.87                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                        10.74                       # Average write queue length over time
system.physmem.readRowHits                     193533                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    105971                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   86.12                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  70.77                       # Row buffer hit rate for writes
system.physmem.avgGap                     13704598.42                       # Average gap between requests
system.iocache.replacements                     47575                       # number of replacements
system.iocache.tagsinuse                     0.104035                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47591                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              4991882227000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.104035                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.006502                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.006502                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          910                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              910                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47630                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47630                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47630                       # number of overall misses
system.iocache.overall_misses::total            47630                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    142432660                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    142432660                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10000305290                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10000305290                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  10142737950                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10142737950                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  10142737950                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10142737950                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          910                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            910                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47630                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47630                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47630                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47630                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156519.406593                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 156519.406593                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214047.630351                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 214047.630351                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 212948.518791                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 212948.518791                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 212948.518791                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 212948.518791                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        135861                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                12418                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.940651                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          910                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47630                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47630                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47630                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47630                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     95090941                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     95090941                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   7569522729                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   7569522729                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   7664613670                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   7664613670                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   7664613670                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   7664613670                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104495.539560                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 104495.539560                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162018.894028                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 162018.894028                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 160919.875499                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 160919.875499                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                86256793                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86256793                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1113068                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             81525739                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                79259204                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.219853                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu.numCycles                        448546895                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27629675                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      426131263                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86256793                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79259204                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     163637829                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4743979                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     122519                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               63152705                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                36413                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         51550                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          359                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9043434                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                488848                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    3024                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          258223805                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.257780                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.417802                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 95012138     36.79%     36.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1565899      0.61%     37.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 71926197     27.85%     65.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   935616      0.36%     65.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1604506      0.62%     66.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2433567      0.94%     67.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1079084      0.42%     67.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1383528      0.54%     68.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 82283270     31.87%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            258223805                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.192303                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.950026                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 31307096                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              60630076                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 159436775                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3257103                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3592755                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              838113616                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   880                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3592755                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 34040592                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                37476959                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       11041434                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 159631550                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              12440515                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              834468110                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 19385                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                5834152                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4771877                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents             8971                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           996054249                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1811560635                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1811560099                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               536                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964410768                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 31643474                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             457361                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         464527                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  28752334                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17095902                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10132687                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1166436                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           902107                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  828339786                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1247404                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 823331592                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            149918                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        22245950                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33811662                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         194652                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     258223805                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.188442                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.385103                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            71699549     27.77%     27.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15529974      6.01%     33.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10286408      3.98%     37.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7471868      2.89%     40.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            75917572     29.40%     70.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3857166      1.49%     71.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72524361     28.09%     99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              784342      0.30%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              152565      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       258223805                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  368681     34.39%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 552933     51.58%     85.98% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                150329     14.02%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            310005      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             795767028     96.65%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             17865255      2.17%     98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9389304      1.14%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              823331592                       # Type of FU issued
system.cpu.iq.rate                           1.835553                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1071943                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001302                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1906239242                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         851843261                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    818849223                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 219                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                250                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           54                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              824093432                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      98                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1643495                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3116410                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        23570                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11612                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1711798                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1932508                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         11844                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3592755                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                26248050                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2110636                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           829587190                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            321004                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17095902                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10132687                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             717072                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1612321                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 11848                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11612                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         657039                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       595254                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1252293                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             821445338                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17448687                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1886253                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26607218                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83228491                       # Number of branches executed
system.cpu.iew.exec_stores                    9158531                       # Number of stores executed
system.cpu.iew.exec_rate                     1.831348                       # Inst execution rate
system.cpu.iew.wb_sent                      820983226                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     818849277                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 639988645                       # num instructions producing a value
system.cpu.iew.wb_consumers                1045811759                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.825560                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611954                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        23057499                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1052750                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1117600                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    254631050                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     3.167025                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.854459                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     82837862     32.53%     32.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11822724      4.64%     37.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3905327      1.53%     38.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74951929     29.44%     68.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2438342      0.96%     69.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1480698      0.58%     69.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       927919      0.36%     70.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70920568     27.85%     97.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5345681      2.10%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    254631050                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407963797                       # Number of instructions committed
system.cpu.commit.committedOps              806422961                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22400378                       # Number of memory references committed
system.cpu.commit.loads                      13979489                       # Number of loads committed
system.cpu.commit.membars                      473507                       # Number of memory barriers committed
system.cpu.commit.branches                   82198469                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735362199                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               5345681                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1078687614                       # The number of ROB reads
system.cpu.rob.rob_writes                  1662572605                       # The number of ROB writes
system.cpu.timesIdled                         1222238                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       190323090                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9817181581                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407963797                       # Number of Instructions Simulated
system.cpu.committedOps                     806422961                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             407963797                       # Number of Instructions Simulated
system.cpu.cpi                               1.099477                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.099477                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.909523                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.909523                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1507059295                       # number of integer regfile reads
system.cpu.int_regfile_writes               977046319                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        54                       # number of floating regfile reads
system.cpu.misc_regfile_reads               264741173                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 402265                       # number of misc regfile writes
system.cpu.icache.replacements                1056074                       # number of replacements
system.cpu.icache.tagsinuse                510.395640                       # Cycle average of tags in use
system.cpu.icache.total_refs                  7921465                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1056586                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.497227                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            56044666000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.395640                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996866                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996866                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7921465                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7921465                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7921465                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7921465                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7921465                       # number of overall hits
system.cpu.icache.overall_hits::total         7921465                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1121968                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1121968                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1121968                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1121968                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1121968                       # number of overall misses
system.cpu.icache.overall_misses::total       1121968                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  15396039491                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  15396039491                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  15396039491                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  15396039491                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  15396039491                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  15396039491                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9043433                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9043433                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9043433                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9043433                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9043433                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9043433                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124064                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.124064                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.124064                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.124064                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.124064                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.124064                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13722.351699                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13722.351699                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13722.351699                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13722.351699                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13722.351699                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13722.351699                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        11326                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               262                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    43.229008                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        62943                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        62943                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        62943                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        62943                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        62943                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        62943                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1059025                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1059025                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1059025                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1059025                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1059025                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1059025                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12680665992                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12680665992                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12680665992                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12680665992                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12680665992                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12680665992                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.117104                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.117104                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.117104                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.117104                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.117104                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.117104                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11973.906180                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11973.906180                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11973.906180                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11973.906180                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11973.906180                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11973.906180                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements         9902                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        6.007248                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs          25368                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs         9915                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         2.558548                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5106962474500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.007248                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.375453                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.375453                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        25400                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        25400                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        25402                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        25402                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        25402                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        25402                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        10789                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        10789                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        10789                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        10789                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        10789                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        10789                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    118480500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    118480500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    118480500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    118480500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    118480500                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    118480500                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        36189                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        36189                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        36191                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        36191                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        36191                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        36191                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.298129                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.298129                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.298113                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.298113                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.298113                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.298113                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10981.601631                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10981.601631                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10981.601631                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10981.601631                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10981.601631                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10981.601631                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         2074                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         2074                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        10789                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        10789                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        10789                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        10789                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        10789                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        10789                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     96902500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     96902500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     96902500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     96902500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     96902500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     96902500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.298129                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.298129                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.298113                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.298113                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.298113                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.298113                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8981.601631                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8981.601631                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8981.601631                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8981.601631                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8981.601631                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8981.601631                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements       112679                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse       13.888368                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs         129664                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs       112694                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.150585                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5099752322000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    13.888368                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.868023                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.868023                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       129683                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       129683                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       129683                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       129683                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       129683                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       129683                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       113702                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total       113702                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       113702                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total       113702                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       113702                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total       113702                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1421375500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1421375500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1421375500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total   1421375500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1421375500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total   1421375500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       243385                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       243385                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       243385                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       243385                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       243385                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       243385                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.467169                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.467169                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.467169                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.467169                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.467169                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.467169                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12500.883889                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12500.883889                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12500.883889                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12500.883889                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12500.883889                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12500.883889                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        35808                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        35808                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       113702                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       113702                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       113702                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total       113702                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       113702                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total       113702                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1193971500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1193971500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1193971500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1193971500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1193971500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1193971500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.467169                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.467169                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.467169                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.467169                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.467169                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.467169                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10500.883889                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10500.883889                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10500.883889                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10500.883889                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1659172                       # number of replacements
system.cpu.dcache.tagsinuse                511.998283                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 19096669                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1659684                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  11.506208                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               27985000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.998283                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999997                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999997                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     10998697                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10998697                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8092860                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8092860                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      19091557                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19091557                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19091557                       # number of overall hits
system.cpu.dcache.overall_hits::total        19091557                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2244277                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2244277                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       318772                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       318772                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2563049                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2563049                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2563049                       # number of overall misses
system.cpu.dcache.overall_misses::total       2563049                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  32186629000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  32186629000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9715417494                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9715417494                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  41902046494                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  41902046494                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  41902046494                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  41902046494                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13242974                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13242974                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8411632                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8411632                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21654606                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21654606                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21654606                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21654606                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.169469                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.169469                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037897                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037897                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.118360                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.118360                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118360                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118360                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14341.647221                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14341.647221                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30477.637603                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30477.637603                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16348.515574                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16348.515574                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16348.515574                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16348.515574                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       394709                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             43025                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.173945                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1560811                       # number of writebacks
system.cpu.dcache.writebacks::total           1560811                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       872480                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       872480                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        26264                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        26264                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       898744                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       898744                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       898744                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       898744                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1371797                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1371797                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       292508                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       292508                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1664305                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1664305                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1664305                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1664305                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17453179000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17453179000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8875888494                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8875888494                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26329067494                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  26329067494                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26329067494                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26329067494                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97298479500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97298479500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2473755000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2473755000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99772234500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99772234500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103587                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103587                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034774                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034774                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076857                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.076857                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076857                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.076857                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12722.858411                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12722.858411                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30344.088004                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30344.088004                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15819.857234                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15819.857234                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15819.857234                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15819.857234                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                113709                       # number of replacements
system.cpu.l2cache.tagsinuse             64835.556178                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3943740                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                177736                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 22.188752                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50100.135073                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker     8.974222                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.131215                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   3272.117566                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  11454.198102                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.764467                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000137                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.049929                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.174777                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.989312                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       105558                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         8113                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst      1039658                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1333728                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2487057                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1598693                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1598693                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          321                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          321                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       154593                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       154593                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       105558                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         8113                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      1039658                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1488321                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2641650                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       105558                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         8113                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      1039658                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1488321                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2641650                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           52                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16888                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        36900                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        53846                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         3866                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         3866                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133854                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133854                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           52                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16888                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       170754                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        187700                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           52                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16888                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       170754                       # number of overall misses
system.cpu.l2cache.overall_misses::total       187700                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4568000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       389500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1172288500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2518183499                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3695429499                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17446500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     17446500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6941993500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   6941993500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4568000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       389500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1172288500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   9460176999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10637422999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4568000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       389500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1172288500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   9460176999                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10637422999                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       105610                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         8119                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1056546                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1370628                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2540903                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1598693                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1598693                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4187                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         4187                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       288447                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       288447                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       105610                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         8119                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1056546                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1659075                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2829350                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       105610                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         8119                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1056546                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1659075                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2829350                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000492                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000739                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.015984                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026922                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021192                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.923334                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.923334                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.464051                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.464051                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000492                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000739                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.015984                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102921                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.066340                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000492                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000739                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.015984                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102921                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.066340                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87846.153846                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69415.472525                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68243.455257                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68629.601066                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  4512.803932                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  4512.803932                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51862.428467                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51862.428467                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87846.153846                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69415.472525                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55402.374170                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56672.472025                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87846.153846                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69415.472525                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55402.374170                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56672.472025                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       103068                       # number of writebacks
system.cpu.l2cache.writebacks::total           103068                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            2                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           52                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16887                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36899                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        53844                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         3866                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         3866                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133854                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133854                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           52                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16887                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       170753                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       187698                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           52                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16887                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       170753                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       187698                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3916050                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       314255                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    962195275                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2059471232                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3025896812                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     39657846                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     39657846                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5291032825                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5291032825                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3916050                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       314255                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    962195275                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7350504057                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8316929637                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3916050                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       314255                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    962195275                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7350504057                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8316929637                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89189069500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89189069500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2311324000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2311324000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91500393500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91500393500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000492                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000739                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.015983                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026921                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021191                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.923334                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.923334                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464051                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464051                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000492                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000739                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.015983                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102921                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.066340                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000492                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000739                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.015983                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102921                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.066340                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56978.461242                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55813.741077                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56197.474408                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10258.108122                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10258.108122                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39528.387833                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39528.387833                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56978.461242                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43047.583685                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44310.166528                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56978.461242                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43047.583685                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44310.166528                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------