path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.141960                       # Number of seconds simulated
sim_ticks                                5141959613000                       # Number of ticks simulated
final_tick                               5141959613000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 152486                       # Simulator instruction rate (inst/s)
host_op_rate                                   301416                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1922658876                       # Simulator tick rate (ticks/s)
host_mem_usage                                 770128                       # Number of bytes of host memory used
host_seconds                                  2674.40                       # Real time elapsed on the host
sim_insts                                   407807707                       # Number of instructions simulated
sim_ops                                     806107146                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide      2476992                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1035072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10749056                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14265280                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1035072                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1035072                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9521344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9521344                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        38703                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           60                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16173                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             167954                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                222895                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          148771                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               148771                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       481721                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            747                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               201299                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2090459                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2774289                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          201299                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             201299                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1851696                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1851696                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1851696                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       481721                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           747                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              201299                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2090459                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4625984                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        222895                       # Number of read requests accepted
system.physmem.writeReqs                       148771                       # Number of write requests accepted
system.physmem.readBursts                      222895                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     148771                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 14256576                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8704                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9520064                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  14265280                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9521344                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      136                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           1680                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               14406                       # Per bank write bursts
system.physmem.perBankRdBursts::1               13692                       # Per bank write bursts
system.physmem.perBankRdBursts::2               14137                       # Per bank write bursts
system.physmem.perBankRdBursts::3               13444                       # Per bank write bursts
system.physmem.perBankRdBursts::4               14027                       # Per bank write bursts
system.physmem.perBankRdBursts::5               13372                       # Per bank write bursts
system.physmem.perBankRdBursts::6               13359                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13805                       # Per bank write bursts
system.physmem.perBankRdBursts::8               13762                       # Per bank write bursts
system.physmem.perBankRdBursts::9               13592                       # Per bank write bursts
system.physmem.perBankRdBursts::10              13956                       # Per bank write bursts
system.physmem.perBankRdBursts::11              13564                       # Per bank write bursts
system.physmem.perBankRdBursts::12              14528                       # Per bank write bursts
system.physmem.perBankRdBursts::13              14698                       # Per bank write bursts
system.physmem.perBankRdBursts::14              14291                       # Per bank write bursts
system.physmem.perBankRdBursts::15              14126                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9807                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9166                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9421                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8835                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9422                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8917                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8763                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9221                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9116                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9134                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9470                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8904                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9718                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9806                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9580                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9471                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    5141959559500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  222895                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 148771                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    173187                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     13769                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      5947                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3181                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3035                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      3711                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      3299                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2487                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1947                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1694                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1507                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1005                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      833                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      764                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      718                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      557                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      456                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      376                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       24                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1667                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1818                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6295                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6657                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6807                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6895                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7974                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8492                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8899                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     9232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     9176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1747                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1906                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1843                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1738                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1321                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1057                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      845                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      632                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      196                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        74587                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      318.776409                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     185.138812                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     338.199277                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          28275     37.91%     37.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        16828     22.56%     60.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7503     10.06%     70.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4244      5.69%     76.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3057      4.10%     80.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2068      2.77%     83.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1382      1.85%     84.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1175      1.58%     86.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        10055     13.48%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          74587                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          8285                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.884007                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      527.034010                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           8284     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            8285                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          8285                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.954255                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.428609                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        5.676130                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            6158     74.33%     74.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            1338     16.15%     90.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              52      0.63%     91.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              77      0.93%     92.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              47      0.57%     92.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              55      0.66%     93.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29             103      1.24%     94.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31              89      1.07%     95.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33              47      0.57%     96.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35              58      0.70%     96.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37              37      0.45%     97.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39              45      0.54%     97.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41              69      0.83%     98.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43              27      0.33%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45              11      0.13%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47              16      0.19%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49              22      0.27%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51               4      0.05%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53               7      0.08%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54-55               3      0.04%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-57               2      0.02%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59               3      0.04%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-61               5      0.06%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::62-63               4      0.05%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-65               3      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::66-67               1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-81               1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-89               1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            8285                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4923822749                       # Total ticks spent queuing
system.physmem.totMemAccLat                9100553999                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1113795000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       22103.81                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  40853.81                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.77                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.77                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.85                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.83                       # Average write queue length when enqueuing
system.physmem.readRowHits                     186870                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    110052                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.89                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.97                       # Row buffer hit rate for writes
system.physmem.avgGap                     13834893.59                       # Average gap between requests
system.physmem.pageHitRate                      79.92                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     4934274417750                       # Time in different power states
system.physmem.memoryStateTime::REF      171701140000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       35983950250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                      5095093                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              662466                       # Transaction distribution
system.membus.trans_dist::ReadResp             662464                       # Transaction distribution
system.membus.trans_dist::WriteReq              13782                       # Transaction distribution
system.membus.trans_dist::WriteResp             13782                       # Transaction distribution
system.membus.trans_dist::Writeback            148771                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2188                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1699                       # Transaction distribution
system.membus.trans_dist::ReadExReq            179320                       # Transaction distribution
system.membus.trans_dist::ReadExResp           179319                       # Transaction distribution
system.membus.trans_dist::MessageReq             1645                       # Transaction distribution
system.membus.trans_dist::MessageResp            1645                       # Transaction distribution
system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3290                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3290                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471084                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775082                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       475021                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1721191                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       132996                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       132996                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1857477                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6580                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241828                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550161                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18322944                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20114933                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5463680                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5463680                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            25585193                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               25585193                       # Total data (bytes)
system.membus.snoop_data_through_bus           613568                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           250592000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           583283000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3290000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1610033997                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1645000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         3152758703                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer4.occupancy          429601748                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47571                       # number of replacements
system.iocache.tags.tagsinuse                0.128712                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47587                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4992977133000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.128712                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.008045                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.008045                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428634                       # Number of tag accesses
system.iocache.tags.data_accesses              428634                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          906                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              906                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47626                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47626                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47626                       # number of overall misses
system.iocache.overall_misses::total            47626                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    147491196                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    147491196                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  11109159898                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  11109159898                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  11256651094                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  11256651094                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  11256651094                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  11256651094                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          906                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            906                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47626                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47626                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47626                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47626                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162793.814570                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 162793.814570                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 237781.675899                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 237781.675899                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 236355.165120                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 236355.165120                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 236355.165120                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 236355.165120                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        159859                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                14672                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.895515                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          906                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          906                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47626                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47626                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47626                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47626                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    100353196                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    100353196                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   8677810402                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8677810402                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   8778163598                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8778163598                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   8778163598                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8778163598                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110765.116998                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 110765.116998                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 185740.804837                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 185740.804837                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 184314.525637                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 184314.525637                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.iobus.throughput                        637150                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq               225562                       # Transaction distribution
system.iobus.trans_dist::ReadResp              225562                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57606                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57606                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1645                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1645                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       427356                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27236                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       471084                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95252                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95252                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3290                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3290                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  569626                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       213678                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio        13618                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       241828                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027792                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027792                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6580                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              3276200                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 3276200                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              3930346                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            213679000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            20374000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           424685346                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           460198000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            53671252                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1645000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                85633263                       # Number of BP lookups
system.cpu.branchPred.condPredicted          85633263                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            884686                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79267379                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                77548662                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.831747                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1440338                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             180105                       # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        453234333                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           25483623                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      422835891                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85633263                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           78989000                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     162683938                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4002747                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     108573                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               70983982                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                43526                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         92374                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          193                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8487571                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                384793                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    2466                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          262469836                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.181706                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.411661                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                100201994     38.18%     38.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1531970      0.58%     38.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 71824716     27.36%     66.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   909581      0.35%     66.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1572022      0.60%     67.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2391233      0.91%     67.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1015593      0.39%     68.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1327813      0.51%     68.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81694914     31.13%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            262469836                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.188938                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.932930                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29410093                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              68121182                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 158520657                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3344277                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3073627                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              832752013                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   987                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3073627                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 32108860                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                42947155                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       12423337                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158815296                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13101561                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              829828808                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 20476                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                6069323                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               5155919                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands           991491995                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1800757525                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1107104494                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               110                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964043985                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 27448008                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             454148                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         459927                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  29603104                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             16744391                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             9834089                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1098610                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           922271                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  825029586                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1184674                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 821050392                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            152353                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        19282759                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     29404306                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         129800                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     262469836                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.128170                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.399623                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            76068971     28.98%     28.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15764450      6.01%     34.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10561557      4.02%     39.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7380977      2.81%     41.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            75732754     28.85%     70.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3744713      1.43%     72.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72297753     27.55%     99.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              770490      0.29%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              148171      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       262469836                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  351121     33.32%     33.32% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                    242      0.02%     33.34% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                     235      0.02%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.36% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 548827     52.08%     85.44% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                153397     14.56%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            310274      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             793553745     96.65%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               150127      0.02%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                124319      0.02%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             17682976      2.15%     98.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9228951      1.12%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              821050392                       # Type of FU issued
system.cpu.iq.rate                           1.811536                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1053822                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001284                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1905885622                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         845507474                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    817131376                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 174                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                198                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           50                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              821793858                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      82                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1694774                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2743773                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        18703                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        12097                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1404751                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1931902                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         12205                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3073627                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                31062869                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2159597                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           826214260                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            248339                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              16744391                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              9834089                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             689465                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1620816                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 13300                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          12097                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         498594                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       510068                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1008662                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             819639552                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17378500                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1410839                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26423310                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83104184                       # Number of branches executed
system.cpu.iew.exec_stores                    9044810                       # Number of stores executed
system.cpu.iew.exec_rate                     1.808423                       # Inst execution rate
system.cpu.iew.wb_sent                      819235043                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     817131426                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 638623234                       # num instructions producing a value
system.cpu.iew.wb_consumers                1043962608                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.802890                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611730                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        19998130                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1054874                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            894775                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    259396209                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     3.107629                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.863349                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     87828444     33.86%     33.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11868241      4.58%     38.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3842531      1.48%     39.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74752258     28.82%     68.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2384729      0.92%     69.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1479281      0.57%     70.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       859408      0.33%     70.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70845236     27.31%     97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5536081      2.13%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    259396209                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407807707                       # Number of instructions committed
system.cpu.commit.committedOps              806107146                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22429955                       # Number of memory references committed
system.cpu.commit.loads                      14000617                       # Number of loads committed
system.cpu.commit.membars                      474711                       # Number of memory barriers committed
system.cpu.commit.branches                   82167469                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 734952495                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155627                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       174437      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        783236239     97.16%     97.18% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          144862      0.02%     97.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121653      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        14000617      1.74%     98.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8429338      1.05%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         806107146                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5536081                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1079887016                       # The number of ROB reads
system.cpu.rob.rob_writes                  1655298855                       # The number of ROB writes
system.cpu.timesIdled                         1259672                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       190764497                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9830690598                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407807707                       # Number of Instructions Simulated
system.cpu.committedOps                     806107146                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             407807707                       # Number of Instructions Simulated
system.cpu.cpi                               1.111392                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.111392                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.899772                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.899772                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1088844162                       # number of integer regfile reads
system.cpu.int_regfile_writes               653876789                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        50                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 415644137                       # number of cc regfile reads
system.cpu.cc_regfile_writes                321521730                       # number of cc regfile writes
system.cpu.misc_regfile_reads               264115519                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 402672                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                53624827                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        3015737                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3015197                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13782                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13782                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1584798                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2253                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2253                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       336401                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       289692                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1908205                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6128379                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        19318                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       159676                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8215578                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61059136                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207801717                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       607680                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5615104                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      275083637                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         275059381                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       677312                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     4044441846                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       568500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1434613560                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3141764506                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      14738244                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     107967138                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements            953583                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.342760                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7479724                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            954095                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              7.839601                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      147639960250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.342760                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.994810                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.994810                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          177                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses           9441724                       # Number of tag accesses
system.cpu.icache.tags.data_accesses          9441724                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      7479724                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7479724                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7479724                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7479724                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7479724                       # number of overall hits
system.cpu.icache.overall_hits::total         7479724                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1007844                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1007844                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1007844                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1007844                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1007844                       # number of overall misses
system.cpu.icache.overall_misses::total       1007844                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14035582232                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14035582232                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14035582232                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14035582232                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14035582232                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14035582232                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8487568                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8487568                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8487568                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8487568                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8487568                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8487568                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.118744                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.118744                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.118744                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.118744                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.118744                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.118744                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13926.343990                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13926.343990                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13926.343990                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13926.343990                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13926.343990                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13926.343990                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         4168                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               190                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    21.936842                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53688                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        53688                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        53688                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        53688                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        53688                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        53688                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       954156                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       954156                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       954156                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       954156                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       954156                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       954156                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11587558437                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11587558437                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11587558437                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11587558437                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11587558437                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11587558437                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.112418                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.112418                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.112418                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.112418                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.112418                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.112418                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12144.301809                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12144.301809                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12144.301809                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12144.301809                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12144.301809                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12144.301809                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements         8939                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.031288                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        21114                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         8953                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     2.358316                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5104803925000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.031288                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376956                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.376956                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        71741                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        71741                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        21134                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        21134                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        21136                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        21136                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        21136                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        21136                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9823                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         9823                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9823                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         9823                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9823                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         9823                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    107949749                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    107949749                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    107949749                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    107949749                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    107949749                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    107949749                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        30957                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        30957                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        30959                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        30959                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        30959                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        30959                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.317311                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.317311                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.317291                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.317291                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.317291                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.317291                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10989.488853                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10989.488853                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10989.488853                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10989.488853                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10989.488853                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10989.488853                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1983                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1983                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9823                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9823                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9823                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         9823                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9823                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         9823                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     88296261                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     88296261                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     88296261                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     88296261                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     88296261                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     88296261                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.317311                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.317311                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.317291                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.317291                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.317291                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.317291                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8988.726560                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8988.726560                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8988.726560                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8988.726560                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8988.726560                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8988.726560                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        70861                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    12.940736                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        90199                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        70877                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.272613                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5101635052500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    12.940736                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.808796                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.808796                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       396218                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       396218                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        90199                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        90199                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        90199                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        90199                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        90199                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        90199                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        71940                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        71940                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        71940                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        71940                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        71940                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        71940                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    878693205                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    878693205                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    878693205                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    878693205                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    878693205                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    878693205                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       162139                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       162139                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       162139                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       162139                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       162139                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       162139                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.443693                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.443693                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.443693                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.443693                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.443693                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.443693                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12214.250834                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12214.250834                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12214.250834                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12214.250834                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12214.250834                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12214.250834                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        22838                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        22838                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        71940                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        71940                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        71940                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        71940                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        71940                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        71940                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    734698929                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    734698929                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    734698929                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    734698929                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    734698929                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    734698929                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.443693                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.443693                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.443693                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.443693                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.443693                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.443693                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10212.662344                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10212.662344                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10212.662344                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1658766                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.994288                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            19002910                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1659278                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.452517                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          39778250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.994288                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          295                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          87874474                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         87874474                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10896738                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10896738                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8103479                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8103479                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      19000217                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19000217                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19000217                       # number of overall hits
system.cpu.dcache.overall_hits::total        19000217                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2237270                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2237270                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       316309                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       316309                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2553579                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2553579                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2553579                       # number of overall misses
system.cpu.dcache.overall_misses::total       2553579                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  32758938054                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  32758938054                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  12034849454                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  12034849454                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  44793787508                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  44793787508                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  44793787508                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  44793787508                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13134008                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13134008                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8419788                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8419788                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21553796                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21553796                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21553796                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21553796                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.170342                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.170342                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037567                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037567                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.118475                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.118475                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118475                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118475                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14642.371307                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14642.371307                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38047.761695                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38047.761695                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17541.571069                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17541.571069                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17541.571069                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17541.571069                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       388234                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             42159                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.208805                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1559977                       # number of writebacks
system.cpu.dcache.writebacks::total           1559977                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       867558                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       867558                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        24476                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        24476                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       892034                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       892034                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       892034                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       892034                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1369712                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1369712                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       291833                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       291833                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1661545                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1661545                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1661545                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1661545                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17680675970                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17680675970                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11138475501                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11138475501                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28819151471                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  28819151471                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28819151471                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  28819151471                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97364609500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97364609500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2539074000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2539074000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99903683500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99903683500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104287                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104287                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034660                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034660                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077088                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.077088                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077088                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077088                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.316471                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.316471                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38167.292599                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38167.292599                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17344.791427                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17344.791427                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17344.791427                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17344.791427                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111887                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64820.177016                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3787056                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           176012                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            21.515897                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50551.329322                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    13.553377                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.127382                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2956.401453                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11298.765482                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.771352                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000207                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.045111                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.172405                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989077                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64125                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          513                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3391                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5259                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54885                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978470                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         34647865                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        34647865                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        64838                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         7507                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       937874                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1332851                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2343070                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1584798                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1584798                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          327                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          327                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       156813                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       156813                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        64838                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         7507                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       937874                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1489664                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2499883                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        64838                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         7507                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       937874                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1489664                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2499883                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           60                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16175                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        36023                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        52263                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1437                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1437                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       132861                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       132861                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           60                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16175                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       168884                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        185124                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           60                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16175                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       168884                       # number of overall misses
system.cpu.l2cache.overall_misses::total       185124                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      5066750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       378250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1233234983                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2788798959                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4027478942                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17149821                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     17149821                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9234678927                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9234678927                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      5066750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       378250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1233234983                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  12023477886                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13262157869                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      5066750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       378250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1233234983                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  12023477886                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13262157869                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        64898                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         7512                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       954049                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1368874                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2395333                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1584798                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1584798                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1764                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1764                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       289674                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       289674                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        64898                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         7512                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       954049                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1658548                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2685007                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        64898                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         7512                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       954049                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1658548                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2685007                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000925                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000666                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016954                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026316                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021819                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.814626                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.814626                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.458657                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.458657                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000925                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000666                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016954                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.101826                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.068947                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000925                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000666                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016954                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.101826                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.068947                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84445.833333                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        75650                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76243.275611                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77417.176776                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77061.763427                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11934.461378                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11934.461378                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69506.318084                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69506.318084                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84445.833333                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        75650                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76243.275611                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71193.706248                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71639.322125                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84445.833333                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        75650                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76243.275611                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71193.706248                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71639.322125                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102104                       # number of writebacks
system.cpu.l2cache.writebacks::total           102104                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           60                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16173                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36021                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        52259                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1437                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1437                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       132861                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       132861                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           60                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16173                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       168882                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       185120                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           60                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16173                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       168882                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       185120                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4324750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       315250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1030094767                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2339275539                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3374010306                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15289917                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15289917                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7567196573                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7567196573                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4324750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       315250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1030094767                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9906472112                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  10941206879                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4324750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       315250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1030094767                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9906472112                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  10941206879                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89251381500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89251381500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2373144500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2373144500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91624526000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91624526000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000925                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000666                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016952                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026314                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021817                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.814626                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.814626                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.458657                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.458657                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000925                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000666                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016952                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101825                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.068946                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000925                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000666                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016952                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101825                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.068946                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63692.250479                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64941.993254                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64563.238983                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10640.164927                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10640.164927                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56955.740006                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56955.740006                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63692.250479                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58659.135444                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59103.321516                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63692.250479                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58659.135444                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59103.321516                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------