path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.162227                       # Number of seconds simulated
sim_ticks                                5162226977000                       # Number of ticks simulated
final_tick                               5162226977000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 127909                       # Simulator instruction rate (inst/s)
host_op_rate                                   252832                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1618521974                       # Simulator tick rate (ticks/s)
host_mem_usage                                 804704                       # Number of bytes of host memory used
host_seconds                                  3189.47                       # Real time elapsed on the host
sim_insts                                   407963408                       # Number of instructions simulated
sim_ops                                     806401326                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         4608                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1045376                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10748480                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11827200                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1045376                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1045376                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9574464                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9574464                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           72                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16334                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             167945                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                184800                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149601                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149601                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            893                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             74                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               202505                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2082140                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5492                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2291104                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          202505                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             202505                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1854716                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1854716                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1854716                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           893                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            74                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              202505                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2082140                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5492                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4145820                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        184800                       # Number of read requests accepted
system.physmem.writeReqs                       196321                       # Number of write requests accepted
system.physmem.readBursts                      184800                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     196321                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11821504                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      5696                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  10906560                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11827200                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               12564544                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       89                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   25886                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           1718                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11628                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11143                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12156                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11292                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11683                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11167                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11068                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10875                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11368                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11325                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11465                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11570                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11698                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12742                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12203                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11328                       # Per bank write bursts
system.physmem.perBankWrBursts::0               11574                       # Per bank write bursts
system.physmem.perBankWrBursts::1               10551                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10459                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9588                       # Per bank write bursts
system.physmem.perBankWrBursts::4               11508                       # Per bank write bursts
system.physmem.perBankWrBursts::5               10703                       # Per bank write bursts
system.physmem.perBankWrBursts::6               10513                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10063                       # Per bank write bursts
system.physmem.perBankWrBursts::8               10551                       # Per bank write bursts
system.physmem.perBankWrBursts::9               10425                       # Per bank write bursts
system.physmem.perBankWrBursts::10              10702                       # Per bank write bursts
system.physmem.perBankWrBursts::11              10392                       # Per bank write bursts
system.physmem.perBankWrBursts::12              10604                       # Per bank write bursts
system.physmem.perBankWrBursts::13              11331                       # Per bank write bursts
system.physmem.perBankWrBursts::14              11278                       # Per bank write bursts
system.physmem.perBankWrBursts::15              10173                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          60                       # Number of times write queue was full causing retry
system.physmem.totGap                    5162226925000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  184800                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 196321                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    170378                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     11550                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1970                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       479                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        56                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        37                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       24                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1624                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6888                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7036                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7316                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7796                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8975                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7810                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7690                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8617                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7972                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1675                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1396                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1658                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2900                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     2598                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     2515                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     3090                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     2622                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     2336                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     2429                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     2344                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1866                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1717                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      790                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      379                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      268                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      332                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      225                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      252                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      281                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       81                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        73421                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      309.557211                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     181.985828                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     329.854749                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          27502     37.46%     37.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17545     23.90%     61.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7551     10.28%     71.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4202      5.72%     77.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2967      4.04%     81.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2030      2.76%     84.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1382      1.88%     86.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1321      1.80%     87.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8921     12.15%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          73421                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6763                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.310069                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      585.144514                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6762     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6763                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6763                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        25.198137                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.714181                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       42.096027                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31            6327     93.55%     93.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47              89      1.32%     94.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              13      0.19%     95.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              16      0.24%     95.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95              24      0.35%     95.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111             14      0.21%     95.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127            33      0.49%     96.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143            33      0.49%     96.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            38      0.56%     97.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175            13      0.19%     97.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            44      0.65%     98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            51      0.75%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            15      0.22%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             4      0.06%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             1      0.01%     99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             4      0.06%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             2      0.03%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             1      0.01%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             1      0.01%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             5      0.07%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367            22      0.33%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             4      0.06%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             2      0.03%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             1      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575             3      0.04%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::656-671             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6763                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2002108102                       # Total ticks spent queuing
system.physmem.totMemAccLat                5465439352                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    923555000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10839.14                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29589.14                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.11                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.43                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.03                       # Average write queue length when enqueuing
system.physmem.readRowHits                     151806                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    129898                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.19                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  76.22                       # Row buffer hit rate for writes
system.physmem.avgGap                     13544850.39                       # Average gap between requests
system.physmem.pageHitRate                      79.32                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  269075520                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  146817000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 709885800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                550534320                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           337171211520                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           130425108030                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2982925034250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3452197666440                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.742620                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4962301533714                       # Time in different power states
system.physmem_0.memoryStateTime::REF    172377920000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     27547412786                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  285987240                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  156044625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 730852200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                553754880                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           337171211520                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           131048206380                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2982378456750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3452324513595                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.767192                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4961386282222                       # Time in different power states
system.physmem_1.memoryStateTime::REF    172377920000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     28457517778                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                86892140                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86892140                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            896476                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79993842                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                78175387                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.726756                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1559595                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             180975                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        451961239                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27669643                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      429138859                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86892140                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79734982                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     420292054                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1880326                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     139799                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                59635                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        206134                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           79                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          545                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9182224                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                451305                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4827                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          449308052                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.884669                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.047434                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                283889001     63.18%     63.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2152335      0.48%     63.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72174656     16.06%     79.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1583547      0.35%     80.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2143406      0.48%     80.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2336945      0.52%     81.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1526578      0.34%     81.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1885904      0.42%     81.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81615680     18.16%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            449308052                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.192256                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.949504                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 22960534                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             267201307                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 150748201                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               7457847                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 940163                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              838480362                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                 940163                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 25806835                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               224389855                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       13453779                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 154655676                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              30061744                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              834963010                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                457566                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               12341140                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 186586                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               14798192                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           997326822                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1813638756                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1114908706                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               291                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964358255                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 32968562                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             467477                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         471287                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  38845539                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17334604                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10181445                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1298649                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1067040                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  829488885                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1196680                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 824229235                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            243657                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        23357015                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     36101946                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         150898                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     449308052                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.834441                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.415481                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           264987396     58.98%     58.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            14037441      3.12%     62.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             9917964      2.21%     64.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7059297      1.57%     65.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            74310664     16.54%     82.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4394298      0.98%     83.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72818105     16.21%     99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1207897      0.27%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              574990      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       449308052                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1986642     71.94%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                    137      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                     673      0.02%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.97% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 612859     22.19%     94.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                161094      5.83%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            292031      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             795863777     96.56%     96.59% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               150844      0.02%     96.61% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                125129      0.02%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                  78      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             18406058      2.23%     98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9391318      1.14%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              824229235                       # Type of FU issued
system.cpu.iq.rate                           1.823672                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2761405                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.003350                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2100771128                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         854054980                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    819688520                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 455                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                442                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          164                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              826698389                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     220                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1868749                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3338025                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14795                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14329                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1756067                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2207525                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         74436                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 940163                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               205965159                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              10145461                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           830685565                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            152778                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17334627                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10181445                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             703446                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 417328                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               8832506                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14329                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         509833                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       537197                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1047030                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             822615157                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              18006824                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1479252                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     27175476                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83299971                       # Number of branches executed
system.cpu.iew.exec_stores                    9168652                       # Number of stores executed
system.cpu.iew.exec_rate                     1.820101                       # Inst execution rate
system.cpu.iew.wb_sent                      822110525                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     819688684                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 640992243                       # num instructions producing a value
system.cpu.iew.wb_consumers                1050515204                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.813626                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.610169                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        24158442                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1045781                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            908032                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    445675381                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.809392                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.671516                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    274876482     61.68%     61.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11176587      2.51%     64.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3572419      0.80%     64.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74567842     16.73%     81.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2417950      0.54%     82.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1626837      0.37%     82.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       937685      0.21%     82.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     71052352     15.94%     98.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5447227      1.22%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    445675381                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407963408                       # Number of instructions committed
system.cpu.commit.committedOps              806401326                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22421978                       # Number of memory references committed
system.cpu.commit.loads                      13996600                       # Number of loads committed
system.cpu.commit.membars                      471855                       # Number of memory barriers committed
system.cpu.commit.branches                   82197677                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735212771                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1156131                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       171861      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        783543527     97.17%     97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          145013      0.02%     97.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121508      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        13994023      1.74%     98.96% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8425378      1.04%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         806401326                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5447227                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1270709490                       # The number of ROB reads
system.cpu.rob.rob_writes                  1664771633                       # The number of ROB writes
system.cpu.timesIdled                          294088                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         2653187                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9872490334                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407963408                       # Number of Instructions Simulated
system.cpu.committedOps                     806401326                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.107847                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.107847                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.902651                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.902651                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1092540236                       # number of integer regfile reads
system.cpu.int_regfile_writes               656081112                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       164                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 416269777                       # number of cc regfile reads
system.cpu.cc_regfile_writes                322038455                       # number of cc regfile writes
system.cpu.misc_regfile_reads               265590229                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 400570                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           1660860                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.966923                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            19133185                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1661372                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.516497                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          41264250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.966923                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999935                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999935                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          197                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          88373649                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         88373649                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10984709                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10984709                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8081292                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8081292                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        64363                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         64363                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      19066001                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19066001                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19130364                       # number of overall hits
system.cpu.dcache.overall_hits::total        19130364                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1806694                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1806694                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       334372                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       334372                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       406627                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       406627                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      2141066                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2141066                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2547693                       # number of overall misses
system.cpu.dcache.overall_misses::total       2547693                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  27203829960                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  27203829960                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  13876174615                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  13876174615                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  41080004575                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  41080004575                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  41080004575                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  41080004575                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12791403                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12791403                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8415664                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8415664                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       470990                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       470990                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21207067                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21207067                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21678057                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21678057                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.141243                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.141243                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039732                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.039732                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863345                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.863345                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.100960                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.100960                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.117524                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.117524                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15057.242654                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15057.242654                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41499.212299                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 41499.212299                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19186.706330                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19186.706330                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16124.393549                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16124.393549                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       418738                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             44180                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.477999                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1562601                       # number of writebacks
system.cpu.dcache.writebacks::total           1562601                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       836073                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       836073                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44459                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        44459                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       880532                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       880532                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       880532                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       880532                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       970621                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       970621                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289913                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       289913                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403165                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       403165                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1260534                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1260534                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1663699                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1663699                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12878267529                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12878267529                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12265177974                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  12265177974                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5946557500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5946557500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25143445503                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  25143445503                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31090003003                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  31090003003                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97454738500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97454738500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2595624500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2595624500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100050363000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 100050363000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075881                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075881                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034449                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034449                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.855995                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.855995                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059439                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.059439                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076746                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.076746                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13268.070162                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13268.070162                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42306.409074                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42306.409074                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14749.686853                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14749.686853                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19946.661893                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19946.661893                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18687.276366                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18687.276366                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        73201                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    15.783499                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs       115173                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        73217                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.573036                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 194860088500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.783499                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.986469                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.986469                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       453261                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       453261                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       115173                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       115173                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       115173                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       115173                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       115173                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       115173                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74305                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        74305                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74305                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        74305                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74305                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        74305                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    909823965                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    909823965                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    909823965                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    909823965                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    909823965                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    909823965                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       189478                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       189478                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       189478                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       189478                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       189478                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       189478                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.392156                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.392156                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.392156                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.392156                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.392156                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.392156                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12244.451450                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12244.451450                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12244.451450                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12244.451450                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12244.451450                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12244.451450                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        20777                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        20777                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74305                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74305                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74305                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        74305                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74305                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        74305                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    798246705                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    798246705                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    798246705                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    798246705                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    798246705                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    798246705                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.392156                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.392156                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.392156                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.392156                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.392156                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.392156                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10742.839715                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10742.839715                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10742.839715                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10742.839715                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10742.839715                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10742.839715                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            998549                       # number of replacements
system.cpu.icache.tags.tagsinuse           508.782510                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             8117400                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            999061                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              8.125029                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      148026169000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   508.782510                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.993716                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.993716                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          166                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          10181383                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         10181383                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      8117400                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8117400                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       8117400                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8117400                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      8117400                       # number of overall hits
system.cpu.icache.overall_hits::total         8117400                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1064820                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1064820                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1064820                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1064820                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1064820                       # number of overall misses
system.cpu.icache.overall_misses::total       1064820                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14888205043                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14888205043                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14888205043                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14888205043                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14888205043                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14888205043                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9182220                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9182220                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9182220                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9182220                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9182220                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9182220                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115965                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.115965                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.115965                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.115965                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.115965                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.115965                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13981.898389                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13981.898389                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13981.898389                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13981.898389                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13981.898389                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13981.898389                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         8289                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               307                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs           27                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        65657                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        65657                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        65657                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        65657                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        65657                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        65657                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       999163                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       999163                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       999163                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       999163                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       999163                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       999163                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12710822780                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12710822780                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12710822780                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12710822780                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12710822780                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12710822780                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108815                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108815                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108815                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.108815                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108815                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.108815                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12721.470651                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12721.470651                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12721.470651                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12721.470651                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12721.470651                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12721.470651                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements        13893                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.071844                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        25336                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs        13905                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     1.822078                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5120509210500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.071844                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.379490                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.379490                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        95038                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        95038                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        25353                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        25353                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        25355                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        25355                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        25355                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        25355                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14776                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        14776                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14776                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        14776                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14776                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        14776                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    169038743                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    169038743                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    169038743                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    169038743                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    169038743                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    169038743                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        40129                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        40129                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        40131                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        40131                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        40131                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        40131                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.368213                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.368213                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.368194                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.368194                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.368194                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.368194                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11440.088184                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11440.088184                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11440.088184                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11440.088184                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11440.088184                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11440.088184                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         2930                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         2930                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14776                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14776                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14776                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        14776                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14776                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        14776                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    146855281                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    146855281                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    146855281                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    146855281                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    146855281                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    146855281                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.368213                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.368213                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.368194                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.368194                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.368194                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.368194                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9938.771048                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9938.771048                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9938.771048                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9938.771048                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9938.771048                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9938.771048                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           112586                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64823.777262                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3838448                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           176580                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            21.737728                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50334.465140                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    16.515711                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.150651                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3177.784987                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11294.860772                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.768043                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000252                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.048489                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.172346                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989132                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63994                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          578                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3409                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4787                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55160                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.976471                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         35090469                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        35090469                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        67085                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12024                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       982640                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1337375                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2399124                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1586308                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1586308                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          347                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          347                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       154552                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       154552                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        67085                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        12024                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       982640                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1491927                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2553676                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        67085                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        12024                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       982640                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1491927                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2553676                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           72                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16338                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        35694                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        52110                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1456                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1456                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133212                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133212                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           72                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16338                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       168906                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        185322                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           72                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16338                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       168906                       # number of overall misses
system.cpu.l2cache.overall_misses::total       185322                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      6378000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       517750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1368817000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3072160502                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4447873252                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     23702788                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     23702788                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10297290972                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  10297290972                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6378000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       517750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1368817000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  13369451474                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  14745164224                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6378000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       517750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1368817000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  13369451474                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  14745164224                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        67157                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        12030                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       998978                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1373069                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2451234                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1586308                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1586308                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1803                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1803                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287764                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287764                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        67157                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        12030                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       998978                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1660833                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2738998                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        67157                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        12030                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       998978                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1660833                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2738998                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001072                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000499                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016355                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.025996                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021259                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.807543                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.807543                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.462921                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.462921                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001072                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000499                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016355                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.101700                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.067661                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001072                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000499                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016355                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.101700                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.067661                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88583.333333                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 86291.666667                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83781.184968                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86069.381465                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 85355.464441                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16279.387363                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16279.387363                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77300.025313                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77300.025313                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88583.333333                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86291.666667                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83781.184968                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79153.206363                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79565.104111                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88583.333333                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86291.666667                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83781.184968                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79153.206363                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79565.104111                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102934                       # number of writebacks
system.cpu.l2cache.writebacks::total           102934                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           72                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16334                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35693                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        52105                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1456                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1456                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133212                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133212                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           72                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16334                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       168905                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       185317                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           72                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16334                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       168905                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       185317                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      5474000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       443250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1164107250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2626406248                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3796430748                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     26736438                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     26736438                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8631944528                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8631944528                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5474000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       443250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1164107250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11258350776                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  12428375276                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5474000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       443250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1164107250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11258350776                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  12428375276                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  88988870500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  88988870500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2413772500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2413772500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91402643000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91402643000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001072                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000499                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016351                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025995                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021257                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.807543                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.807543                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.462921                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.462921                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001072                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000499                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016351                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101699                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.067659                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001072                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000499                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016351                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101699                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.067659                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76027.777778                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        73875                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71268.963512                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73583.230549                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72861.160119                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18362.938187                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18362.938187                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64798.550641                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64798.550641                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76027.777778                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        73875                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71268.963512                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66654.928960                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67065.489275                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76027.777778                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        73875                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71268.963512                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66654.928960                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67065.489275                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        3067519                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3066979                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13939                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13939                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1586308                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46766                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2284                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2284                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       287771                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       287771                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError            7                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1998141                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6126615                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        29736                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       162239                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8316731                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63934592                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    208102552                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       957440                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5627776                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          278622360                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       59218                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      4385945                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.010871                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.103697                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            4338264     98.91%     98.91% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4              47681      1.09%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4385945                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4071743474                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       573000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1503118459                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3140913916                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      22173731                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     111517380                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               223909                       # Transaction distribution
system.iobus.trans_dist::ReadResp              223909                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57755                       # Transaction distribution
system.iobus.trans_dist::WriteResp              11035                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1653                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1653                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       423734                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1218                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       468058                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95270                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95270                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3306                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3306                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  566634                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       211867                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2436                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       240327                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027864                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027864                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6612                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6612                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3274803                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3940376                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            211868000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1020000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            20815000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           257361146                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           457023000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            50384761                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1653000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47580                       # number of replacements
system.iocache.tags.tagsinuse                0.202391                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47596                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4993301800000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.202391                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.012649                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.012649                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428715                       # Number of tag accesses
system.iocache.tags.data_accesses              428715                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          915                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              915                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::pc.south_bridge.ide          915                       # number of demand (read+write) misses
system.iocache.demand_misses::total               915                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          915                       # number of overall misses
system.iocache.overall_misses::total              915                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    146193424                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    146193424                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   8577113961                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   8577113961                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    146193424                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    146193424                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    146193424                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    146193424                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          915                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            915                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          915                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             915                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          915                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            915                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 159774.233880                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 159774.233880                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183585.487179                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183585.487179                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 159774.233880                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 159774.233880                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 159774.233880                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 159774.233880                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         29604                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 4403                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.723598                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          915                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          915                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          915                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          915                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          915                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          915                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     98194936                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     98194936                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   6147663971                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6147663971                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     98194936                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     98194936                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     98194936                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     98194936                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107316.869945                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 107316.869945                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131585.273352                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131585.273352                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 107316.869945                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 107316.869945                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 107316.869945                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 107316.869945                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              657723                       # Transaction distribution
system.membus.trans_dist::ReadResp             657716                       # Transaction distribution
system.membus.trans_dist::WriteReq              13939                       # Transaction distribution
system.membus.trans_dist::WriteResp             13939                       # Transaction distribution
system.membus.trans_dist::Writeback            149601                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2217                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1736                       # Transaction distribution
system.membus.trans_dist::ReadExReq            132934                       # Transaction distribution
system.membus.trans_dist::ReadExResp           132932                       # Transaction distribution
system.membus.trans_dist::MessageReq             1653                       # Transaction distribution
system.membus.trans_dist::MessageResp            1653                       # Transaction distribution
system.membus.trans_dist::BadAddressError            7                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3306                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3306                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       468058                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769226                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       476258                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           14                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1713556                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141465                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141465                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1858327                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6612                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6612                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       240327                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538449                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18386624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20165400                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      6005120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                26177132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1646                       # Total snoops (count)
system.membus.snoop_fanout::samples            384552                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  384552    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              384552                       # Request fanout histogram
system.membus.reqLayer0.occupancy           357825500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           388164500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3306000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1202618637                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                8500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1653000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2206854286                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           51509239                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------