path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.137926                       # Number of seconds simulated
sim_ticks                                5137926173000                       # Number of ticks simulated
final_tick                               5137926173000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 165389                       # Simulator instruction rate (inst/s)
host_op_rate                                   326926                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2083966500                       # Simulator tick rate (ticks/s)
host_mem_usage                                 742788                       # Number of bytes of host memory used
host_seconds                                  2465.46                       # Real time elapsed on the host
sim_insts                                   407759509                       # Number of instructions simulated
sim_ops                                     806020953                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide      2427584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1035776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10808512                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14275968                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1035776                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1035776                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9555328                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9555328                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        37931                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           59                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16184                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168883                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                223062                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149302                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149302                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       472483                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            735                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               201594                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2103672                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2778547                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          201594                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             201594                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1859764                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1859764                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1859764                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       472483                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           735                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              201594                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2103672                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4638310                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        223062                       # Number of read requests accepted
system.physmem.writeReqs                       149302                       # Number of write requests accepted
system.physmem.readBursts                      223062                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     149302                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 14267968                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8000                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9553728                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  14275968                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9555328                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      125                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           1775                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               14642                       # Per bank write bursts
system.physmem.perBankRdBursts::1               13963                       # Per bank write bursts
system.physmem.perBankRdBursts::2               14587                       # Per bank write bursts
system.physmem.perBankRdBursts::3               13341                       # Per bank write bursts
system.physmem.perBankRdBursts::4               14143                       # Per bank write bursts
system.physmem.perBankRdBursts::5               13526                       # Per bank write bursts
system.physmem.perBankRdBursts::6               13007                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13123                       # Per bank write bursts
system.physmem.perBankRdBursts::8               13660                       # Per bank write bursts
system.physmem.perBankRdBursts::9               13743                       # Per bank write bursts
system.physmem.perBankRdBursts::10              13657                       # Per bank write bursts
system.physmem.perBankRdBursts::11              13667                       # Per bank write bursts
system.physmem.perBankRdBursts::12              14668                       # Per bank write bursts
system.physmem.perBankRdBursts::13              14755                       # Per bank write bursts
system.physmem.perBankRdBursts::14              14289                       # Per bank write bursts
system.physmem.perBankRdBursts::15              14166                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10056                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9321                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9829                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8830                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9558                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8986                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8593                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8747                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8969                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9193                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9160                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9087                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9894                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9881                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9649                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9524                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    5137926057000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  223062                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 149302                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    173856                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     14004                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      5938                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3116                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2938                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      3695                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      3277                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3105                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2401                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1802                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1616                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1416                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1120                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1019                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      848                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      763                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      690                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      540                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      420                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      347                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       24                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1696                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6323                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6727                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6895                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7003                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7385                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8610                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8913                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9225                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     9112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     9115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1696                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1783                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1529                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1057                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      857                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      652                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        75897                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      313.867900                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     181.633012                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     336.529129                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          29529     38.91%     38.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        16915     22.29%     61.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7566      9.97%     71.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4259      5.61%     76.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2981      3.93%     80.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2008      2.65%     83.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1459      1.92%     85.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1171      1.54%     86.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        10009     13.19%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          75897                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          8307                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.835320                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      526.600201                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           8306     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            8307                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          8307                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.970025                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.437156                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        5.734930                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            6174     74.32%     74.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            1334     16.06%     90.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              66      0.79%     91.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              64      0.77%     91.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              51      0.61%     92.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              45      0.54%     93.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29             113      1.36%     94.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31              87      1.05%     95.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33              56      0.67%     96.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35              56      0.67%     96.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37              34      0.41%     97.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39              52      0.63%     97.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41              60      0.72%     98.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43              31      0.37%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45              10      0.12%     99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47              10      0.12%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49              28      0.34%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51               7      0.08%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53               4      0.05%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54-55               3      0.04%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-57               5      0.06%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59               4      0.05%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-61               2      0.02%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::62-63               3      0.04%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-65               2      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::66-67               1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-69               2      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-77               1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::78-79               1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::90-91               1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            8307                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4966355250                       # Total ticks spent queuing
system.physmem.totMemAccLat                9146424000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1114685000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       22276.94                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  41026.94                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.78                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.78                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.86                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.93                       # Average write queue length when enqueuing
system.physmem.readRowHits                     185691                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    110625                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.29                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.09                       # Row buffer hit rate for writes
system.physmem.avgGap                     13798127.79                       # Average gap between requests
system.physmem.pageHitRate                      79.60                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     4930575819000                       # Time in different power states
system.physmem.memoryStateTime::REF      171566460000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       35783789000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                      5117506                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              662560                       # Transaction distribution
system.membus.trans_dist::ReadResp             662552                       # Transaction distribution
system.membus.trans_dist::WriteReq              13764                       # Transaction distribution
system.membus.trans_dist::WriteResp             13764                       # Transaction distribution
system.membus.trans_dist::Writeback            149302                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2261                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1794                       # Transaction distribution
system.membus.trans_dist::ReadExReq            180173                       # Transaction distribution
system.membus.trans_dist::ReadExResp           180170                       # Transaction distribution
system.membus.trans_dist::MessageReq             1643                       # Transaction distribution
system.membus.trans_dist::MessageResp            1643                       # Transaction distribution
system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3286                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3286                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471036                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775076                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       477605                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1723733                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       132228                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       132228                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1859247                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241801                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550149                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18417024                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20208974                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5414272                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5414272                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            25629818                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               25629818                       # Total data (bytes)
system.membus.snoop_data_through_bus           663552                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           250523000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           583102000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3286000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1620731000                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                9000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1643000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         3164060842                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer4.occupancy          429649499                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47575                       # number of replacements
system.iocache.tags.tagsinuse                0.116331                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47591                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4992948576000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.116331                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007271                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.007271                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428670                       # Number of tag accesses
system.iocache.tags.data_accesses              428670                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          910                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              910                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47630                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47630                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47630                       # number of overall misses
system.iocache.overall_misses::total            47630                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    151620185                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    151620185                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  11039278588                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  11039278588                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  11190898773                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  11190898773                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  11190898773                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  11190898773                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          910                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            910                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47630                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47630                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47630                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47630                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166615.587912                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 166615.587912                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 236285.928682                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 236285.928682                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 234954.834621                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 234954.834621                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 234954.834621                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 234954.834621                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        159238                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                14593                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.911944                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          910                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47630                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47630                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47630                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47630                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104274685                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    104274685                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   8607905090                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8607905090                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   8712179775                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8712179775                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   8712179775                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8712179775                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114587.565934                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 114587.565934                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 184244.543878                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 184244.543878                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 182913.705123                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 182913.705123                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.iobus.throughput                        637650                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq               225557                       # Transaction distribution
system.iobus.trans_dist::ReadResp              225557                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57591                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57591                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1643                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1643                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       427354                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27236                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       471036                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95260                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95260                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3286                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3286                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  569582                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       213677                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio        13618                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       241801                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027824                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027824                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6572                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              3276197                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 3276197                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              3919904                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8851000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            213678000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            20374000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           424855274                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           460165000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            53596501                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1643000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                85854110                       # Number of BP lookups
system.cpu.branchPred.condPredicted          85854110                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            890492                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79431123                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                77651636                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.759711                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1460640                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             181048                       # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        452853570                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           25683785                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      423946474                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85854110                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79112276                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     162997927                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4233083                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     105681                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               69250991                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                42777                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         91487                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          266                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8611652                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                409614                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    2534                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          261469410                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.201181                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.413215                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 98890192     37.82%     37.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1558006      0.60%     38.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 71842115     27.48%     65.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   921619      0.35%     66.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1585920      0.61%     66.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2431144      0.93%     67.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1036910      0.40%     68.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1345104      0.51%     68.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81858400     31.31%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            261469410                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.189585                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.936167                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29046589                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              66961601                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 159616384                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               2548340                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3296496                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              834624632                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   895                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3296496                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 31320829                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                35759496                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       12826241                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 159575235                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              18691113                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              831621243                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                271968                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                7201596                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 103405                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                9490411                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           993545092                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1805477878                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1109904628                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               111                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             963933701                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 29611389                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             457228                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         464601                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  24223020                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             16966534                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             9968316                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1221781                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           988150                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  826572087                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1194475                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 821819105                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            208862                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        20915933                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     32275833                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         139879                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     261469410                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.143079                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.407689                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            76437702     29.23%     29.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            14614697      5.59%     34.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10065724      3.85%     38.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7027094      2.69%     41.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            75658650     28.94%     70.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3979218      1.52%     71.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72575299     27.76%     99.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              879014      0.34%     99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              232012      0.09%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       261469410                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  395534     35.48%     35.48% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                    246      0.02%     35.50% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                     260      0.02%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.53% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 578947     51.93%     87.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                139812     12.54%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            313841      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             794169455     96.64%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               150148      0.02%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                125336      0.02%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             17790783      2.16%     98.87% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9269542      1.13%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              821819105                       # Type of FU issued
system.cpu.iq.rate                           1.814757                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1114799                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001357                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1906543911                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         848693742                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    817833447                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 176                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                182                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           50                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              822619981                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      82                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1787791                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2974113                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        16000                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        13012                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1545780                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1935112                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         35450                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3296496                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                15966541                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              12762115                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           827766562                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            204474                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              16966534                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              9968316                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             698992                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1766485                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents              10560079                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          13012                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         503157                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       519909                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1023066                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             820377360                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17471183                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1441744                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26545601                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83164783                       # Number of branches executed
system.cpu.iew.exec_stores                    9074418                       # Number of stores executed
system.cpu.iew.exec_rate                     1.811573                       # Inst execution rate
system.cpu.iew.wb_sent                      819943769                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     817833497                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 640559141                       # num instructions producing a value
system.cpu.iew.wb_consumers                1047723157                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.805956                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611382                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        21640086                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1054596                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            900184                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    258172914                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     3.122020                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.868515                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     87519981     33.90%     33.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11178946      4.33%     38.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3524931      1.37%     39.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74556840     28.88%     68.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2487891      0.96%     69.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1503617      0.58%     70.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       865491      0.34%     70.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70822706     27.43%     97.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5712511      2.21%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    258172914                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407759509                       # Number of instructions committed
system.cpu.commit.committedOps              806020953                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22414956                       # Number of memory references committed
system.cpu.commit.loads                      13992420                       # Number of loads committed
system.cpu.commit.membars                      474659                       # Number of memory barriers committed
system.cpu.commit.branches                   82156165                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 734866809                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155346                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       174342      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        783165220     97.16%     97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          144784      0.02%     97.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121651      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        13992420      1.74%     98.96% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8422536      1.04%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         806020953                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5712511                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1080043164                       # The number of ROB reads
system.cpu.rob.rob_writes                  1658634797                       # The number of ROB writes
system.cpu.timesIdled                         1275471                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       191384160                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9823003775                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407759509                       # Number of Instructions Simulated
system.cpu.committedOps                     806020953                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.110590                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.110590                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.900422                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.900422                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1089597141                       # number of integer regfile reads
system.cpu.int_regfile_writes               654482969                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        50                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 415870022                       # number of cc regfile reads
system.cpu.cc_regfile_writes                321677512                       # number of cc regfile writes
system.cpu.misc_regfile_reads               264445635                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 402422                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                53724216                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        3026047                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3025482                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13764                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13764                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1581183                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2322                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2322                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       334322                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       287613                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1928223                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6126020                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18717                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       156212                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8229172                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61697728                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207710542                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       574144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5436928                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      275419342                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         275396046                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       635008                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     4043112921                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       546000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1449735220                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3140330868                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      14620748                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     106945143                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements            963566                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.311037                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7590970                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            964078                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              7.873813                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      147613206250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.311037                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.994748                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.994748                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          231                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          180                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses           9575846                       # Number of tag accesses
system.cpu.icache.tags.data_accesses          9575846                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      7590970                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7590970                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7590970                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7590970                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7590970                       # number of overall hits
system.cpu.icache.overall_hits::total         7590970                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1020680                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1020680                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1020680                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1020680                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1020680                       # number of overall misses
system.cpu.icache.overall_misses::total       1020680                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14179701612                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14179701612                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14179701612                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14179701612                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14179701612                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14179701612                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8611650                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8611650                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8611650                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8611650                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8611650                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8611650                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.118523                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.118523                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.118523                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.118523                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.118523                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.118523                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13892.406643                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13892.406643                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13892.406643                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13892.406643                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13892.406643                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13892.406643                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         4723                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               198                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    23.853535                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        56484                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        56484                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        56484                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        56484                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        56484                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        56484                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       964196                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       964196                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       964196                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       964196                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       964196                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       964196                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11690907021                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11690907021                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11690907021                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11690907021                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11690907021                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11690907021                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.111964                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.111964                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.111964                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.111964                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.111964                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.111964                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12125.031654                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12125.031654                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12125.031654                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12125.031654                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12125.031654                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12125.031654                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements         8862                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.026427                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        19635                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         8877                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     2.211896                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5109382719500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.026427                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376652                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.376652                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        68718                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        68718                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        19738                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        19738                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        19740                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        19740                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        19740                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        19740                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9746                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         9746                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9746                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         9746                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9746                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         9746                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    105945749                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    105945749                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    105945749                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    105945749                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    105945749                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    105945749                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        29484                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        29484                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        29486                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        29486                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        29486                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        29486                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.330552                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.330552                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.330530                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.330530                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.330530                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.330530                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10870.690437                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10870.690437                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10870.690437                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10870.690437                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10870.690437                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10870.690437                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1636                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1636                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9746                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9746                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9746                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         9746                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9746                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         9746                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     86450253                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     86450253                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     86450253                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     86450253                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     86450253                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     86450253                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.330552                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.330552                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.330530                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.330530                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.330530                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.330530                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8870.331726                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8870.331726                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8870.331726                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8870.331726                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8870.331726                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8870.331726                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        70197                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    14.820412                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        92434                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        70211                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.316517                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5101611575500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    14.820412                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.926276                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.926276                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       398660                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       398660                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        92440                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        92440                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        92440                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        92440                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        92440                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        92440                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        71260                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        71260                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        71260                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        71260                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        71260                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        71260                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    875246716                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    875246716                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    875246716                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    875246716                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    875246716                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    875246716                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       163700                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       163700                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       163700                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       163700                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       163700                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       163700                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.435308                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.435308                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.435308                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.435308                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.435308                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.435308                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12282.440584                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12282.440584                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12282.440584                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12282.440584                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12282.440584                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12282.440584                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        20047                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        20047                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        71260                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        71260                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        71260                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        71260                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        71260                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        71260                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    732616430                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    732616430                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    732616430                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    732616430                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    732616430                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    732616430                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.435308                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.435308                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.435308                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.435308                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.435308                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.435308                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10280.892927                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10280.892927                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10280.892927                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1657713                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.996506                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            19009946                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1658225                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.464033                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          39778250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.996506                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999993                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999993                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          328                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          87793833                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         87793833                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10909808                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10909808                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8097329                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8097329                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      19007137                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19007137                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19007137                       # number of overall hits
system.cpu.dcache.overall_hits::total        19007137                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2211100                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2211100                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       315662                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       315662                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2526762                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2526762                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2526762                       # number of overall misses
system.cpu.dcache.overall_misses::total       2526762                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  32878750930                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  32878750930                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  12078727781                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  12078727781                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  44957478711                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  44957478711                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  44957478711                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  44957478711                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13120908                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13120908                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8412991                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8412991                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21533899                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21533899                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21533899                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21533899                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.168517                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.168517                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037521                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037521                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.117339                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.117339                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.117339                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.117339                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14869.861576                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14869.861576                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38264.750844                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38264.750844                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17792.526052                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17792.526052                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17792.526052                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17792.526052                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       428041                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             36530                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.717520                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1559500                       # number of writebacks
system.cpu.dcache.writebacks::total           1559500                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       840350                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       840350                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        25845                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        25845                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       866195                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       866195                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       866195                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       866195                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1370750                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1370750                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289817                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       289817                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1660567                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1660567                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1660567                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1660567                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17852039460                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17852039460                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11191134624                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11191134624                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29043174084                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  29043174084                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29043174084                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  29043174084                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97363185500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97363185500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2536205500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2536205500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99899391000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99899391000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104471                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104471                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034449                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034449                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077114                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.077114                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077114                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077114                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13023.556053                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13023.556053                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38614.486466                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38614.486466                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17489.914038                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17489.914038                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17489.914038                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17489.914038                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           112318                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64820.835708                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3791752                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           176203                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            21.519225                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50598.140423                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    13.189472                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.125676                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2974.923375                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11234.456763                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.772066                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000201                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.045394                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.171424                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989087                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63885                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          534                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3396                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6277                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53619                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.974808                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         34689659                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        34689659                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        64846                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         7330                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       947840                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1333918                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2353934                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1581183                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1581183                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          324                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          324                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       153879                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       153879                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        64846                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         7330                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       947840                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1487797                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2507813                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        64846                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         7330                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       947840                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1487797                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2507813                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           59                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16187                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        36112                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        52363                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1531                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1531                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133713                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133713                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           59                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16187                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169825                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        186076                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           59                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16187                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169825                       # number of overall misses
system.cpu.l2cache.overall_misses::total       186076                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4865250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       378250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1226165489                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2849475947                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4080884936                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     18074783                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     18074783                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9317667167                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9317667167                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4865250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       378250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1226165489                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  12167143114                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13398552103                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4865250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       378250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1226165489                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  12167143114                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13398552103                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        64905                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         7335                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       964027                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1370030                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2406297                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1581183                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1581183                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1855                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1855                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287592                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287592                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        64905                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         7335                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       964027                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1657622                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2693889                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        64905                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         7335                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       964027                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1657622                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2693889                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000909                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000682                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016791                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026359                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021761                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.825337                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.825337                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.464940                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.464940                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000909                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000682                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016791                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102451                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.069073                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000909                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000682                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016791                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102451                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.069073                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 82461.864407                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        75650                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75750.014765                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78906.622369                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77934.513607                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11805.867407                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11805.867407                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69684.078339                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69684.078339                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 82461.864407                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        75650                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75750.014765                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71645.182476                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72005.804634                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 82461.864407                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        75650                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75750.014765                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71645.182476                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72005.804634                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102635                       # number of writebacks
system.cpu.l2cache.writebacks::total           102635                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           59                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16184                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36110                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        52358                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1531                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1531                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133713                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133713                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           59                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16184                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169823                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       186071                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           59                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16184                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169823                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       186071                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4137750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       315250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1022850261                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2399724551                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3427027812                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     16292512                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     16292512                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7636829333                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7636829333                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4137750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       315250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1022850261                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10036553884                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11063857145                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4137750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       315250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1022850261                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10036553884                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  11063857145                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89250074000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89250074000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2370675000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2370675000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91620749000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91620749000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000909                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000682                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016788                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026357                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021759                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.825337                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.825337                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464940                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464940                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000909                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000682                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016788                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102450                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.069072                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000909                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000682                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016788                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102450                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.069072                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63201.326063                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66455.955442                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65453.757057                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10641.745265                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10641.745265                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57113.589053                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57113.589053                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63201.326063                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59100.085878                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59460.405678                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        63050                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63201.326063                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59100.085878                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59460.405678                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------