path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.137726                       # Number of seconds simulated
sim_ticks                                5137726358500                       # Number of ticks simulated
final_tick                               5137726358500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 193743                       # Simulator instruction rate (inst/s)
host_op_rate                                   385165                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4079424438                       # Simulator tick rate (ticks/s)
host_mem_usage                                1056160                       # Number of bytes of host memory used
host_seconds                                  1259.42                       # Real time elapsed on the host
sim_insts                                   244004222                       # Number of instructions simulated
sim_ops                                     485086710                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           380096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4972288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           215232                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2058496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         2112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           369024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          3382272                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11408192                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       380096                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       215232                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       369024                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          964352                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9193728                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9193728                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              5939                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             77692                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3363                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             32164                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           33                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              5766                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             52848                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                178253                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          143652                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143652                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               73981                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              967799                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               41892                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              400663                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           411                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               71826                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              658321                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5518                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2220475                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          73981                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          41892                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          71826                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             187700                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1789455                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1789455                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1789455                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              73981                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             967799                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              41892                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             400663                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          411                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              71826                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             658321                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5518                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4009929                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         94617                       # Number of read requests accepted
system.physmem.writeReqs                        88760                       # Number of write requests accepted
system.physmem.readBursts                       94617                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      88760                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  6047936                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7552                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   5680640                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   6055488                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                5680640                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      118                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          28899                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                6147                       # Per bank write bursts
system.physmem.perBankRdBursts::1                5269                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5685                       # Per bank write bursts
system.physmem.perBankRdBursts::3                5978                       # Per bank write bursts
system.physmem.perBankRdBursts::4                5788                       # Per bank write bursts
system.physmem.perBankRdBursts::5                5231                       # Per bank write bursts
system.physmem.perBankRdBursts::6                5218                       # Per bank write bursts
system.physmem.perBankRdBursts::7                5097                       # Per bank write bursts
system.physmem.perBankRdBursts::8                6282                       # Per bank write bursts
system.physmem.perBankRdBursts::9                6366                       # Per bank write bursts
system.physmem.perBankRdBursts::10               6408                       # Per bank write bursts
system.physmem.perBankRdBursts::11               6175                       # Per bank write bursts
system.physmem.perBankRdBursts::12               5716                       # Per bank write bursts
system.physmem.perBankRdBursts::13               6642                       # Per bank write bursts
system.physmem.perBankRdBursts::14               6153                       # Per bank write bursts
system.physmem.perBankRdBursts::15               6344                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6191                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5213                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6082                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5966                       # Per bank write bursts
system.physmem.perBankWrBursts::4                5232                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5147                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4857                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4466                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5491                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5559                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5838                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5586                       # Per bank write bursts
system.physmem.perBankWrBursts::12               5717                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5929                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5787                       # Per bank write bursts
system.physmem.perBankWrBursts::15               5699                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
system.physmem.totGap                    5136593386000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   94617                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  88760                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     87985                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      5016                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       993                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       194                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        47                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1916                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4660                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4616                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4503                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4558                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4579                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5584                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6774                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6014                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5868                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4923                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4555                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4503                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       10                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        41697                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      281.270307                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     168.374177                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     307.197981                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          16587     39.78%     39.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        10275     24.64%     64.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4266     10.23%     74.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2445      5.86%     80.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1622      3.89%     84.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1132      2.71%     87.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          786      1.89%     89.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          680      1.63%     90.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3904      9.36%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          41697                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4370                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.624485                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      178.940609                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            4367     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-6655            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9728-10239            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4370                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4370                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.311213                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.106663                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.785732                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                51      1.17%      1.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 5      0.11%      1.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                1      0.02%      1.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               8      0.18%      1.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            3654     83.62%     85.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              60      1.37%     86.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             119      2.72%     89.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              59      1.35%     90.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              85      1.95%     92.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             116      2.65%     95.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              13      0.30%     95.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               5      0.11%     95.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               9      0.21%     95.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               3      0.07%     95.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               2      0.05%     95.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               4      0.09%     95.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             133      3.04%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.09%     99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               6      0.14%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               3      0.07%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.02%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.02%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.07%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.05%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            10      0.23%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.02%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.02%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.07%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4370                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1101479246                       # Total ticks spent queuing
system.physmem.totMemAccLat                2873335496                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    472495000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11655.99                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30405.99                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.18                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.11                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.18                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.11                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.11                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.15                       # Average write queue length when enqueuing
system.physmem.readRowHits                      75876                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     65681                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.29                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.00                       # Row buffer hit rate for writes
system.physmem.avgGap                     28011110.37                       # Average gap between requests
system.physmem.pageHitRate                      77.24                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  153536040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   83535375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 346421400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                279618480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           250238982240                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            94990329855                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2239672524000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             2585764947390                       # Total energy per rank (pJ)
system.physmem_0.averagePower              667.869445                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   3685813216724                       # Time in different power states
system.physmem_0.memoryStateTime::REF    127934040000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     17956780776                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  161655480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   87978000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 390663000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                295410240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           250238982240                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            95244065640                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2234394426750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             2580813181350                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.044329                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   3685435461238                       # Time in different power states
system.physmem_1.memoryStateTime::REF    127934040000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     18309070012                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
system.cpu0.numCycles                       810473886                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   70312072                       # Number of instructions committed
system.cpu0.committedOps                    143658243                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            131612768                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                     897074                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     13988759                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   131612768                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads          240911367                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         113282572                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            82064957                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           54880945                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     13139441                       # number of memory refs
system.cpu0.num_load_insts                    9809284                       # Number of load instructions
system.cpu0.num_store_insts                   3330157                       # Number of store instructions
system.cpu0.num_idle_cycles              769348747.137634                       # Number of idle cycles
system.cpu0.num_busy_cycles              41125138.862366                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.050742                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.949258                       # Percentage of idle cycles
system.cpu0.Branches                         15218344                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                83498      0.06%      0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu                130336285     90.73%     90.78% # Class of executed instruction
system.cpu0.op_class::IntMult                   55624      0.04%     90.82% # Class of executed instruction
system.cpu0.op_class::IntDiv                    45353      0.03%     90.85% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.85% # Class of executed instruction
system.cpu0.op_class::MemRead                 9807642      6.83%     97.68% # Class of executed instruction
system.cpu0.op_class::MemWrite                3330157      2.32%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 143658559                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          1637472                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999430                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           19610556                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1637984                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            11.972373                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   233.382237                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   253.425972                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data    25.191221                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.455825                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.494973                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.049202                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          251                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88313667                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88313667                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      4629522                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      2541915                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4295165                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11466602                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3206369                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1799760                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      3076031                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       8082160                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        19345                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data         9882                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        30831                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        60058                       # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data      7835891                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      4341675                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      7371196                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        19548762                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      7855236                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      4351557                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      7402027                       # number of overall hits
system.cpu0.dcache.overall_hits::total       19608820                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       342984                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       163194                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       822092                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1328270                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       120211                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        69264                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       136170                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       325645                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       144505                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        65147                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       196531                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       406183                       # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data       463195                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       232458                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       958262                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1653915                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       607700                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       297605                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1154793                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2060098                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2262546000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  12291465500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  14554011500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2775957490                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   4654158371                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   7430115861                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   5038503490                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  16945623871                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  21984127361                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   5038503490                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  16945623871                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  21984127361                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      4972506                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      2705109                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      5117257                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     12794872                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3326580                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1869024                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      3212201                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      8407805                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       163850                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        75029                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       227362                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       466241                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8299086                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      4574133                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      8329458                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     21202677                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      8462936                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      4649162                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      8556820                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     21668918                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.068976                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.060328                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.160651                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.103813                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.036137                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.037059                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.042391                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.038731                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.881935                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.868291                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.864397                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.871187                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.055813                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.050820                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.115045                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.078005                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.071807                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.064013                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.134956                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.095072                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13864.149417                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14951.447648                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10957.118282                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40077.926340                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34179.028942                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 22816.612756                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21674.898218                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17683.706409                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13292.174846                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16930.170830                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14674.165734                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 10671.398817                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       195153                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            22760                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     8.574385                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      1547245                       # number of writebacks
system.cpu0.dcache.writebacks::total          1547245                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           49                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       383157                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       383206                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1554                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        32300                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        33854                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         1603                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       415457                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       417060                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         1603                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       415457                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       417060                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       163145                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       438935                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       602080                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        67710                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       103870                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       171580                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        65147                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       193119                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       258266                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       230855                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       542805                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       773660                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       296002                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       735924                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1031926                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       186313                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       204652                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total       390965                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3641                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         3691                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total         7332                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       189954                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       208343                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total       398297                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2099080000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5941231000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8040311000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2625649990                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3973863872                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6599513862                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    969909500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2805652000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3775561500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4724729990                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9915094872                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  14639824862                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5694639490                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  12720746872                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  18415386362                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30666876000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33145024000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63811900000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    650679500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    751025500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1401705000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31317555500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33896049500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65213605000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.060310                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.085775                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.047056                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036227                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.032336                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.020407                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.868291                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.849390                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.553932                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.050470                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065167                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.036489                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.063668                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.086004                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.047622                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12866.345889                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13535.559935                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13354.223691                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38777.876089                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38258.052104                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38463.188379                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14888.014797                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14528.099255                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14618.887116                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20466.223344                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18266.402984                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18922.814753                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19238.516936                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17285.408374                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17845.646260                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164598.691449                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 161957.977445                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163216.400445                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178709.008514                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 203474.803576                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 191176.350245                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164869.155164                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162693.488622                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163731.097648                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements           865313                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.808042                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          127930489                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           865825                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           147.755596                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle     149027837500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   256.241174                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   140.482462                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst   114.084406                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.500471                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.274380                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.222821                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997672                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          300                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        129687214                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       129687214                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     85494784                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     39252405                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3183300                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      127930489                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     85494784                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     39252405                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3183300                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       127930489                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     85494784                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     39252405                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3183300                       # number of overall hits
system.cpu0.icache.overall_hits::total      127930489                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       295547                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       174112                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       421231                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       890890                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       295547                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       174112                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       421231                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        890890                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       295547                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       174112                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       421231                       # number of overall misses
system.cpu0.icache.overall_misses::total       890890                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2498575500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5836919481                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   8335494981                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2498575500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   5836919481                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   8335494981                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2498575500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   5836919481                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   8335494981                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     85790331                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     39426517                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      3604531                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    128821379                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     85790331                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     39426517                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      3604531                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    128821379                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     85790331                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     39426517                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      3604531                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    128821379                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003445                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004416                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.116862                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.006916                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003445                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004416                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.116862                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.006916                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003445                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004416                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.116862                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.006916                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14350.392276                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13856.813675                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9356.368329                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14350.392276                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13856.813675                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9356.368329                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14350.392276                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13856.813675                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9356.368329                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4826                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              303                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.927393                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        25055                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        25055                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        25055                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        25055                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        25055                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        25055                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       174112                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       396176                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       570288                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       174112                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       396176                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       570288                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       174112                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       396176                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       570288                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2324463500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5197379983                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   7521843483                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2324463500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5197379983                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   7521843483                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2324463500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5197379983                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   7521843483                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004416                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.109911                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004427                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004416                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.109911                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.004427                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004416                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.109911                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.004427                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13350.392276                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13118.866320                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13189.552442                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13350.392276                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13118.866320                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13189.552442                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13350.392276                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13118.866320                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13189.552442                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                      2606018119                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   35722790                       # Number of instructions committed
system.cpu1.committedOps                     69377917                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             64437935                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     498036                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      6548156                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    64437935                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads          119381439                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          55453390                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            36402445                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           27104510                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      4834095                       # number of memory refs
system.cpu1.num_load_insts                    2964009                       # Number of load instructions
system.cpu1.num_store_insts                   1870086                       # Number of store instructions
system.cpu1.num_idle_cycles              2478102522.985643                       # Number of idle cycles
system.cpu1.num_busy_cycles              127915596.014357                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.049085                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.950915                       # Percentage of idle cycles
system.cpu1.Branches                          7225753                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                35671      0.05%      0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu                 64456455     92.91%     92.96% # Class of executed instruction
system.cpu1.op_class::IntMult                   31131      0.04%     93.00% # Class of executed instruction
system.cpu1.op_class::IntDiv                    22623      0.03%     93.03% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.03% # Class of executed instruction
system.cpu1.op_class::MemRead                 2962280      4.27%     97.30% # Class of executed instruction
system.cpu1.op_class::MemWrite                1870086      2.70%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  69378246                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups               29560975                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         29560975                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           321330                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            26625449                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               26036610                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            97.788435                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 603794                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             66654                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                       155113045                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles          11047280                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                     145686023                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   29560975                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          26640404                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                    142542790                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 677515                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                    104928                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles                5475                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             8867                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        68985                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles           22                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          511                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  3604542                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               166149                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   3283                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples         154116964                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.860489                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            3.036370                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                98277439     63.77%     63.77% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  921613      0.60%     64.37% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                23771065     15.42%     79.79% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  603849      0.39%     80.18% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  843324      0.55%     80.73% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  864608      0.56%     81.29% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  573617      0.37%     81.66% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  772001      0.50%     82.16% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                27489448     17.84%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total           154116964                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.190577                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.939225                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                10113688                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             93745988                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 23732554                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles              5061206                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                339409                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts             283817902                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                339409                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                12262766                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               76655623                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       4610961                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 26368994                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles             12755160                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts             282570010                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents               203292                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents               5910187                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                 59652                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               4622392                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands          337562699                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            617313701                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       378956511                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups              176                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps            325317107                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                12245592                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            169706                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        171154                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                 24674635                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6903065                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3842483                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           404867                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          342392                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                 280633357                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             431682                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                278499537                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued           103065                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        9014489                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     13791367                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved         66778                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples    154116964                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.807066                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       2.400549                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           90926640     59.00%     59.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            5330208      3.46%     62.46% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            3853102      2.50%     64.96% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            3864237      2.51%     67.46% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4           22585971     14.66%     82.12% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5            2780196      1.80%     83.92% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6           24046184     15.60%     99.53% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             494962      0.32%     99.85% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8             235464      0.15%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total      154116964                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                1774419     86.10%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.10% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                221659     10.76%     96.86% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                64684      3.14%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            87958      0.03%      0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu            267524922     96.06%     96.09% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               58980      0.02%     96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                56493      0.02%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                 63      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             7208859      2.59%     98.72% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3562262      1.28%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total             278499537                       # Type of FU issued
system.cpu2.iq.rate                          1.795462                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    2060762                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.007400                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         713279610                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes        290083917                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses    276907807                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                255                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes               236                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses          101                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses             280472218                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                    123                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          745560                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1225052                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         5875                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         5188                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       625672                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads       750058                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        26954                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                339409                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles               70544458                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles              3078967                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts          281065039                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            38553                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6903084                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3842483                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            256263                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                170697                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents              2578390                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          5188                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        180466                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       193564                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              374030                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts            277914745                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              7063605                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           530025                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
system.cpu2.iew.exec_refs                    10537501                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                28240197                       # Number of branches executed
system.cpu2.iew.exec_stores                   3473896                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.791692                       # Inst execution rate
system.cpu2.iew.wb_sent                     277728046                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                    276907908                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                215869899                       # num instructions producing a value
system.cpu2.iew.wb_consumers                354183211                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.785201                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.609487                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        9010167                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         364904                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           325088                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples    152771285                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.780770                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.657176                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     94646882     61.95%     61.95% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4418156      2.89%     64.85% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1318603      0.86%     65.71% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3     24750822     16.20%     81.91% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       992364      0.65%     82.56% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       731797      0.48%     83.04% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       443039      0.29%     83.33% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7     23300929     15.25%     98.58% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      2168693      1.42%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total    152771285                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts           137969360                       # Number of instructions committed
system.cpu2.commit.committedOps             272050550                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8894843                       # Number of memory references committed
system.cpu2.commit.loads                      5678032                       # Number of loads committed
system.cpu2.commit.membars                     160530                       # Number of memory barriers committed
system.cpu2.commit.branches                  27847068                       # Number of branches committed
system.cpu2.commit.fp_insts                        48                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                248702825                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              458806                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        52824      0.02%      0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu       262991815     96.67%     96.69% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          56918      0.02%     96.71% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv           54179      0.02%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        5677987      2.09%     98.82% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       3216811      1.18%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total        272050550                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              2168693                       # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads                   431630642                       # The number of ROB reads
system.cpu2.rob.rob_writes                  563473683                       # The number of ROB writes
system.cpu2.timesIdled                         116646                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                         996081                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  4908046353                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                  137969360                       # Number of Instructions Simulated
system.cpu2.committedOps                    272050550                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.124257                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.124257                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.889476                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.889476                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               370420908                       # number of integer regfile reads
system.cpu2.int_regfile_writes              221942656                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    73069                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                141352578                       # number of cc regfile reads
system.cpu2.cc_regfile_writes               108476747                       # number of cc regfile writes
system.cpu2.misc_regfile_reads               90603281                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                149391                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq              3552124                       # Transaction distribution
system.iobus.trans_dist::ReadResp             3552124                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57703                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57703                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1656                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1656                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7080216                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1182                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27854                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      7124404                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95250                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95250                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3312                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3312                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                 7222966                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3540108                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2364                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13927                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total      3568437                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  6602845                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              2765072                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                28000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              5295000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 1000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                28000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            140109000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy              421000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy               86000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            11369000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                4000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           144756051                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1032000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           299839000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            30990000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1161000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47570                       # number of replacements
system.iocache.tags.tagsinuse                0.092294                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47586                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5000591335509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.092294                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005768                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.005768                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428625                       # Number of tag accesses
system.iocache.tags.data_accesses              428625                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          905                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              905                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide          905                       # number of demand (read+write) misses
system.iocache.demand_misses::total               905                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          905                       # number of overall misses
system.iocache.overall_misses::total              905                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    128938756                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    128938756                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   3283387295                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   3283387295                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    128938756                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    128938756                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    128938756                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    128938756                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          905                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            905                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          905                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             905                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          905                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            905                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142473.763536                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 142473.763536                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70277.981485                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 70277.981485                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 142473.763536                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 142473.763536                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 142473.763536                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 142473.763536                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           548                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   46                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    11.913043                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          771                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          771                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        27816                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        27816                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          771                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          771                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          771                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          771                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     90388756                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     90388756                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1892587295                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   1892587295                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     90388756                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     90388756                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     90388756                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     90388756                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.851934                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.851934                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.595377                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.595377                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.851934                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.851934                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.851934                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.851934                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 117235.740597                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68039.520240                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68039.520240                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 117235.740597                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 117235.740597                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   105297                       # number of replacements
system.l2c.tags.tagsinuse                64829.932138                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4653506                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169379                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    27.473925                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   51173.407982                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.134359                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1534.003878                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4961.516829                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      244.491161                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1538.007484                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker     8.330522                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1242.728330                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     4127.311591                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.780844                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.023407                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.075707                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.003731                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.023468                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000127                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.018963                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.062978                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.989226                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        64082                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3909                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         7185                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52613                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.977814                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 41530530                       # Number of tag accesses
system.l2c.tags.data_accesses                41530530                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        18603                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker        10268                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        13451                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         7422                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        62068                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        13128                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 124940                       # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
system.l2c.Writeback_hits::writebacks         1547245                       # number of Writeback hits
system.l2c.Writeback_hits::total              1547245                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              73                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              62                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data             120                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 255                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            56139                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            39496                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            63875                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               159510                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        289595                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        170749                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst        390398                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total            850742                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       472949                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       223727                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data       618198                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          1314874                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         18603                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker         10270                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              289595                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              529088                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         13451                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          7422                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              170749                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              263223                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         62068                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         13128                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              390398                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              682073                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2450068                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        18603                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker        10270                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             289595                       # number of overall hits
system.l2c.overall_hits::cpu0.data             529088                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        13451                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         7422                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             170749                       # number of overall hits
system.l2c.overall_hits::cpu1.data             263223                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        62068                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        13128                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             390398                       # number of overall hits
system.l2c.overall_hits::cpu2.data             682073                       # number of overall hits
system.l2c.overall_hits::total                2450068                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           33                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                   38                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data           455                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           314                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           620                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1389                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          63544                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          27850                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          39321                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             130715                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         5939                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         3363                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst         5766                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           15068                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data        14540                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         4565                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data        13791                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          32896                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              5939                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             78084                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3363                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             32415                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           33                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              5766                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             53112                       # number of demand (read+write) misses
system.l2c.demand_misses::total                178717                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             5939                       # number of overall misses
system.l2c.overall_misses::cpu0.data            78084                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3363                       # number of overall misses
system.l2c.overall_misses::cpu1.data            32415                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           33                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             5766                       # number of overall misses
system.l2c.overall_misses::cpu2.data            53112                       # number of overall misses
system.l2c.overall_misses::total               178717                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      3062000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total        3062000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      5922500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data      7897000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     13819500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   2097810500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   3123724500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   5221535000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    269851500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst    492403500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total    762255000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    377324500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data   1213247000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1590571500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    269851500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2475135000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      3062000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    492403500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   4336971500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      7577423500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    269851500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2475135000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      3062000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    492403500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   4336971500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     7577423500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        18603                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        10273                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        13451                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7422                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        62101                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        13128                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             124978                       # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1547245                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1547245                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data          528                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          376                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          740                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1644                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       119683                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        67346                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data       103196                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           290225                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       295534                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       174112                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst       396164                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total        865810                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       487489                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       228292                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data       631989                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      1347770                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        18603                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        10275                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          295534                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          607172                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        13451                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7422                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          174112                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          295638                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        62101                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        13128                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          396164                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          735185                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2628785                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        18603                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        10275                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         295534                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         607172                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        13451                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7422                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         174112                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         295638                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        62101                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        13128                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         396164                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         735185                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2628785                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000487                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000531                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.000304                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.861742                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.835106                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.837838                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.844891                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.530936                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.413536                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.381032                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.450392                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.020096                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.019315                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.014555                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.017403                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.029826                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.019996                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.021822                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.024408                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000487                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.020096                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.128603                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.019315                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.109644                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000531                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.014555                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.072243                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.067985                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000487                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.020096                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.128603                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.019315                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.109644                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000531                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.014555                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.072243                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.067985                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 92787.878788                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 80578.947368                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18861.464968                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12737.096774                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  9949.244060                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75325.332136                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79441.634241                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 39945.951115                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80241.302409                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 85397.762747                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 50587.669233                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82655.969332                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 87973.823508                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 48351.516902                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80241.302409                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 76357.704766                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 92787.878788                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 85397.762747                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 81657.092559                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 42399.007929                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80241.302409                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 76357.704766                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 92787.878788                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 85397.762747                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 81657.092559                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 42399.007929                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               96985                       # number of writebacks
system.l2c.writebacks::total                    96985                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           33                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total              33                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks           60                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total           60                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          314                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          620                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          934                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        27850                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        39321                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         67171                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         3363                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5766                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total         9129                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         4565                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data        13791                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        18356                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3363                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        32415                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           33                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         5766                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        53112                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            94689                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3363                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        32415                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           33                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         5766                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        53112                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           94689                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data       186313                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data       204652                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total       390965                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3641                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         3691                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total         7332                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data       189954                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data       208343                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       398297                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2732000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total      2732000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      7099500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     13006500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     20106000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1819310500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2730514500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   4549825000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    236221500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    434743500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total    670965000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    331674500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1075337000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1407011500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    236221500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   2150985000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      2732000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    434743500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   3805851500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6630533500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    236221500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   2150985000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2732000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    434743500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   3805851500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6630533500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28337960500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30586872000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  58924832500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    608808000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    708573000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1317381000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28946768500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31295445000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  60242213500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000531                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.000264                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.835106                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.837838                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.568127                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.413536                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.381032                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.231445                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.019315                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.014555                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010544                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.019996                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.021822                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.013620                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.019315                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.109644                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000531                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014555                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.072243                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.036020                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.019315                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.109644                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000531                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014555                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.072243                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.036020                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 82787.878788                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22609.872611                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20978.225806                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21526.766595                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65325.332136                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69441.634241                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 67734.960027                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70241.302409                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75397.762747                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73498.192573                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72655.969332                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77973.823508                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76651.312922                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70241.302409                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66357.704766                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75397.762747                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71657.092559                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 70024.327007                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70241.302409                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66357.704766                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75397.762747                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71657.092559                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 70024.327007                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152098.675347                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149457.967672                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150716.387656                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167209.008514                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 191973.178001                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 179675.531915                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152388.307169                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150211.166202                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 151249.478404                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq             5066901                       # Transaction distribution
system.membus.trans_dist::ReadResp            5115808                       # Transaction distribution
system.membus.trans_dist::WriteReq              13888                       # Transaction distribution
system.membus.trans_dist::WriteResp             13888                       # Transaction distribution
system.membus.trans_dist::Writeback            143652                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8856                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             1645                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1645                       # Transaction distribution
system.membus.trans_dist::ReadExReq            130459                       # Transaction distribution
system.membus.trans_dist::ReadExResp           130459                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         48907                       # Transaction distribution
system.membus.trans_dist::MessageReq             1656                       # Transaction distribution
system.membus.trans_dist::MessageResp            1656                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3312                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3312                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7124404                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3037174                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       465190                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total     10626768                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       142086                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       142086                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               10772166                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3568437                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6074345                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17606208                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     27248990                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3023616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3023616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                30279230                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              694                       # Total snoops (count)
system.membus.snoop_fanout::samples           5463095                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.000303                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.017408                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 5461439     99.97%     99.97% # Request fanout histogram
system.membus.snoop_fanout::2                    1656      0.03%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total             5463095                       # Request fanout histogram
system.membus.reqLayer0.occupancy           232635000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           304127000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             2322000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy           583726731                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1161000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1349926167                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           52433855                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq            5228525                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           7442369                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13890                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13890                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          1636010                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          961008                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1644                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1644                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           290225                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          290225                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq        865835                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      1348541                       # Transaction distribution
system.toL2Bus.trans_dist::MessageReq            1161                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        27816                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2596558                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15078411                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        72306                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       219403                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17966678                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55412672                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213513438                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       261576                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       779088                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              269966774                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          176011                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         10394757                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.029410                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.168953                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               10089048     97.06%     97.06% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 305709      2.94%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           10394757                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         2840392499                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           358500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         856033294                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1941516813                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          27469982                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         100352159                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------