blob: 551b52f89e36f9284755725960660a895faddff7 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
|
---------- Begin Simulation Statistics ----------
sim_seconds 5.139589 # Number of seconds simulated
sim_ticks 5139589353000 # Number of ticks simulated
final_tick 5139589353000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 286755 # Simulator instruction rate (inst/s)
host_op_rate 569759 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6048900638 # Simulator tick rate (ticks/s)
host_mem_usage 936564 # Number of bytes of host memory used
host_seconds 849.67 # Real time elapsed on the host
sim_insts 243647713 # Number of instructions simulated
sim_ops 484108731 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2450688 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 424832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5722240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 151040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1810944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 1920 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 372032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2837824 # Number of bytes read from this memory
system.physmem.bytes_read::total 13771904 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 424832 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 151040 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 372032 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 947904 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9105344 # Number of bytes written to this memory
system.physmem.bytes_written::total 9105344 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 38292 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 6638 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 89410 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 28296 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 30 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 5813 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 44341 # Number of read requests responded to by this memory
system.physmem.num_reads::total 215186 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 142271 # Number of write requests responded to by this memory
system.physmem.num_writes::total 142271 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 476826 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 82659 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1113365 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 29388 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 352352 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 374 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 72386 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 552150 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2679573 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 82659 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 29388 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 72386 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 184432 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1771609 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1771609 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1771609 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 476826 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 82659 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1113365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 29388 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 352352 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 72386 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 552150 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4451182 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 96603 # Total number of read requests seen
system.physmem.writeReqs 74912 # Total number of write requests seen
system.physmem.cpureqs 172248 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 6182592 # Total number of bytes read from memory
system.physmem.bytesWritten 4794368 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 6182592 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4794368 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 732 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 5743 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 5750 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 5839 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 6096 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 6289 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 6214 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 5688 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 5956 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 5856 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 5878 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 6204 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 6723 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 6230 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 5996 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 6010 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 6119 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 4526 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 4556 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 4662 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 4674 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 5230 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 4937 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 4457 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 4557 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 4265 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 4556 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 4962 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 5050 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 4875 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 4641 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 4582 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 4382 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
system.physmem.totGap 5136024228000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 96603 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 74912 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 77105 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 8744 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3065 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1211 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1026 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 838 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 498 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 448 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 435 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 399 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 376 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 368 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 338 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 356 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 385 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 352 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 279 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 202 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2892 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2985 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 3260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 3272 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 3272 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 3268 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 3266 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 3265 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 3261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 3262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 3257 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 3254 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 3251 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 3250 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 3246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 3242 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3242 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3240 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 3239 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 3238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 3231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 3229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 417 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 301 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 33252 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 329.902562 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 152.864384 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1038.972369 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 14693 44.19% 44.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 5121 15.40% 59.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 3144 9.46% 69.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 2114 6.36% 75.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 1414 4.25% 79.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 1109 3.34% 82.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 834 2.51% 85.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 672 2.02% 87.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 527 1.58% 89.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 500 1.50% 90.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 311 0.94% 91.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 308 0.93% 92.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 231 0.69% 93.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 204 0.61% 93.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 157 0.47% 94.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 279 0.84% 95.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 147 0.44% 95.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 117 0.35% 95.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 74 0.22% 96.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 80 0.24% 96.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 100 0.30% 96.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 111 0.33% 96.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 291 0.88% 97.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 116 0.35% 98.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 63 0.19% 98.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 43 0.13% 98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 35 0.11% 98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 34 0.10% 98.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 18 0.05% 98.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 13 0.04% 98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 14 0.04% 98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 17 0.05% 98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 9 0.03% 98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243 4 0.01% 98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 7 0.02% 99.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371 10 0.03% 99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 7 0.02% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 1 0.00% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563 6 0.02% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 8 0.02% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 9 0.03% 99.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755 6 0.02% 99.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 2 0.01% 99.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 3 0.01% 99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947 4 0.01% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 3 0.01% 99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 1 0.00% 99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331 2 0.01% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395 6 0.02% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 5 0.02% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 2 0.01% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 2 0.01% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715 3 0.01% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971 3 0.01% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099 5 0.02% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291 3 0.01% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187 1 0.00% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379 2 0.01% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507 1 0.00% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827 2 0.01% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019 4 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723 5 0.02% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851 4 0.01% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171 2 0.01% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7491 2 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555 3 0.01% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811 2 0.01% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 29 0.09% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8259 3 0.01% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8771 2 0.01% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9539 2 0.01% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859 2 0.01% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11011 2 0.01% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14083 2 0.01% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14851 2 0.01% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915 11 0.03% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979 2 0.01% 99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043 4 0.01% 99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15107 4 0.01% 99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171 3 0.01% 99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 2 0.01% 99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427 2 0.01% 99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491 2 0.01% 99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15936-15939 4 0.01% 99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16003 2 0.01% 99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16131 5 0.02% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195 2 0.01% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16259 5 0.02% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16323 2 0.01% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 27 0.08% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16963 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 33252 # Bytes accessed per row activation
system.physmem.totQLat 1788062000 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 3723402000 # Sum of mem lat for all requests
system.physmem.totBusLat 482955000 # Total cycles spent in databus access
system.physmem.totBankLat 1452385000 # Total cycles spent in bank access
system.physmem.avgQLat 18511.68 # Average queueing delay per request
system.physmem.avgBankLat 15036.44 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 38548.13 # Average memory access latency
system.physmem.avgRdBW 1.20 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.93 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1.20 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.93 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.11 # Average write queue length over time
system.physmem.readRowHits 84146 # Number of row buffer hits during reads
system.physmem.writeRowHits 54105 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.12 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 72.22 # Row buffer hit rate for writes
system.physmem.avgGap 29945044.04 # Average gap between requests
system.membus.throughput 6414834 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 427545 # Transaction distribution
system.membus.trans_dist::ReadResp 427545 # Transaction distribution
system.membus.trans_dist::WriteReq 5661 # Transaction distribution
system.membus.trans_dist::WriteResp 5661 # Transaction distribution
system.membus.trans_dist::Writeback 74912 # Transaction distribution
system.membus.trans_dist::UpgradeReq 735 # Transaction distribution
system.membus.trans_dist::UpgradeResp 735 # Transaction distribution
system.membus.trans_dist::ReadExReq 72970 # Transaction distribution
system.membus.trans_dist::ReadExResp 72970 # Transaction distribution
system.membus.trans_dist::MessageReq 216 # Transaction distribution
system.membus.trans_dist::MessageResp 216 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 432 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312952 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 1030222 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 54502 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 54502 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 273592 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave 312952 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1085156 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total 864 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 9889556 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2243648 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 2243648 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 10976960 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 12134068 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 32713165 # Total data (bytes)
system.membus.snoop_data_through_bus 256448 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 793885999 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 164366000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 314753000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer3.occupancy 432000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 216000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1632166487 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer4.occupancy 175306750 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.l2c.tags.replacements 104154 # number of replacements
system.l2c.tags.tagsinuse 64818.882502 # Cycle average of tags in use
system.l2c.tags.total_refs 3632248 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 168346 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 21.576087 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 51171.986670 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125486 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 1262.785068 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 4574.642727 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 231.301246 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1356.639626 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.163681 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 0.039070 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1464.364249 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 4745.834679 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.780823 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.019269 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.069804 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.003529 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.020701 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.022344 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.072416 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.989058 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 20178 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 11162 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 357762 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 528228 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 4903 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 153273 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 226490 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 46782 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 8793 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 321700 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 546165 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2227865 # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
system.l2c.Writeback_hits::writebacks 1544497 # number of Writeback hits
system.l2c.Writeback_hits::total 1544497 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 143 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 76 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 255 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 71037 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 43117 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 57018 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 171172 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 20178 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 11164 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 357762 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 599265 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 4903 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 153273 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 269607 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 46782 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 8793 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 321700 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 603183 # number of demand (read+write) hits
system.l2c.demand_hits::total 2399039 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 20178 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 11164 # number of overall hits
system.l2c.overall_hits::cpu0.inst 357762 # number of overall hits
system.l2c.overall_hits::cpu0.data 599265 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 4903 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits
system.l2c.overall_hits::cpu1.inst 153273 # number of overall hits
system.l2c.overall_hits::cpu1.data 269607 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 46782 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 8793 # number of overall hits
system.l2c.overall_hits::cpu2.inst 321700 # number of overall hits
system.l2c.overall_hits::cpu2.data 603183 # number of overall hits
system.l2c.overall_hits::total 2399039 # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 6638 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 13571 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 2360 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4761 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 31 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 5815 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 14526 # number of ReadReq misses
system.l2c.ReadReq_misses::total 47708 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 712 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 243 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 390 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1345 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 76337 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 23772 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 30004 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 130113 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 6638 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 89908 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2360 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 28533 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 31 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 5815 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 44530 # number of demand (read+write) misses
system.l2c.demand_misses::total 177821 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
system.l2c.overall_misses::cpu0.inst 6638 # number of overall misses
system.l2c.overall_misses::cpu0.data 89908 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2360 # number of overall misses
system.l2c.overall_misses::cpu1.data 28533 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 31 # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu2.inst 5815 # number of overall misses
system.l2c.overall_misses::cpu2.data 44530 # number of overall misses
system.l2c.overall_misses::total 177821 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst 185186500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 369106743 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3097499 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker 88750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 524253495 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 1205998231 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2287731218 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 2444401 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 4607806 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 7052207 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1673798209 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 2232599179 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 3906397388 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 185186500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 2042904952 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 3097499 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker 88750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 524253495 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 3438597410 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 6194128606 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 185186500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 2042904952 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 3097499 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker 88750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 524253495 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 3438597410 # number of overall miss cycles
system.l2c.overall_miss_latency::total 6194128606 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 20178 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 11167 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 364400 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 541799 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 4903 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 155633 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 231251 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 46813 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 8794 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 327515 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 560691 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2275573 # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1544497 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1544497 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 855 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 279 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 466 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1600 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 147374 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 66889 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 87022 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 301285 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 20178 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 11169 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 364400 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 689173 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 4903 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 155633 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 298140 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker 46813 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker 8794 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 327515 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 647713 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2576860 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 20178 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 11169 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 364400 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 689173 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 4903 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 155633 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 298140 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker 46813 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker 8794 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 327515 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 647713 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2576860 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000448 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.018216 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.025048 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.015164 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.020588 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000662 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000114 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.017755 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.025907 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.020965 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.832749 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870968 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.836910 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.840625 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.517981 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.355395 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.344786 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.431860 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000448 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.018216 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.130458 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.015164 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.095703 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000662 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker 0.000114 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.017755 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.068750 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.069007 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000448 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.018216 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.130458 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.015164 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.095703 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000662 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker 0.000114 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.017755 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.068750 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.069007 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78468.855932 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77527.146188 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 99919.322581 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88750 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 90155.373173 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 83023.422208 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 47952.779785 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10059.263374 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11814.887179 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 5243.276580 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70410.491713 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74410.051293 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 30023.113663 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 78468.855932 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 71597.972593 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 99919.322581 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 90155.373173 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 77219.793622 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 34833.504513 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 78468.855932 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 71597.972593 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 99919.322581 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 90155.373173 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 77219.793622 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 34833.504513 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 95604 # number of writebacks
system.l2c.writebacks::total 95604 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.dtb.walker 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.dtb.walker 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.inst 2360 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 4761 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 30 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 5813 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 14526 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 27491 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 243 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 390 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 633 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 23772 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 30004 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 53776 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2360 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 28533 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 30 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 5813 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 44530 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 81267 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2360 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 28533 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 30 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 5813 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 44530 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 81267 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 155365000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 308892757 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2656751 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 76250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 450701255 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1022394749 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1940086762 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2530241 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3952388 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 6482629 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1375043791 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1855159821 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 3230203612 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 155365000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1683936548 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2656751 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 76250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 450701255 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 2877554570 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 5170290374 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 155365000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1683936548 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2656751 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 76250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 450701255 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 2877554570 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 5170290374 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28552490000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30418768500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 58971258500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 380243500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 689742500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1069986000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28932733500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31108511000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 60041244500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015164 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020588 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000641 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000114 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017749 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.025907 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.012081 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870968 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.836910 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.395625 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.355395 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.344786 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.178489 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015164 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.095703 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000641 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000114 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017749 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.068750 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.031537 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015164 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.095703 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000641 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000114 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017749 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.068750 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.031537 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65832.627119 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64879.806133 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 88558.366667 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 77533.331326 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70383.777296 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 70571.705722 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10412.514403 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10134.328205 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10241.120063 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57842.999790 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61830.416644 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 60067.755356 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65832.627119 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59017.157257 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 88558.366667 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77533.331326 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64620.583202 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 63621.031587 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65832.627119 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59017.157257 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 88558.366667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77533.331326 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64620.583202 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 63621.031587 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 47579 # number of replacements
system.iocache.tags.tagsinuse 0.100447 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 4999807573509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.100447 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006278 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.006278 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses
system.iocache.ReadReq_misses::total 914 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide 47634 # number of demand (read+write) misses
system.iocache.demand_misses::total 47634 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47634 # number of overall misses
system.iocache.overall_misses::total 47634 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 16928907 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 16928907 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 4287176010 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 4287176010 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 4304104917 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4304104917 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 4304104917 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4304104917 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 47634 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47634 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47634 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47634 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 18521.780088 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 18521.780088 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 91763.185146 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 91763.185146 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 90357.830898 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 90357.830898 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 90357.830898 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 90357.830898 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 61504 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 5648 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.889518 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 149 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 149 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 19296 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 19296 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 19445 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 19445 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 19445 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 19445 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 9180907 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 9180907 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3283180510 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 3283180510 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3292361417 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 3292361417 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3292361417 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 3292361417 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.163020 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.163020 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.413014 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 0.413014 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.408217 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.408217 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.408217 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.408217 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 61616.825503 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 61616.825503 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 170148.243677 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 170148.243677 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 169316.606686 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 169316.606686 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 169316.606686 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 169316.606686 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.toL2Bus.throughput 52172743 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 1753367 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 1753366 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 5661 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 5661 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 894976 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 745 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 745 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 173207 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 153920 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 966317 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3599461 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 26176 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 114965 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count 4706919 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 30921472 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118979348 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 89784 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 413728 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size 150404332 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 267998065 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 148408 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4987080585 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 706500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 2176927347 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4676438168 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 14970214 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 63358037 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 1260736 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 151186 # Transaction distribution
system.iobus.trans_dist::ReadResp 151186 # Transaction distribution
system.iobus.trans_dist::WriteReq 24735 # Transaction distribution
system.iobus.trans_dist::WriteResp 24735 # Transaction distribution
system.iobus.trans_dist::MessageReq 216 # Transaction distribution
system.iobus.trans_dist::MessageResp 216 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4266 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 290624 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 38 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15770 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 312952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 38890 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 38890 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 432 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4266 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290624 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 38 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.com_1.pio 15770 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side 38890 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 352274 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2412 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 145312 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 76 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7885 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 159887 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1236136 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1236136 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 864 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2412 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145312 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 76 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.com_1.pio 7885 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side 1236136 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 1396887 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 6479664 # Total data (bytes)
system.iobus.reqLayer0.occupancy 492564 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 3525000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 145313000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 31000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 11833000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 175039167 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 307513000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 20042250 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer2.occupancy 216000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.numCycles 1821353005 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 73292155 # Number of instructions committed
system.cpu0.committedOps 148692338 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 136997121 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 1072392 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 14299557 # number of instructions that are conditional controls
system.cpu0.num_int_insts 136997121 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 337067923 # number of times the integer registers were read
system.cpu0.num_int_register_writes 173978676 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 14736464 # number of memory refs
system.cpu0.num_load_insts 10677140 # Number of load instructions
system.cpu0.num_store_insts 4059324 # Number of store instructions
system.cpu0.num_idle_cycles 1078995887905.232788 # Number of idle cycles
system.cpu0.num_busy_cycles -1077174534900.232788 # Number of busy cycles
system.cpu0.not_idle_fraction -591.414477 # Percentage of non-idle cycles
system.cpu0.idle_fraction 592.414477 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 847048 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.817647 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 129995405 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 847560 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 153.376050 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 147328649500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 320.566465 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 97.238420 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 93.012763 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.626106 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.189919 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.181666 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997691 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 89325030 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 38126450 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2543925 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 129995405 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 89325030 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 38126450 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2543925 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 129995405 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 89325030 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 38126450 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2543925 # number of overall hits
system.cpu0.icache.overall_hits::total 129995405 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 364401 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 155633 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 345614 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 865648 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 364401 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 155633 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 345614 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 865648 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 364401 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 155633 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 345614 # number of overall misses
system.cpu0.icache.overall_misses::total 865648 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2193404000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5014378720 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 7207782720 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 2193404000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 5014378720 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 7207782720 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 2193404000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 5014378720 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 7207782720 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 89689431 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 38282083 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 2889539 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 130861053 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 89689431 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 38282083 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 2889539 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 130861053 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 89689431 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 38282083 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 2889539 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 130861053 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004063 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004065 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.119609 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.006615 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004063 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004065 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.119609 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.006615 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004063 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004065 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.119609 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.006615 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14093.437767 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14508.609952 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8326.459161 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14093.437767 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14508.609952 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8326.459161 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14093.437767 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14508.609952 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8326.459161 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 6927 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 238 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.105042 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 18078 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 18078 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 18078 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 18078 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 18078 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 18078 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 155633 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 327536 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 483169 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 155633 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 327536 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 483169 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 155633 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 327536 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 483169 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1880996000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4143986636 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 6024982636 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1880996000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4143986636 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 6024982636 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1880996000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4143986636 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 6024982636 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004065 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.113352 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003692 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004065 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.113352 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.003692 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004065 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.113352 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.003692 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12086.099992 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12469.721021 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12086.099992 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12469.721021 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12086.099992 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12469.721021 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 1634474 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999389 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 19647501 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1634986 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 12.016923 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 379.364018 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 126.391213 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.244158 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.740945 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.246858 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012196 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 5614384 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 2225977 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 3715968 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 11556329 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3907488 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 1533784 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 2648186 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 8089458 # number of WriteReq hits
system.cpu0.dcache.demand_hits::cpu0.data 9521872 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 3759761 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 6364154 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 19645787 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 9521872 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 3759761 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 6364154 # number of overall hits
system.cpu0.dcache.overall_hits::total 19645787 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 541799 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 231251 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 917589 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1690639 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 148229 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 67168 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 99931 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 315328 # number of WriteReq misses
system.cpu0.dcache.demand_misses::cpu0.data 690028 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 298419 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1017520 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2005967 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 690028 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 298419 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1017520 # number of overall misses
system.cpu0.dcache.overall_misses::total 2005967 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3337683757 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15521474368 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 18859158125 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2326474532 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3256971146 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 5583445678 # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 5664158289 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 18778445514 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 24442603803 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 5664158289 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 18778445514 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 24442603803 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6156183 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 2457228 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4633557 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13246968 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4055717 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1600952 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2748117 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 8404786 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 10211900 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 4058180 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7381674 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 21651754 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 10211900 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 4058180 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 7381674 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 21651754 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.088009 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.094111 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.198031 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.127625 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036548 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.041955 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.036363 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.037518 # miss rate for WriteReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.067571 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.073535 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.137844 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.092647 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067571 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.073535 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137844 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.092647 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14433.164644 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16915.497426 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11155.047367 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34636.650369 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32592.200078 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17706.786831 # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18980.555156 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18455.111953 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 12184.948109 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18980.555156 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18455.111953 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12184.948109 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 172601 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 11703 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.748441 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1544497 # number of writebacks
system.cpu0.dcache.writebacks::total 1544497 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 356856 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 356856 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 12485 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 12485 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 369341 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 369341 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 369341 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 369341 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 231251 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 560733 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 791984 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 67168 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 87446 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 154614 # number of WriteReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 298419 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 648179 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 946598 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 298419 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 648179 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 946598 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2872959243 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8335143522 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11208102765 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2180545468 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2931248595 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5111794063 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 5053504711 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11266392117 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 16319896828 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5053504711 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11266392117 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 16319896828 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31052633000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33182784500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64235417500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 405522500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 732474500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1137997000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31458155500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33915259000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65373414500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.094111 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.121016 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.059786 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.041955 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031820 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018396 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.073535 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087809 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.043719 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.073535 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087809 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.043719 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12423.553814 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14864.727994 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14151.930803 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32464.052346 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33520.670986 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33061.650711 # average WriteReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16934.259250 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17381.606187 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17240.578184 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16934.259250 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17381.606187 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17240.578184 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 2606005785 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 34706075 # Number of instructions committed
system.cpu1.committedOps 67513326 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 62627092 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 413647 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 6441517 # number of instructions that are conditional controls
system.cpu1.num_int_insts 62627092 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 150899030 # number of times the integer registers were read
system.cpu1.num_int_register_writes 80614256 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 4252332 # number of memory refs
system.cpu1.num_load_insts 2649427 # Number of load instructions
system.cpu1.num_store_insts 1602905 # Number of store instructions
system.cpu1.num_idle_cycles 9584663693.774578 # Number of idle cycles
system.cpu1.num_busy_cycles -6978657908.774579 # Number of busy cycles
system.cpu1.not_idle_fraction -2.677913 # Percentage of non-idle cycles
system.cpu1.idle_fraction 3.677913 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 28549199 # Number of BP lookups
system.cpu2.branchPred.condPredicted 28549199 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 285864 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 26202333 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 25707724 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 98.112347 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 509000 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 57796 # Number of incorrect RAS predictions.
system.cpu2.numCycles 153739924 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 8861182 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 140768018 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 28549199 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 26216724 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 54013734 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 1344784 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 58192 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.BlockedCycles 24037963 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 3706 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 6519 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 19114 # Number of stall cycles due to pending traps
system.cpu2.fetch.IcacheWaitRetryStallCycles 569 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 2889543 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 128346 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 1609 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 88045773 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 3.152898 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 3.410636 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 34147694 38.78% 38.78% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 547423 0.62% 39.41% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 23764633 26.99% 66.40% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 284582 0.32% 66.72% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 557969 0.63% 67.35% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 795617 0.90% 68.26% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 319692 0.36% 68.62% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 484471 0.55% 69.17% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 27143692 30.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 88045773 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.185698 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.915624 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 10285454 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 22943626 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 41627806 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 1270133 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 1048147 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 276853450 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 7 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 1048147 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 11254615 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 13961054 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 3963789 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 41762702 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 5184927 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 275944284 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 6769 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 2459328 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 2061675 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.FullRegisterEvents 2717 # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands 329857779 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 599690764 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 599690564 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 200 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 320509391 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 9348388 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 136043 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 137064 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 11288733 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 5902057 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3230740 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 354441 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 291130 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 274390669 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 398438 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 272978735 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 57079 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 6609909 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 10125547 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 50893 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 88045773 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 3.100418 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 2.393656 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 25312226 28.75% 28.75% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 5904467 6.71% 35.46% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 3803238 4.32% 39.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 2580509 2.93% 42.71% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 25019730 28.42% 71.12% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 1259471 1.43% 72.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 23861754 27.10% 99.65% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 255558 0.29% 99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 48820 0.06% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 88045773 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 115953 32.52% 32.52% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 120 0.03% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 32.55% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 188030 52.73% 85.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 52485 14.72% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 70354 0.03% 0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 263570476 96.55% 96.58% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 51118 0.02% 96.60% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 46597 0.02% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 6213747 2.28% 98.89% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3026443 1.11% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 272978735 # Type of FU issued
system.cpu2.iq.rate 1.775588 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 356588 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.001306 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 634455588 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 281402142 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 271688146 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 29 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 273264957 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 12 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 613124 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 928259 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 6814 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 3642 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 478181 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 656152 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 10356 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 1048147 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 9348181 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 808638 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 274789107 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 65396 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 5902057 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3230758 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 220588 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 626855 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 4558 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 3642 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 161804 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 161245 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 323049 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 272529284 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 6113028 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 449451 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
system.cpu2.iew.exec_refs 9080043 # number of memory reference insts executed
system.cpu2.iew.exec_branches 27720555 # Number of branches executed
system.cpu2.iew.exec_stores 2967015 # Number of stores executed
system.cpu2.iew.exec_rate 1.772664 # Inst execution rate
system.cpu2.iew.wb_sent 272391201 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 271688152 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 212092617 # num instructions producing a value
system.cpu2.iew.wb_consumers 346983399 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.767193 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.611247 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 6884729 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 347545 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 288057 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 86997626 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 3.079430 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 2.871941 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 29972174 34.45% 34.45% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4215922 4.85% 39.30% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1166731 1.34% 40.64% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 24592469 28.27% 68.91% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 801811 0.92% 69.83% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 544306 0.63% 70.45% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 310409 0.36% 70.81% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 23365384 26.86% 97.67% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 2028420 2.33% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 86997626 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 135649483 # Number of instructions committed
system.cpu2.commit.committedOps 267903067 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 7726375 # Number of memory references committed
system.cpu2.commit.loads 4973798 # Number of loads committed
system.cpu2.commit.membars 163952 # Number of memory barriers committed
system.cpu2.commit.branches 27408076 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 244468826 # Number of committed integer instructions.
system.cpu2.commit.function_calls 411685 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 2028420 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 359731311 # The number of ROB reads
system.cpu2.rob.rob_writes 550627170 # The number of ROB writes
system.cpu2.timesIdled 462650 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 65694151 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 4912523731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 135649483 # Number of Instructions Simulated
system.cpu2.committedOps 267903067 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 135649483 # Number of Instructions Simulated
system.cpu2.cpi 1.133362 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.133362 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.882331 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.882331 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 500765277 # number of integer regfile reads
system.cpu2.int_regfile_writes 324464285 # number of integer regfile writes
system.cpu2.fp_regfile_reads 62550 # number of floating regfile reads
system.cpu2.fp_regfile_writes 62544 # number of floating regfile writes
system.cpu2.misc_regfile_reads 88091146 # number of misc regfile reads
system.cpu2.misc_regfile_writes 122333 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
|