path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.141168                       # Number of seconds simulated
sim_ticks                                5141168437500                       # Number of ticks simulated
final_tick                               5141168437500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 561125                       # Simulator instruction rate (inst/s)
host_op_rate                                  1115525                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            11816760555                       # Simulator tick rate (ticks/s)
host_mem_usage                                 973408                       # Number of bytes of host memory used
host_seconds                                   435.07                       # Real time elapsed on the host
sim_insts                                   244131065                       # Number of instructions simulated
sim_ops                                     485336254                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           377472                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4958144                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           201472                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2034880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         2368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           383296                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          3456256                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11442624                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       377472                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       201472                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       383296                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          962240                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9198208                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9198208                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              5898                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             77471                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3148                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             31795                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           37                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              5989                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             54004                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                178791                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          143722                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143722                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               73421                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              964400                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               39188                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              395801                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           461                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               74554                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              672271                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5515                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2225685                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          73421                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          39188                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          74554                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             187164                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1789128                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1789128                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1789128                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              73421                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             964400                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              39188                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             395801                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          461                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              74554                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             672271                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5515                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4014813                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         95417                       # Number of read requests accepted
system.physmem.writeReqs                        81462                       # Number of write requests accepted
system.physmem.readBursts                       95417                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      81462                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  6099840                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6848                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   5213440                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   6106688                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                5213568                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      107                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          21330                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                6364                       # Per bank write bursts
system.physmem.perBankRdBursts::1                5596                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5691                       # Per bank write bursts
system.physmem.perBankRdBursts::3                5690                       # Per bank write bursts
system.physmem.perBankRdBursts::4                6222                       # Per bank write bursts
system.physmem.perBankRdBursts::5                5617                       # Per bank write bursts
system.physmem.perBankRdBursts::6                5512                       # Per bank write bursts
system.physmem.perBankRdBursts::7                5018                       # Per bank write bursts
system.physmem.perBankRdBursts::8                6455                       # Per bank write bursts
system.physmem.perBankRdBursts::9                6386                       # Per bank write bursts
system.physmem.perBankRdBursts::10               5929                       # Per bank write bursts
system.physmem.perBankRdBursts::11               5798                       # Per bank write bursts
system.physmem.perBankRdBursts::12               5744                       # Per bank write bursts
system.physmem.perBankRdBursts::13               6558                       # Per bank write bursts
system.physmem.perBankRdBursts::14               6049                       # Per bank write bursts
system.physmem.perBankRdBursts::15               6681                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5937                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5551                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4927                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4762                       # Per bank write bursts
system.physmem.perBankWrBursts::4                5737                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5264                       # Per bank write bursts
system.physmem.perBankWrBursts::6                5028                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4496                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4483                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4823                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4660                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4592                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4759                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5475                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5045                       # Per bank write bursts
system.physmem.perBankWrBursts::15               5921                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
system.physmem.totGap                    5140168291000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   95417                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  81462                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     89320                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4643                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       843                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       184                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        44                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        34                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        34                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1349                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4416                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4395                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4340                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4383                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4398                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5388                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4638                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4893                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4936                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4337                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       33                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        3                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        41437                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      273.022082                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     164.972231                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     298.458037                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          16767     40.46%     40.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        10137     24.46%     64.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4304     10.39%     75.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2528      6.10%     81.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1659      4.00%     85.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1139      2.75%     88.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          786      1.90%     90.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          657      1.59%     91.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3460      8.35%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          41437                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4254                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        22.404325                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      181.210886                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            4251     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-6655            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9728-10239            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4254                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4254                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.149036                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.343940                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       10.936401                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                69      1.62%      1.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 7      0.16%      1.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                1      0.02%      1.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               8      0.19%      2.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            3652     85.85%     87.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              58      1.36%     89.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              99      2.33%     91.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              64      1.50%     93.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              41      0.96%     94.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              93      2.19%     96.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              12      0.28%     96.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               8      0.19%     96.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              11      0.26%     96.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               4      0.09%     97.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.14%     97.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               2      0.05%     97.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             101      2.37%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               2      0.05%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               3      0.07%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               1      0.02%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.02%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             6      0.14%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4254                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1082395298                       # Total ticks spent queuing
system.physmem.totMemAccLat                2869457798                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    476550000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11356.58                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30106.58                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.19                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.01                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.19                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.01                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         9.18                       # Average write queue length when enqueuing
system.physmem.readRowHits                      76601                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     58731                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.37                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  72.10                       # Row buffer hit rate for writes
system.physmem.avgGap                     29060364.94                       # Average gap between requests
system.physmem.pageHitRate                      76.56                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  152477640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   82953750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 356538000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                270228960                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           250406807040                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            95253378300                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2241273732750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             2587796116440                       # Total energy per rank (pJ)
system.physmem_0.averagePower              667.867379                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   3687953773966                       # Time in different power states
system.physmem_0.memoryStateTime::REF    128019840000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     18290517534                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  160786080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   87503625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 386872200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                257631840                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           250406807040                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            95644179990                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2237947569750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             2584891350525                       # Total energy per rank (pJ)
system.physmem_1.averagePower              667.974891                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   3687410747240                       # Time in different power states
system.physmem_1.memoryStateTime::REF    128019840000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     18840857760                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
system.cpu0.numCycles                       818622179                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   70465386                       # Number of instructions committed
system.cpu0.committedOps                    143948929                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            131896754                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                     904463                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     13997547                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   131896754                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads          241558700                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         113520418                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            82096977                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           54912679                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     13231012                       # number of memory refs
system.cpu0.num_load_insts                    9870869                       # Number of load instructions
system.cpu0.num_store_insts                   3360143                       # Number of store instructions
system.cpu0.num_idle_cycles              776995348.800534                       # Number of idle cycles
system.cpu0.num_busy_cycles              41626830.199466                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.050850                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.949150                       # Percentage of idle cycles
system.cpu0.Branches                         15238298                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                84207      0.06%      0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu                130532761     90.68%     90.74% # Class of executed instruction
system.cpu0.op_class::IntMult                   57038      0.04%     90.78% # Class of executed instruction
system.cpu0.op_class::IntDiv                    45915      0.03%     90.81% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.81% # Class of executed instruction
system.cpu0.op_class::MemRead                 9869228      6.86%     97.67% # Class of executed instruction
system.cpu0.op_class::MemWrite                3360143      2.33%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 143949292                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          1638295                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999362                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           19673231                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1638807                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            12.004605                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   232.517984                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   254.861534                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data    24.619844                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.454137                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.497776                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.048086                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88575778                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88575778                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      4693238                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      2575592                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4254114                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11522944                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3236162                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1812970                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      3039112                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       8088244                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        19748                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10138                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        30323                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        60209                       # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data      7929400                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      4388562                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      7293226                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        19611188                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      7949148                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      4398700                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      7323549                       # number of overall hits
system.cpu0.dcache.overall_hits::total       19671397                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       340869                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       165985                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       824524                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1331378                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       120523                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        67710                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       137190                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       325423                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       143877                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        63954                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       198209                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       406040                       # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data       461392                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       233695                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       961714                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1656801                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       605269                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       297649                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1159923                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2062841                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2308605500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  12073568500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  14382174000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2733996493                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   4762186878                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   7496183371                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   5042601993                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  16835755378                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  21878357371                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   5042601993                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  16835755378                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  21878357371                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5034107                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      2741577                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      5078638                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     12854322                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3356685                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1880680                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      3176302                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      8413667                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       163625                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        74092                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       228532                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       466249                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8390792                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      4622257                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      8254940                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     21267989                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      8554417                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      4696349                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      8483472                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     21734238                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.067712                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.060544                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.162351                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.103574                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.035905                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.036003                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.043192                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.038678                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.879309                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.863170                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.867314                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.870865                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.054988                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.050559                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.116502                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.077901                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.070755                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.063379                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.136727                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.094912                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13908.518842                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14643.077097                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10802.472326                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40378.031207                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34712.346949                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23035.198406                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21577.705954                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17505.989700                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13205.181172                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16941.437710                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14514.545688                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 10605.934908                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       198021                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            23048                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     8.591678                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      1547778                       # number of writebacks
system.cpu0.dcache.writebacks::total          1547778                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           51                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       385318                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       385369                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1567                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        32007                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        33574                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         1618                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       417325                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       418943                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         1618                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       417325                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       418943                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       165934                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       439206                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       605140                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        66143                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       105183                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       171326                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        63954                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       194797                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       258751                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       232077                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       544389                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       776466                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       296031                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       739186                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1035217                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       186036                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       204987                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total       391023                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3332                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4183                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total         7515                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       189368                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       209170                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total       398538                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2142200000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5924742500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8066942500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2581607993                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   4076188379                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6657796372                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    949074500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2819608000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3768682500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4723807993                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  10000930879                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  14724738872                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5672882493                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  12820538879                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  18493421372                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30610037000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33210281500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63820318500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    591963000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    837812500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1429775500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31202000000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  34048094000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65250094000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.060525                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086481                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.047077                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.035170                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.033115                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.020363                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.863170                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.852384                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.554963                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.050209                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065947                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.036509                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.063034                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087132                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.047631                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12909.952150                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13489.666580                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13330.704465                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39030.706091                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38753.300239                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38860.396974                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14839.955280                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14474.596631                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14564.900232                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20354.485766                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18370.927552                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18963.790909                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19163.136607                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17344.131083                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17864.294512                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164538.245286                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 162011.647080                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163213.720165                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177659.963986                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200289.863734                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190256.220892                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164769.126780                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162777.138213                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163723.644922                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements           878678                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.838296                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          128369667                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           879190                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           146.009016                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle     149037485500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   260.884696                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   143.250304                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst   106.703296                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.509540                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.279786                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.208405                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997731                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          148                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          300                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        130155693                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       130155693                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     85680859                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     39485533                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3203275                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      128369667                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     85680859                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     39485533                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3203275                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       128369667                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     85680859                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     39485533                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3203275                       # number of overall hits
system.cpu0.icache.overall_hits::total      128369667                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       290083                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       179832                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       436910                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       906825                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       290083                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       179832                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       436910                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        906825                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       290083                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       179832                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       436910                       # number of overall misses
system.cpu0.icache.overall_misses::total       906825                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2559612500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6034776488                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   8594388988                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2559612500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   6034776488                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   8594388988                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2559612500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   6034776488                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   8594388988                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     85970942                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     39665365                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      3640185                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    129276492                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     85970942                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     39665365                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      3640185                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    129276492                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     85970942                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     39665365                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      3640185                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    129276492                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003374                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004534                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.120024                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.007015                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003374                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004534                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.120024                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.007015                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003374                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004534                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.120024                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.007015                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.353908                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.401840                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9477.450432                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14233.353908                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.401840                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9477.450432                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14233.353908                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.401840                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9477.450432                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         5682                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              315                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.038095                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        27624                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        27624                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        27624                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        27624                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        27624                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        27624                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       179832                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       409286                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       589118                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       179832                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       409286                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       589118                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       179832                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       409286                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       589118                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2379780500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5367725488                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   7747505988                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2379780500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5367725488                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   7747505988                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2379780500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5367725488                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   7747505988                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004534                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.112435                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004557                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004534                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.112435                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.004557                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004534                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.112435                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.004557                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13233.353908                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13114.852421                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13151.025750                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13233.353908                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13114.852421                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13151.025750                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13233.353908                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13114.852421                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13151.025750                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                      2607160707                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   35907928                       # Number of instructions committed
system.cpu1.committedOps                     69695660                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             64757843                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     501298                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      6590213                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    64757843                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads          119979371                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          55719008                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            36729292                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           27266794                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      4880817                       # number of memory refs
system.cpu1.num_load_insts                    2999293                       # Number of load instructions
system.cpu1.num_store_insts                   1881524                       # Number of store instructions
system.cpu1.num_idle_cycles              2477690884.667310                       # Number of idle cycles
system.cpu1.num_busy_cycles              129469822.332690                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.049659                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.950341                       # Percentage of idle cycles
system.cpu1.Branches                          7272679                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                37847      0.05%      0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu                 64724112     92.87%     92.92% # Class of executed instruction
system.cpu1.op_class::IntMult                   30276      0.04%     92.96% # Class of executed instruction
system.cpu1.op_class::IntDiv                    24690      0.04%     93.00% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.00% # Class of executed instruction
system.cpu1.op_class::MemRead                 2997578      4.30%     97.30% # Class of executed instruction
system.cpu1.op_class::MemWrite                1881524      2.70%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  69696027                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups               29601975                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         29601975                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           343203                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            26791839                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               26086008                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            97.365500                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 612616                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             69103                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                       155854675                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles          11239571                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                     145909604                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   29601975                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          26698624                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                    143043306                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 717621                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                    104333                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles                8734                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             9529                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        59780                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles           15                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          573                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  3640195                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               178300                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   3755                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples         154824000                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.854554                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            3.033337                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                98922679     63.89%     63.89% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  904691      0.58%     64.48% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                23796776     15.37%     79.85% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  606779      0.39%     80.24% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  848220      0.55%     80.79% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  866864      0.56%     81.35% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  584872      0.38%     81.73% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  770506      0.50%     82.22% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                27522613     17.78%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total           154824000                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.189933                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.936190                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                10345116                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             94152744                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 23674011                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles              5064791                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                359462                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts             284127557                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                359462                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                12498058                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               76923253                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       4647068                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 26307426                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles             12860925                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts             282811274                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents               202798                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents               5895071                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                 49763                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               4758021                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands          337796411                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            617680830                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       379222273                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups              178                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps            324911571                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                12884840                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            166150                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        167782                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                 24657180                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6871363                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3845087                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           401055                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          322271                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                 280748482                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             429304                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                278478009                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued           108269                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        9486121                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     14384380                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved         66849                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples    154824000                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.798675                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       2.397594                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           91620665     59.18%     59.18% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            5352321      3.46%     62.63% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            3836914      2.48%     65.11% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            3858930      2.49%     67.61% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4           22596079     14.59%     82.20% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5            2789392      1.80%     84.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6           24067258     15.54%     99.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             479282      0.31%     99.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8             223159      0.14%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total      154824000                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                1768977     86.18%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                219653     10.70%     96.88% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                63974      3.12%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            83002      0.03%      0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu            267565718     96.08%     96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               58655      0.02%     96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                54123      0.02%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                 92      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             7168633      2.57%     98.73% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3547786      1.27%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total             278478009                       # Type of FU issued
system.cpu2.iq.rate                          1.786780                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    2052604                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.007371                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         713940635                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes        290668152                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses    276821518                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                256                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes               236                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses          114                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses             280447483                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                    128                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          731517                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1286395                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         6167                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         5109                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       663777                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads       750358                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        29268                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                359462                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles               70735172                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles              3134720                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts          281177786                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            44449                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6871363                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3845087                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            251829                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                166997                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents              2638315                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          5109                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        196795                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       202269                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              399064                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts            277848009                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              7014778                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           573017                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
system.cpu2.iew.exec_refs                    10469775                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                28224309                       # Number of branches executed
system.cpu2.iew.exec_stores                   3454997                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.782738                       # Inst execution rate
system.cpu2.iew.wb_sent                     277647788                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                    276821632                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                215782455                       # num instructions producing a value
system.cpu2.iew.wb_consumers                353891684                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.776152                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.609742                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        9482299                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         362455                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           346445                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples    153408377                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.771035                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.652208                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     95336138     62.15%     62.15% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4415580      2.88%     65.02% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1307869      0.85%     65.88% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3     24753928     16.14%     82.01% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       995070      0.65%     82.66% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       727248      0.47%     83.13% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       439603      0.29%     83.42% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7     23319103     15.20%     98.62% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      2113838      1.38%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total    153408377                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts           137757751                       # Number of instructions committed
system.cpu2.commit.committedOps             271691665                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8766278                       # Number of memory references committed
system.cpu2.commit.loads                      5584968                       # Number of loads committed
system.cpu2.commit.membars                     161958                       # Number of memory barriers committed
system.cpu2.commit.branches                  27804222                       # Number of branches committed
system.cpu2.commit.fp_insts                        48                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                248326046                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              453891                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        49969      0.02%      0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu       262767573     96.72%     96.73% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          56460      0.02%     96.75% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv           51419      0.02%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        5584918      2.06%     98.83% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       3181310      1.17%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total        271691665                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              2113838                       # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads                   432438077                       # The number of ROB reads
system.cpu2.rob.rob_writes                  563770770                       # The number of ROB writes
system.cpu2.timesIdled                         121162                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                        1030675                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  4911308393                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                  137757751                       # Number of Instructions Simulated
system.cpu2.committedOps                    271691665                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.131368                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.131368                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.883886                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.883886                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               370162227                       # number of integer regfile reads
system.cpu2.int_regfile_writes              221868711                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    73082                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                141178662                       # number of cc regfile reads
system.cpu2.cc_regfile_writes               108439379                       # number of cc regfile writes
system.cpu2.misc_regfile_reads               90543264                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                143975                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq              3552152                       # Transaction distribution
system.iobus.trans_dist::ReadResp             3552152                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57748                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57748                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1661                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1661                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7080216                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1182                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27854                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      7124542                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3322                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3322                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                 7223122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3540108                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2364                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13927                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total      3568515                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6644                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6644                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  6602975                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              2788160                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                28000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              5737000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 1000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            140109000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy              441000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy               86000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            11321000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                4000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           105499646                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1032000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           300163000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            23378000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1173000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47574                       # number of replacements
system.iocache.tags.tagsinuse                0.102984                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47590                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5000591236509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.102984                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006437                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.006437                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428661                       # Number of tag accesses
system.iocache.tags.data_accesses              428661                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide          909                       # number of demand (read+write) misses
system.iocache.demand_misses::total               909                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          909                       # number of overall misses
system.iocache.overall_misses::total              909                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    126015772                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    126015772                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   2387409874                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   2387409874                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    126015772                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    126015772                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    126015772                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    126015772                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          909                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             909                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          909                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            909                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138631.212321                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 138631.212321                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 51100.382577                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 51100.382577                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138631.212321                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 138631.212321                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138631.212321                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 138631.212321                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           218                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   18                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.111111                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          757                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          757                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        20232                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        20232                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          757                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          757                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          757                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          757                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     88165772                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     88165772                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1375809874                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   1375809874                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     88165772                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     88165772                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     88165772                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     88165772                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.832783                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.832783                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.433048                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.433048                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.832783                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.832783                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.832783                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.832783                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 116467.334214                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68001.674278                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68001.674278                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 116467.334214                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 116467.334214                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   105183                       # number of replacements
system.l2c.tags.tagsinuse                64828.721241                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4684113                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169423                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    27.647445                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   50898.132317                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.126487                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1607.202570                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     5199.796885                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      251.414397                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1573.306131                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker     6.399418                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker     0.004770                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1229.783271                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     4062.554995                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.776644                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.024524                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.079343                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.003836                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.024007                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000098                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.018765                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.061990                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.989208                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        64240                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          115                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3044                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6984                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54074                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.980225                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 41790314                       # Number of tag accesses
system.l2c.tags.data_accesses                41790314                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        18694                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker        10376                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        14927                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         8452                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        63394                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        13067                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 128910                       # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
system.l2c.Writeback_hits::writebacks         1547778                       # number of Writeback hits
system.l2c.Writeback_hits::total              1547778                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              86                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              61                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data             104                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 251                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            57261                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            38255                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            63793                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               159309                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        284171                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        176684                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst        403286                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total            864141                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       469690                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       225324                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data       620313                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          1315327                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         18694                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker         10378                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              284171                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              526951                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         14927                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          8452                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              176684                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              263579                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         63394                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         13067                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              403286                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              684106                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2467689                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        18694                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker        10378                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             284171                       # number of overall hits
system.l2c.overall_hits::cpu0.data             526951                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        14927                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         8452                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             176684                       # number of overall hits
system.l2c.overall_hits::cpu1.data             263579                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        63394                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        13067                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             403286                       # number of overall hits
system.l2c.overall_hits::cpu2.data             684106                       # number of overall hits
system.l2c.overall_hits::total                2467689                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           37                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                   43                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data           482                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           340                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           597                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1419                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          62694                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          27499                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          40743                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             130936                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         5899                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         3148                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst         5990                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           15037                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data        15056                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         4564                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data        13637                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          33257                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              5899                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             77750                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3148                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             32063                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           37                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              5990                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             54380                       # number of demand (read+write) misses
system.l2c.demand_misses::total                179273                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             5899                       # number of overall misses
system.l2c.overall_misses::cpu0.data            77750                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3148                       # number of overall misses
system.l2c.overall_misses::cpu1.data            32063                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           37                       # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             5990                       # number of overall misses
system.l2c.overall_misses::cpu2.data            54380                       # number of overall misses
system.l2c.overall_misses::total               179273                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      3871500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker        83000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total        3954500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      6342500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data      7566000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     13908500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   2068321500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   3225795000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   5294116500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    254232000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst    507297500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total    761529500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    380479000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data   1184085000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1564564000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    254232000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2448800500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      3871500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker        83000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    507297500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   4409880000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      7624164500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    254232000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2448800500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      3871500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker        83000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    507297500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   4409880000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     7624164500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        18694                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        10381                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        14927                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         8452                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        63431                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        13068                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             128953                       # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1547778                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1547778                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data          568                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          401                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          701                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1670                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       119955                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        65754                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data       104536                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           290245                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       290070                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       179832                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst       409276                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total        879178                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       484746                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       229888                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data       633950                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      1348584                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        18694                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        10383                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          290070                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          604701                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        14927                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         8452                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          179832                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          295642                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        63431                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        13068                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          409276                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          738486                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2646962                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        18694                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        10383                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         290070                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         604701                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        14927                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         8452                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         179832                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         295642                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        63431                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        13068                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         409276                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         738486                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2646962                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000482                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000583                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000077                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.000333                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.848592                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.847880                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.851641                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.849701                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.522646                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.418210                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.389751                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.451122                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.020336                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.017505                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.014636                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.017103                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.031060                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.019853                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.021511                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.024661                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000482                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.020336                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.128576                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.017505                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.108452                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000583                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker     0.000077                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.014636                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.073637                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.067728                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000482                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.020336                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.128576                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.017505                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.108452                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000583                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker     0.000077                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.014636                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.073637                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.067728                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 104635.135135                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        83000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 91965.116279                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18654.411765                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12673.366834                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  9801.620860                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75214.425979                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79174.213975                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 40432.856510                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80759.847522                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84690.734558                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 50643.712177                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83365.249781                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 86828.847987                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 47044.652254                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80759.847522                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 76374.653027                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 104635.135135                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker        83000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 84690.734558                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 81093.784480                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 42528.236265                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80759.847522                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 76374.653027                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 104635.135135                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker        83000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 84690.734558                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 81093.784480                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 42528.236265                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               97055                       # number of writebacks
system.l2c.writebacks::total                    97055                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           37                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total              38                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks           56                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total           56                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          340                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          597                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          937                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        27499                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        40743                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         68242                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         3148                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5989                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total         9137                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         4564                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data        13637                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        18201                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3148                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        32063                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           37                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         5989                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        54380                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            95618                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3148                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        32063                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           37                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         5989                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        54380                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           95618                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data       186036                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data       204987                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total       391023                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3332                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4183                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total         7515                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data       189368                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data       209170                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       398538                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      3501500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker        73000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total      3574500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      7682000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     12454500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     20136500                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1793331500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2818365000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   4611696500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    222752000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    447335500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total    670087500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    334839000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1048084000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1382923000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    222752000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   2128170500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3501500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker        73000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    447335500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   3866449000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6668281500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    222752000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   2128170500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3501500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker        73000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    447335500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   3866449000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6668281500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28284583500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30647941500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  58932525000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    553645000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    789702500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1343347500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28838228500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31437644000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  60275872500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000583                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000077                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.000295                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.847880                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.851641                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.561078                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.418210                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.389751                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.235119                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.017505                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.014633                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010393                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.019853                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.021511                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.013496                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.017505                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.108452                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000583                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000077                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014633                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.073637                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.036124                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.017505                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.108452                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000583                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000077                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014633                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.073637                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.036124                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        73000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 94065.789474                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22594.117647                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20861.809045                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21490.394877                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65214.425979                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69174.213975                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 67578.565986                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70759.847522                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74692.853565                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73337.802342                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73365.249781                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 76855.906724                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75980.605461                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70759.847522                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66374.653027                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        73000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74692.853565                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71100.570063                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 69738.767805                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70759.847522                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66374.653027                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        73000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74692.853565                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71100.570063                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 69738.767805                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152038.226472                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149511.634884                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150713.704820                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166159.963986                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 188788.548888                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178755.489022                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152286.703667                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150297.098054                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 151242.472487                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq             5067102                       # Transaction distribution
system.membus.trans_dist::ReadResp            5116344                       # Transaction distribution
system.membus.trans_dist::WriteReq              13938                       # Transaction distribution
system.membus.trans_dist::WriteResp             13938                       # Transaction distribution
system.membus.trans_dist::Writeback            143722                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8694                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             1684                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1684                       # Transaction distribution
system.membus.trans_dist::ReadExReq            130671                       # Transaction distribution
system.membus.trans_dist::ReadExResp           130671                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         49245                       # Transaction distribution
system.membus.trans_dist::MessageReq             1661                       # Transaction distribution
system.membus.trans_dist::MessageResp            1661                       # Transaction distribution
system.membus.trans_dist::BadAddressError            3                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3322                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3322                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7124542                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3037538                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       466123                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            6                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total     10628209                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       142133                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       142133                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               10773664                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6644                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6644                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3568515                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6075073                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17638016                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     27281604                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3024768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3024768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                30313016                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              794                       # Total snoops (count)
system.membus.snoop_fanout::samples           5463823                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.000304                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.017433                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 5462162     99.97%     99.97% # Request fanout histogram
system.membus.snoop_fanout::2                    1661      0.03%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total             5463823                       # Request fanout histogram
system.membus.reqLayer0.occupancy           233077000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           304111500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             2346000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy           540335137                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                4500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1173000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1355053149                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           39163714                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq            5228129                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           7456138                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13940                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13940                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          1629241                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          974525                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1670                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1670                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           290245                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          290245                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq        879201                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      1349341                       # Transaction distribution
system.toL2Bus.trans_dist::MessageReq            1173                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError            3                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        20232                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2636643                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15081470                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        73733                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       221081                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              18012927                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     56268224                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213600772                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       270696                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       799584                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              270939276                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          164260                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         10415382                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.028580                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.166622                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               10117713     97.14%     97.14% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 297669      2.86%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           10415382                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         2866107499                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           340500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         884323704                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1946611318                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          27584988                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          99698688                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------