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|
---------- Begin Simulation Statistics ----------
sim_seconds 5.137889 # Number of seconds simulated
sim_ticks 5137889173500 # Number of ticks simulated
final_tick 5137889173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 239672 # Simulator instruction rate (inst/s)
host_op_rate 476391 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5046842796 # Simulator tick rate (ticks/s)
host_mem_usage 957396 # Number of bytes of host memory used
host_seconds 1018.04 # Real time elapsed on the host
sim_insts 243995320 # Number of instructions simulated
sim_ops 484985266 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2475904 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 403712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5648960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 122048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1730432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 1600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 439808 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2919040 # Number of bytes read from this memory
system.physmem.bytes_read::total 13741824 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 403712 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 122048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 439808 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 965568 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9081216 # Number of bytes written to this memory
system.physmem.bytes_written::total 9081216 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 38686 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 6308 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 88265 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1907 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 27038 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 25 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 6872 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 45610 # Number of read requests responded to by this memory
system.physmem.num_reads::total 214716 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 141894 # Number of write requests responded to by this memory
system.physmem.num_writes::total 141894 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 481891 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 78575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1099471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 23755 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 336798 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 311 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 85601 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 568140 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2674605 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 78575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 23755 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 85601 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 187931 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1767499 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1767499 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1767499 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 481891 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 78575 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1099471 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 23755 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 336798 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 311 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 85601 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 568140 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4442104 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 101962 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 77214 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 101962 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts 77214 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 6525568 # Total number of bytes read from memory
system.physmem.bytesWritten 4941696 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 6525568 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4941696 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 761 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 6643 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 6709 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 6361 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 6804 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 6400 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 6366 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 5890 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 6159 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 5804 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 6034 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 5639 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 6376 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 6508 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 6377 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 6998 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 6828 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 5378 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 5214 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 4748 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 5235 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 5043 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 4974 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 4413 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 4576 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 4071 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 4483 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 4133 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 4579 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 5113 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 4622 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 5461 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 5171 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry
system.physmem.totGap 5136889044500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 101962 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 77214 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 78859 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 9083 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3841 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1511 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1324 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1094 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 669 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 612 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 574 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 532 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 498 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 477 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 509 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 521 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 487 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 366 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 253 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 120 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2893 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 3009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 3347 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 3369 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 3369 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 3366 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 3364 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 3360 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 3356 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 3354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 3353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 3350 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 3350 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 3347 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 3346 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 3344 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3338 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 3336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 3333 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3333 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 3330 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 3330 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 562 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 376 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 32753 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 349.964889 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 152.240831 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1180.348858 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 14687 44.84% 44.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 5019 15.32% 60.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 3032 9.26% 69.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 2021 6.17% 75.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 1281 3.91% 79.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 1132 3.46% 82.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 832 2.54% 85.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 693 2.12% 87.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 503 1.54% 89.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 527 1.61% 90.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 287 0.88% 91.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 266 0.81% 92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 203 0.62% 93.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 195 0.60% 93.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 197 0.60% 94.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 238 0.73% 94.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 149 0.45% 95.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 112 0.34% 95.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 86 0.26% 96.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 79 0.24% 96.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 89 0.27% 96.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 70 0.21% 96.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 290 0.89% 97.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 98 0.30% 97.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 63 0.19% 98.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 48 0.15% 98.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 49 0.15% 98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 27 0.08% 98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 22 0.07% 98.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 16 0.05% 98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 16 0.05% 98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 11 0.03% 98.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 5 0.02% 98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179 13 0.04% 98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243 5 0.02% 98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 10 0.03% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371 7 0.02% 98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 5 0.02% 98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563 7 0.02% 98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 3 0.01% 98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 3 0.01% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755 3 0.01% 98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 3 0.01% 98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 5 0.02% 98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 2 0.01% 98.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 2 0.01% 98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267 3 0.01% 99.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331 4 0.01% 99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395 4 0.01% 99.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 7 0.02% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 1 0.00% 99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 4 0.01% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779 6 0.02% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907 5 0.02% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971 2 0.01% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035 1 0.00% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099 9 0.03% 99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227 2 0.01% 99.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419 3 0.01% 99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483 2 0.01% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547 2 0.01% 99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995 1 0.00% 99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059 2 0.01% 99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123 3 0.01% 99.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187 1 0.00% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507 2 0.01% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019 2 0.01% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275 1 0.00% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531 3 0.01% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723 5 0.02% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851 2 0.01% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979 3 0.01% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171 1 0.00% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939 3 0.01% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 48 0.15% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219 2 0.01% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9603 2 0.01% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915 13 0.04% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15107 7 0.02% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171 2 0.01% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491 3 0.01% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555 3 0.01% 99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15683 3 0.01% 99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15811 2 0.01% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16131 3 0.01% 99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195 9 0.03% 99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16259 10 0.03% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16323 15 0.05% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 34 0.10% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16451 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17667 2 0.01% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 32753 # Bytes accessed per row activation
system.physmem.totQLat 1954361749 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 3940385499 # Sum of mem lat for all requests
system.physmem.totBusLat 509480000 # Total cycles spent in databus access
system.physmem.totBankLat 1476543750 # Total cycles spent in bank access
system.physmem.avgQLat 19179.97 # Average queueing delay per request
system.physmem.avgBankLat 14490.69 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 38670.66 # Average memory access latency
system.physmem.avgRdBW 1.27 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.96 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1.27 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.96 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.12 # Average write queue length over time
system.physmem.readRowHits 89443 # Number of row buffer hits during reads
system.physmem.writeRowHits 56909 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.78 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes
system.physmem.avgGap 28669515.14 # Average gap between requests
system.membus.throughput 6421183 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 424471 # Transaction distribution
system.membus.trans_dist::ReadResp 424470 # Transaction distribution
system.membus.trans_dist::WriteReq 6959 # Transaction distribution
system.membus.trans_dist::WriteResp 6959 # Transaction distribution
system.membus.trans_dist::Writeback 77214 # Transaction distribution
system.membus.trans_dist::UpgradeReq 768 # Transaction distribution
system.membus.trans_dist::UpgradeResp 768 # Transaction distribution
system.membus.trans_dist::ReadExReq 79729 # Transaction distribution
system.membus.trans_dist::ReadExResp 79729 # Transaction distribution
system.membus.trans_dist::MessageReq 903 # Transaction distribution
system.membus.trans_dist::MessageResp 903 # Transaction distribution
system.membus.trans_dist::BadAddressError 1 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1806 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 1806 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312334 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497960 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 218608 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 1028904 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 68108 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 68108 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1098818 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3612 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total 3612 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160445 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995917 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8655808 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 9812170 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2811456 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 2811456 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 12627238 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 32732190 # Total data (bytes)
system.membus.snoop_data_through_bus 259136 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 164966500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 315386000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1806000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer3.occupancy 820026249 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 903000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1636763940 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer4.occupancy 218001500 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.l2c.tags.replacements 103793 # number of replacements
system.l2c.tags.tagsinuse 64823.461690 # Cycle average of tags in use
system.l2c.tags.total_refs 3658744 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 167885 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 21.793156 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 51284.674060 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121869 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 1299.911935 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 4544.856644 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 221.437918 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1509.586927 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.216404 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003202 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1337.967786 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 4616.684944 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.782542 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.019835 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.069349 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.003379 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.023034 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000125 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.020416 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.070445 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.989128 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 22091 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 11658 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 334413 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 510225 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 10171 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 5452 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 152259 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 227659 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 50814 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 10913 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 351942 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 566551 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2254148 # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
system.l2c.Writeback_hits::writebacks 1543420 # number of Writeback hits
system.l2c.Writeback_hits::total 1543420 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 115 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 83 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 254 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 69377 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 36565 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 61899 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 167841 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 22091 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 11660 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 334413 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 579602 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 10171 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 5452 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 152259 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 264224 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 50814 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 10913 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 351942 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 628450 # number of demand (read+write) hits
system.l2c.demand_hits::total 2421991 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 22091 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 11660 # number of overall hits
system.l2c.overall_hits::cpu0.inst 334413 # number of overall hits
system.l2c.overall_hits::cpu0.data 579602 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 10171 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 5452 # number of overall hits
system.l2c.overall_hits::cpu1.inst 152259 # number of overall hits
system.l2c.overall_hits::cpu1.data 264224 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 50814 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 10913 # number of overall hits
system.l2c.overall_hits::cpu2.inst 351942 # number of overall hits
system.l2c.overall_hits::cpu2.data 628450 # number of overall hits
system.l2c.overall_hits::total 2421991 # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 6308 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 16059 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 1908 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 3914 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 25 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 6873 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 12824 # number of ReadReq misses
system.l2c.ReadReq_misses::total 47916 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 775 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 221 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 356 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1352 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 72577 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 23336 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 33144 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 129057 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 6308 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 88636 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 1908 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 27250 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 25 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 6873 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 45968 # number of demand (read+write) misses
system.l2c.demand_misses::total 176973 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
system.l2c.overall_misses::cpu0.inst 6308 # number of overall misses
system.l2c.overall_misses::cpu0.data 88636 # number of overall misses
system.l2c.overall_misses::cpu1.inst 1908 # number of overall misses
system.l2c.overall_misses::cpu1.data 27250 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 25 # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu2.inst 6873 # number of overall misses
system.l2c.overall_misses::cpu2.data 45968 # number of overall misses
system.l2c.overall_misses::total 176973 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst 145483750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 305732245 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2908500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker 88750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 619386243 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 1056307494 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2129906982 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 2658895 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 4530318 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 7189213 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1598265396 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 2458778359 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 4057043755 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 145483750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1903997641 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 2908500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker 88750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 619386243 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 3515085853 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 6186950737 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 145483750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1903997641 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 2908500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker 88750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 619386243 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 3515085853 # number of overall miss cycles
system.l2c.overall_miss_latency::total 6186950737 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 22091 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 11662 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 340721 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 526284 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 10171 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 5452 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 154167 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 231573 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 50839 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 10914 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 358815 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 579375 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2302064 # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1543420 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1543420 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 890 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 277 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 439 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1606 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 141954 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 59901 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 95043 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 296898 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 22091 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 11664 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 340721 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 668238 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 10171 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 5452 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 154167 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 291474 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker 50839 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker 10914 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 358815 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 674418 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2598964 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 22091 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 11664 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 340721 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 668238 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 10171 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 5452 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 154167 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 291474 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker 50839 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker 10914 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 358815 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 674418 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2598964 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000343 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.018514 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.030514 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.012376 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.016902 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000092 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.019155 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.022134 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.020814 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.870787 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.797834 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.810934 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.841843 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.511271 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.389576 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.348726 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.434685 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000343 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.018514 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.132641 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.012376 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.093490 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker 0.000092 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.019155 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.068160 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.068094 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000343 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.018514 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.132641 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.012376 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.093490 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker 0.000092 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.019155 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.068160 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.068094 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76249.344864 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 78112.479561 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 116340 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88750 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 90118.760803 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 82369.580006 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 44450.851114 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12031.199095 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12725.612360 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 5317.465237 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68489.261056 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74184.719979 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 31436.061237 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 76249.344864 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 69871.473064 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 116340 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 90118.760803 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 76468.105051 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 34959.856797 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 76249.344864 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 69871.473064 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 116340 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 90118.760803 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 76468.105051 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 34959.856797 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 95227 # number of writebacks
system.l2c.writebacks::total 95227 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.inst 1908 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 3914 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 25 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 6872 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 12824 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 25544 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 221 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 356 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 577 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 23336 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 33144 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 56480 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 1908 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 27250 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 25 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 6872 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 45968 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 82024 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 1908 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 27250 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 25 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 6872 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 45968 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 82024 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 121373750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 256053755 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 76250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 532537507 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 893917000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1806552262 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2360218 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3787353 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 6147571 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1304557104 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2042074099 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 3346631203 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 121373750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1560610859 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 76250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 532537507 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 2935991099 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 5153183465 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 121373750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1560610859 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 76250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 532537507 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 2935991099 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 5153183465 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28189792500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30481780500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 58671573000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 471155500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 768000500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1239156000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28660948000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31249781000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 59910729000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.022134 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.011096 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.797834 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.810934 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.359278 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.389576 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.348726 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.190234 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.093490 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.068160 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.031560 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.093490 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.068160 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.031560 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65419.968063 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 69706.565814 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 70723.154635 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10679.719457 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10638.632022 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10654.369151 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55903.201234 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61612.180153 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 59253.385322 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57270.123266 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63870.324987 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 62825.312896 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57270.123266 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63870.324987 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 62825.312896 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 47570 # number of replacements
system.iocache.tags.tagsinuse 0.094174 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 47586 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 5000166705009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094174 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005886 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.005886 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses
system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses
system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses
system.iocache.overall_misses::total 47625 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131928771 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 131928771 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5225930177 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 5225930177 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 5357858948 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 5357858948 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 5357858948 # number of overall miss cycles
system.iocache.overall_miss_latency::total 5357858948 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145777.647514 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 145777.647514 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 111856.382213 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 111856.382213 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 112500.975286 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 112500.975286 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 112500.975286 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 112500.975286 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 75733 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 7002 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.815910 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 739 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 23440 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 23440 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 24179 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 24179 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 24179 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 24179 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93470771 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 93470771 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4006299177 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 4006299177 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4099769948 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 4099769948 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4099769948 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 4099769948 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816575 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.816575 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.501712 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 0.501712 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.507696 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.507696 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.507696 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.507696 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126482.775372 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 126482.775372 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 170917.200384 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 170917.200384 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 169559.119401 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 169559.119401 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 169559.119401 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 169559.119401 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.toL2Bus.throughput 52280174 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 1811511 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 1810976 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 6959 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 6959 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 914733 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 716 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 716 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 178384 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 154949 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1025990 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3658453 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 36523 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 129481 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 4850447 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32830848 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 121529738 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 130928 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 488080 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 154979594 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 268493674 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 116064 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 5106548110 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 2311338505 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4765806692 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 20170721 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 68576287 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 1274820 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 150850 # Transaction distribution
system.iobus.trans_dist::ReadResp 150850 # Transaction distribution
system.iobus.trans_dist::WriteReq 29496 # Transaction distribution
system.iobus.trans_dist::WriteResp 29496 # Transaction distribution
system.iobus.trans_dist::MessageReq 903 # Transaction distribution
system.iobus.trans_dist::MessageResp 903 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5804 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 46 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287488 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 552 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15072 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 312334 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 48358 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 48358 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1806 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1806 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 362498 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3277 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 23 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143744 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1104 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 160445 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1536536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1536536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3612 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3612 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 1700593 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 6549885 # Total data (bytes)
system.iobus.reqLayer0.occupancy 2124548 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 4801000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 39000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 143745000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 436000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 11266000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 213288448 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 306278000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 29307500 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer2.occupancy 903000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.numCycles 1216464910 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 71961421 # Number of instructions committed
system.cpu0.committedOps 146368954 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 134434152 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 983451 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 14191112 # number of instructions that are conditional controls
system.cpu0.num_int_insts 134434152 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 247103574 # number of times the integer registers were read
system.cpu0.num_int_register_writes 115380288 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 83614520 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 55784493 # number of times the CC registers were written
system.cpu0.num_mem_refs 14023782 # number of memory refs
system.cpu0.num_load_insts 10248970 # Number of load instructions
system.cpu0.num_store_insts 3774812 # Number of store instructions
system.cpu0.num_idle_cycles 1155422884.085227 # Number of idle cycles
system.cpu0.num_busy_cycles 61042025.914772 # Number of busy cycles
system.cpu0.not_idle_fraction 0.050180 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.949820 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 853207 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.801369 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 129244758 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 853719 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 151.390279 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 147441059000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 310.509377 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 127.091120 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 73.200872 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.606464 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.248225 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.142970 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997659 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 87593978 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 38906796 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2743984 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 129244758 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 87593978 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 38906796 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2743984 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 129244758 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 87593978 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 38906796 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2743984 # number of overall hits
system.cpu0.icache.overall_hits::total 129244758 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 340722 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 154167 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 378624 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 873513 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 340722 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 154167 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 378624 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 873513 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 340722 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 154167 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 378624 # number of overall misses
system.cpu0.icache.overall_misses::total 873513 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2138351750 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5548047899 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 7686399649 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 2138351750 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 5548047899 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 7686399649 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 2138351750 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 5548047899 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 7686399649 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 87934700 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 39060963 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3122608 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 130118271 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 87934700 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 39060963 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 3122608 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 130118271 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 87934700 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 39060963 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 3122608 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 130118271 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003875 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003947 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121252 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.006713 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003875 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003947 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121252 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.006713 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003875 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003947 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121252 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.006713 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13870.359740 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14653.186008 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8799.410712 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13870.359740 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14653.186008 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8799.410712 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13870.359740 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14653.186008 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8799.410712 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 6480 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.887967 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 19783 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 19783 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 19783 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 19783 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 19783 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 19783 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 154167 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 358841 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 513008 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 154167 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 358841 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 513008 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 154167 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 358841 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 513008 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1829084250 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4581098483 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 6410182733 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1829084250 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4581098483 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 6410182733 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1829084250 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4581098483 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 6410182733 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003943 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.003943 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.003943 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12495.288052 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12495.288052 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12495.288052 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 1633606 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999469 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 19601664 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1634118 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 11.995256 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 202.875385 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 302.501214 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.622869 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.396241 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.590823 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012935 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 5120812 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 2495791 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 3903609 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 11520212 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3628684 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 1642970 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 2808111 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 8079765 # number of WriteReq hits
system.cpu0.dcache.demand_hits::cpu0.data 8749496 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 4138761 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 6711720 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 19599977 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 8749496 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 4138761 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 6711720 # number of overall hits
system.cpu0.dcache.overall_hits::total 19599977 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 526284 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 231573 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 944815 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1702672 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 142844 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 60178 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 112298 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 315320 # number of WriteReq misses
system.cpu0.dcache.demand_misses::cpu0.data 669128 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 291751 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1057113 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2017992 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 669128 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 291751 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1057113 # number of overall misses
system.cpu0.dcache.overall_misses::total 2017992 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3286416755 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15267347781 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 18553764536 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2165300822 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3604529651 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 5769830473 # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 5451717577 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 18871877432 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 24323595009 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 5451717577 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 18871877432 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 24323595009 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5647096 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 2727364 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4848424 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13222884 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3771528 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1703148 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2920409 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 8395085 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 9418624 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 4430512 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7768833 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 21617969 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 9418624 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 4430512 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 7768833 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 21617969 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093196 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.084907 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.194871 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.128767 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037874 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035333 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.038453 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.037560 # miss rate for WriteReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071043 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065850 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.136071 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.093348 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071043 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065850 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.136071 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.093348 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14191.709547 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16159.086997 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10896.851852 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35981.601615 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32097.897122 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 18298.333353 # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18686.200140 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17852.280155 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 12053.365429 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18686.200140 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17852.280155 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12053.365429 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 177204 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 11696 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.150821 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1543420 # number of writebacks
system.cpu0.dcache.writebacks::total 1543420 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 365400 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 365400 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 16856 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 16856 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 382256 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 382256 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 382256 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 382256 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 231573 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 579415 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 810988 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60178 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95442 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 155620 # number of WriteReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 291751 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 674857 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 966608 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 291751 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 674857 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 966608 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2821426245 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8425862038 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11247288283 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2033592178 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3216384846 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5249977024 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4855018423 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11642246884 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 16497265307 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4855018423 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11642246884 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 16497265307 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30662990000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33250431500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63913421500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 506056500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 816755500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1322812000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31169046500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34067187000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65236233500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.084907 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.119506 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061332 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035333 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032681 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018537 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065850 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086867 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.044713 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065850 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086867 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.044713 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12183.744413 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14542.015719 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13868.624792 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33792.950547 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33699.889420 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33735.876006 # average WriteReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16640.965834 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17251.427908 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17067.172325 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16640.965834 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17251.427908 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17067.172325 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 2606006645 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 35315213 # Number of instructions committed
system.cpu1.committedOps 68682433 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 63797816 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 457734 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 6497995 # number of instructions that are conditional controls
system.cpu1.num_int_insts 63797816 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 117816925 # number of times the integer registers were read
system.cpu1.num_int_register_writes 55078781 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 36195960 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 26980721 # number of times the CC registers were written
system.cpu1.num_mem_refs 4621452 # number of memory refs
system.cpu1.num_load_insts 2916499 # Number of load instructions
system.cpu1.num_store_insts 1704953 # Number of store instructions
system.cpu1.num_idle_cycles 2477007170.096548 # Number of idle cycles
system.cpu1.num_busy_cycles 128999474.903452 # Number of busy cycles
system.cpu1.not_idle_fraction 0.049501 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.950499 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 28832932 # Number of BP lookups
system.cpu2.branchPred.condPredicted 28832932 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 311283 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 26470595 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 25835663 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 97.601369 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 539109 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 63758 # Number of incorrect RAS predictions.
system.cpu2.numCycles 156318365 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 9648571 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 142153316 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 28832932 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 26374772 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 54477061 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 1438031 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 74339 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.BlockedCycles 25017392 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 3513 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 6379 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 22688 # Number of stall cycles due to pending traps
system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 3122610 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 142940 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 2082 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 90361689 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 3.101501 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 3.407201 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 36017869 39.86% 39.86% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 584325 0.65% 40.51% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 23803917 26.34% 66.85% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 312236 0.35% 67.19% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 599559 0.66% 67.86% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 810629 0.90% 68.76% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 333254 0.37% 69.12% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 522143 0.58% 69.70% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 27377757 30.30% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 90361689 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.184450 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.909383 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 11120847 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 23921754 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 35744474 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 1291324 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 1114642 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 279457828 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 12 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 1114642 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 12111653 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 14421944 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 4371925 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 35874443 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 5298501 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 278479903 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 7178 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 2457632 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 2167618 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands 332694530 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 605890178 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 372281709 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 54 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 322791874 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 9902651 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 146965 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 147763 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 11459312 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 6166984 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3428654 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 344111 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 288647 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 276817235 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 412713 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 275284943 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 59120 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 6994425 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 10714687 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 55194 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 90361689 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 3.046479 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 2.402703 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 26846835 29.71% 29.71% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 6154250 6.81% 36.52% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 3929000 4.35% 40.87% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 2711977 3.00% 43.87% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 25114660 27.79% 71.66% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 1340428 1.48% 73.15% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 23928680 26.48% 99.63% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 282970 0.31% 99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 52889 0.06% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 90361689 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 125502 33.84% 33.84% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 241 0.06% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 190694 51.42% 85.33% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 54418 14.67% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 78208 0.03% 0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 265424287 96.42% 96.45% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 56044 0.02% 96.47% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 46278 0.02% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 6463688 2.35% 98.83% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3216438 1.17% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 275284943 # Type of FU issued
system.cpu2.iq.rate 1.761053 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 370855 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.001347 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 641401400 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 284227989 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 273934511 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 90 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 102 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 275577549 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 41 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 638960 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 974310 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 6664 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 4257 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 503319 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 656257 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 10390 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 1114642 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 9684851 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 815798 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 277229948 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 71784 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 6166984 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3428654 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 232570 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 630862 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 4638 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 4257 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 175308 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 177843 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 353151 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 274790127 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 6353973 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 494815 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
system.cpu2.iew.exec_refs 9504896 # number of memory reference insts executed
system.cpu2.iew.exec_branches 27944071 # Number of branches executed
system.cpu2.iew.exec_stores 3150923 # Number of stores executed
system.cpu2.iew.exec_rate 1.757888 # Inst execution rate
system.cpu2.iew.wb_sent 274642284 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 273934533 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 213583516 # num instructions producing a value
system.cpu2.iew.wb_consumers 349233536 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.752414 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.611578 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 7294558 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 357518 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 313650 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 89247046 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 3.024569 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 2.872131 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 31615758 35.42% 35.42% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4405793 4.94% 40.36% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1230871 1.38% 41.74% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 24727866 27.71% 69.45% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 857199 0.96% 70.41% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 581394 0.65% 71.06% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 343629 0.39% 71.44% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 23391082 26.21% 97.65% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 2093454 2.35% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 89247046 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 136718686 # Number of instructions committed
system.cpu2.commit.committedOps 269933879 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 8118007 # Number of memory references committed
system.cpu2.commit.loads 5192672 # Number of loads committed
system.cpu2.commit.membars 165488 # Number of memory barriers committed
system.cpu2.commit.branches 27614013 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 246437097 # Number of committed integer instructions.
system.cpu2.commit.function_calls 432570 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 2093454 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 364355237 # The number of ROB reads
system.cpu2.rob.rob_writes 555575410 # The number of ROB writes
system.cpu2.timesIdled 476451 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 65956676 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 4907452688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 136718686 # Number of Instructions Simulated
system.cpu2.committedOps 269933879 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 136718686 # Number of Instructions Simulated
system.cpu2.cpi 1.143358 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.143358 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.874617 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.874617 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 365607519 # number of integer regfile reads
system.cpu2.int_regfile_writes 219416427 # number of integer regfile writes
system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads
system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes
system.cpu2.cc_regfile_reads 139623375 # number of cc regfile reads
system.cpu2.cc_regfile_writes 107543298 # number of cc regfile writes
system.cpu2.misc_regfile_reads 89002893 # number of misc regfile reads
system.cpu2.misc_regfile_writes 130765 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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