path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.133759                       # Number of seconds simulated
sim_ticks                                5133759356500                       # Number of ticks simulated
final_tick                               5133759356500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 270712                       # Simulator instruction rate (inst/s)
host_op_rate                                   538208                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5706161187                       # Simulator tick rate (ticks/s)
host_mem_usage                                 956212                       # Number of bytes of host memory used
host_seconds                                   899.69                       # Real time elapsed on the host
sim_insts                                   243556000                       # Number of instructions simulated
sim_ops                                     484219202                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           473664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5506752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           151296                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          1916928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         2560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           343744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          2959424                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11383040                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       473664                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       151296                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       343744                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          968704                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9167488                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9167488                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              7401                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             86043                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2364                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             29952                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           40                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              5371                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             46241                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                177860                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          143242                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143242                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               92265                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1072655                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               29471                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              373397                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           499                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               66958                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              576463                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5523                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2217291                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          92265                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          29471                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          66958                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             188693                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1785726                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1785726                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1785726                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              92265                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1072655                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              29471                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             373397                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          499                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              66958                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             576463                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5523                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4003017                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         84411                       # Number of read requests accepted
system.physmem.writeReqs                       105225                       # Number of write requests accepted
system.physmem.readBursts                       84411                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     105225                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  5391616                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10688                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6646720                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   5402304                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6734400                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      167                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    1370                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            877                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                5556                       # Per bank write bursts
system.physmem.perBankRdBursts::1                4342                       # Per bank write bursts
system.physmem.perBankRdBursts::2                4498                       # Per bank write bursts
system.physmem.perBankRdBursts::3                5943                       # Per bank write bursts
system.physmem.perBankRdBursts::4                5610                       # Per bank write bursts
system.physmem.perBankRdBursts::5                4878                       # Per bank write bursts
system.physmem.perBankRdBursts::6                4789                       # Per bank write bursts
system.physmem.perBankRdBursts::7                4605                       # Per bank write bursts
system.physmem.perBankRdBursts::8                5348                       # Per bank write bursts
system.physmem.perBankRdBursts::9                5424                       # Per bank write bursts
system.physmem.perBankRdBursts::10               4968                       # Per bank write bursts
system.physmem.perBankRdBursts::11               5291                       # Per bank write bursts
system.physmem.perBankRdBursts::12               5168                       # Per bank write bursts
system.physmem.perBankRdBursts::13               6289                       # Per bank write bursts
system.physmem.perBankRdBursts::14               5888                       # Per bank write bursts
system.physmem.perBankRdBursts::15               5647                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6974                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5943                       # Per bank write bursts
system.physmem.perBankWrBursts::2                5537                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6451                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6503                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5766                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6233                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6363                       # Per bank write bursts
system.physmem.perBankWrBursts::8                6662                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6738                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7192                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7225                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6202                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7261                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6520                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6285                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    5132576110500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   84411                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 105225                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     78589                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4433                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       775                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       139                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        37                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1625                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3056                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5196                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5931                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6760                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7506                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7265                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7577                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6913                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6618                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5783                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4284                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      225                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        39329                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      306.093112                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     177.896548                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     332.057147                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          15327     38.97%     38.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         9261     23.55%     62.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3835      9.75%     72.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2116      5.38%     77.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1579      4.01%     81.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          961      2.44%     84.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          670      1.70%     85.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          553      1.41%     87.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         5027     12.78%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          39329                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4061                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.744644                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      186.795472                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            4058     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5632-6143            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9728-10239            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4061                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4061                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        25.573750                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       20.065998                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       25.155630                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-7                71      1.75%      1.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-15                7      0.17%      1.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            3181     78.33%     80.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31             170      4.19%     84.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             129      3.18%     87.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              48      1.18%     88.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             114      2.81%     91.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              18      0.44%     92.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              31      0.76%     92.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              38      0.94%     93.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87              54      1.33%     95.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95              16      0.39%     95.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103             98      2.41%     97.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             9      0.22%     98.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119            19      0.47%     98.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             5      0.12%     98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135            15      0.37%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             3      0.07%     99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            11      0.27%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             4      0.10%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             4      0.10%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             2      0.05%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             3      0.07%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             4      0.10%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             2      0.05%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             1      0.02%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             2      0.05%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-279             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4061                       # Writes before turning the bus around for reads
system.physmem.totQLat                      954764500                       # Total ticks spent queuing
system.physmem.totMemAccLat                2534339500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    421220000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11333.32                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30083.32                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.05                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.29                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.05                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.31                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.74                       # Average write queue length when enqueuing
system.physmem.readRowHits                      67051                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     81719                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   79.59                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.69                       # Row buffer hit rate for writes
system.physmem.avgGap                     27065410.10                       # Average gap between requests
system.physmem.pageHitRate                      79.09                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     4938610465000                       # Time in different power states
system.physmem.memoryStateTime::REF      171427360000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       23717365000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 143949960                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 153377280                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                  78544125                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                  83688000                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                313723800                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                343379400                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               322509600                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               350470800                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          335311916160                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          335311916160                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          122830725285                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          123321765465                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          2972506855500                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          2972076118500                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            3431508224430                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            3431640715605                       # Total energy per rank (pJ)
system.physmem.averagePower::0             668.420699                       # Core power per rank (mW)
system.physmem.averagePower::1             668.446507                       # Core power per rank (mW)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
system.cpu0.numCycles                       816782821                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   71499658                       # Number of instructions committed
system.cpu0.committedOps                    145804776                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            133691400                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                     937441                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     14175274                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   133691400                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads          245252400                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         114908320                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            83238542                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           55564556                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     13632532                       # number of memory refs
system.cpu0.num_load_insts                   10074437                       # Number of load instructions
system.cpu0.num_store_insts                   3558095                       # Number of store instructions
system.cpu0.num_idle_cycles              775198881.273652                       # Number of idle cycles
system.cpu0.num_busy_cycles              41583939.726348                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.050912                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.949088                       # Percentage of idle cycles
system.cpu0.Branches                         15460140                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                93742      0.06%      0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu                131973601     90.51%     90.58% # Class of executed instruction
system.cpu0.op_class::IntMult                   57512      0.04%     90.62% # Class of executed instruction
system.cpu0.op_class::IntDiv                    47972      0.03%     90.65% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.65% # Class of executed instruction
system.cpu0.op_class::MemRead                10074437      6.91%     97.56% # Class of executed instruction
system.cpu0.op_class::MemWrite                3558095      2.44%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 145805359                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          1638252                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999461                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           19656533                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1638764                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            11.994731                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   126.389920                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   280.383418                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data   105.226123                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.246855                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.547624                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.205520                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          227                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          261                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88454507                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88454507                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      4870617                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      2557813                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4089779                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11518209                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3418412                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1747628                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2910585                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       8076625                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        20088                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10280                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        29520                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        59888                       # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8289029                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      4305441                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      7000364                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        19594834                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8309117                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      4315721                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      7029884                       # number of overall hits
system.cpu0.dcache.overall_hits::total       19654722                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       359255                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       161570                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       796344                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1317169                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       135705                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        61031                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       128691                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       325427                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       152338                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        62833                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       191442                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       406613                       # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data       494960                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       222601                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       925035                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1642596                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       647298                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       285434                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1116477                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2049209                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2259833750                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  13132608806                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  15392442556                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2339164805                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3938449787                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   6277614592                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   4598998555                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  17071058593                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  21670057148                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   4598998555                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  17071058593                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  21670057148                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5229872                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      2719383                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4886123                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     12835378                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3554117                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1808659                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      3039276                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      8402052                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       172426                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        73113                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       220962                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       466501                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8783989                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      4528042                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7925399                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     21237430                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      8956415                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      4601155                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      8146361                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     21703931                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.068693                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.059414                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.162981                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.102620                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.038182                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.033744                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.042343                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.038732                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.883498                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.859396                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.866402                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.871623                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.056348                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.049161                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.116718                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.077344                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.072272                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.062035                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.137052                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.094416                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13986.716284                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16491.125451                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11686.004268                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38327.486114                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30603.925581                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19290.392598                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20660.278054                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18454.500201                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13192.566613                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16112.301110                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15290.112195                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 10574.839925                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       135105                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            28093                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     4.809205                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      1547770                       # number of writebacks
system.cpu0.dcache.writebacks::total          1547770                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           57                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       372578                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       372635                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1579                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        31008                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        32587                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         1636                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       403586                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       405222                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         1636                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       403586                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       405222                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       161513                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       423766                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       585279                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        59452                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        97683                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       157135                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        62832                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       187900                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       250732                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       220965                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       521449                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       742414                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       283797                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       709349                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       993146                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1935504250                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5902265073                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7837769323                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2132980169                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3177778177                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5310758346                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    865437000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2825430002                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3690867002                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4068484419                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9080043250                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  13148527669                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4933921419                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11905473252                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  16839394671                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30454123000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33015030500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63469153500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    582453000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    716246000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1298699000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31036576000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33731276500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64767852500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.059393                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086728                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045599                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032871                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.032140                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018702                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.859382                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.850372                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.537474                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.048799                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065795                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.034958                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061680                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087076                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.045759                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11983.581817                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13928.123240                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13391.509559                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35877.349273                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32531.537494                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33797.424800                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13773.825439                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15036.881330                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14720.366774                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18412.347743                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17413.099364                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17710.506091                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17385.389624                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16783.661148                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16955.608411                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements           869855                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.839263                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          129296965                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           870367                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           148.554535                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle     149014386250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   139.113677                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   266.308370                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst   105.417216                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.271706                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.520134                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.205893                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997733                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          296                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        131061052                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       131061052                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     86941528                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     39247522                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3107915                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      129296965                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     86941528                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     39247522                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3107915                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       129296965                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     86941528                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     39247522                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3107915                       # number of overall hits
system.cpu0.icache.overall_hits::total      129296965                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       320636                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       160378                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       412688                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       893702                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       320636                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       160378                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       412688                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        893702                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       320636                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       160378                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       412688                       # number of overall misses
system.cpu0.icache.overall_misses::total       893702                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2244294000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5764913336                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   8009207336                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2244294000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   5764913336                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   8009207336                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2244294000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   5764913336                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   8009207336                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     87262164                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     39407900                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      3520603                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    130190667                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     87262164                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     39407900                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      3520603                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    130190667                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     87262164                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     39407900                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      3520603                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    130190667                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003674                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004070                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.117221                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.006865                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003674                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004070                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.117221                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.006865                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003674                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004070                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.117221                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.006865                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13993.777201                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13969.180921                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8961.832172                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13993.777201                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13969.180921                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8961.832172                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13993.777201                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13969.180921                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8961.832172                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4336                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              258                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.806202                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        23317                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        23317                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        23317                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        23317                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        23317                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        23317                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       160378                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       389371                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       549749                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       160378                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       389371                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       549749                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       160378                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       389371                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       549749                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1922680000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4757652042                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   6680332042                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1922680000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4757652042                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   6680332042                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1922680000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4757652042                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   6680332042                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004070                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.110598                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004223                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004070                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.110598                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.004223                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004070                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.110598                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.004223                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11988.427340                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12218.814555                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12151.603808                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11988.427340                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12218.814555                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12151.603808                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11988.427340                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12218.814555                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12151.603808                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                      2604022160                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   35714054                       # Number of instructions committed
system.cpu1.committedOps                     69387825                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             64459883                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     492416                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      6558216                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    64459883                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads          119340959                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          55539831                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            36447320                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           27215061                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      4790084                       # number of memory refs
system.cpu1.num_load_insts                    2979771                       # Number of load instructions
system.cpu1.num_store_insts                   1810313                       # Number of store instructions
system.cpu1.num_idle_cycles              2477161896.436619                       # Number of idle cycles
system.cpu1.num_busy_cycles              126860263.563381                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.048717                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.951283                       # Percentage of idle cycles
system.cpu1.Branches                          7226981                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                35150      0.05%      0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu                 64505894     92.96%     93.01% # Class of executed instruction
system.cpu1.op_class::IntMult                   31723      0.05%     93.06% # Class of executed instruction
system.cpu1.op_class::IntDiv                    25263      0.04%     93.10% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.10% # Class of executed instruction
system.cpu1.op_class::MemRead                 2979771      4.29%     97.39% # Class of executed instruction
system.cpu1.op_class::MemWrite                1810313      2.61%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  69388114                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups               29235559                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         29235559                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           325219                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            26520697                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               25831839                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            97.402564                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 591824                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             65511                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                       154416401                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles          10884284                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                     144162908                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   29235559                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          26423663                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                    142028644                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 680270                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                    102603                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles                5389                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             9165                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        58663                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles         3537                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          505                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  3520608                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               170393                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   3486                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples         153432274                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.849912                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            3.030749                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                98146892     63.97%     63.97% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  849455      0.55%     64.52% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                23639563     15.41%     79.93% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  596355      0.39%     80.32% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  820460      0.53%     80.85% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  843182      0.55%     81.40% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  578600      0.38%     81.78% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  712944      0.46%     82.24% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                27244823     17.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total           153432274                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.189329                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.933598                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                10016257                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             93700057                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 23552939                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles              5059225                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                340786                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts             280915475                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                340786                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                12183481                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               76207577                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       4633489                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 26208589                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles             13095410                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts             279683437                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents               223314                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents               5946104                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                 66230                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               4950669                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands          334110880                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            610223912                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       374707495                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups               50                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps            321802825                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                12308055                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            159496                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        160992                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                 24728287                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6624186                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3707561                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           399799                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          335575                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                 277732310                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             423659                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                275640781                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued           103956                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        8785176                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     13632215                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved         64646                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples    153432274                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.796498                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       2.396081                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           90704132     59.12%     59.12% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            5447937      3.55%     62.67% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            3973753      2.59%     65.26% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            3694975      2.41%     67.67% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4           22399331     14.60%     82.26% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5            2621812      1.71%     83.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6           23895005     15.57%     99.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             478633      0.31%     99.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8             216696      0.14%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total      153432274                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                1775129     86.29%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     6      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                     95      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                220574     10.72%     97.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                61430      2.99%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            78003      0.03%      0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu            265083835     96.17%     96.20% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               56667      0.02%     96.22% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                50646      0.02%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             6950861      2.52%     98.76% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3420769      1.24%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total             275640781                       # Type of FU issued
system.cpu2.iq.rate                          1.785049                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    2057234                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.007463                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         706874938                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes        286945707                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses    274032875                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                 88                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                98                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses           22                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses             277619970                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                     42                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          720639                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1236107                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         6357                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         5250                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       663784                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads       755898                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        23011                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                340786                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles               71022096                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles              1766284                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts          278155969                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            42225                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6624208                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3707561                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            245817                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                196681                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents              1270617                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          5250                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        184655                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       193373                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              378028                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts            275054919                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              6809103                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           532643                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
system.cpu2.iew.exec_refs                    10142277                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                27929616                       # Number of branches executed
system.cpu2.iew.exec_stores                   3333174                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.781255                       # Inst execution rate
system.cpu2.iew.wb_sent                     274858802                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                    274032897                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                213637344                       # num instructions producing a value
system.cpu2.iew.wb_consumers                350353641                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.774636                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.609776                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        9127323                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         359013                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           328005                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples    152066658                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.769136                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.649747                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     94590362     62.20%     62.20% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4261266      2.80%     65.01% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1284145      0.84%     65.85% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3     24598382     16.18%     82.03% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4      1032712      0.68%     82.71% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       681511      0.45%     83.15% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       477761      0.31%     83.47% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7     23127222     15.21%     98.68% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      2013297      1.32%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total    152066658                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts           136342288                       # Number of instructions committed
system.cpu2.commit.committedOps             269026601                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8431878                       # Number of memory references committed
system.cpu2.commit.loads                      5388101                       # Number of loads committed
system.cpu2.commit.membars                     162694                       # Number of memory barriers committed
system.cpu2.commit.branches                  27513301                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                245807321                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              438928                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        45809      0.02%      0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu       260445608     96.81%     96.83% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          54412      0.02%     96.85% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv           48894      0.02%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.87% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        5388101      2.00%     98.87% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       3043777      1.13%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total        269026601                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              2013297                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                   428179753                       # The number of ROB reads
system.cpu2.rob.rob_writes                  557679634                       # The number of ROB writes
system.cpu2.timesIdled                         117886                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                         984127                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  4904701568                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                  136342288                       # Number of Instructions Simulated
system.cpu2.committedOps                    269026601                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.132564                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.132564                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.882952                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.882952                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               366241285                       # number of integer regfile reads
system.cpu2.int_regfile_writes              219634896                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    72934                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   72912                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                139741848                       # number of cc regfile reads
system.cpu2.cc_regfile_writes               107405291                       # number of cc regfile writes
system.cpu2.misc_regfile_reads               89464185                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                137179                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq              3554524                       # Transaction distribution
system.iobus.trans_dist::ReadResp             3554524                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57693                       # Transaction distribution
system.iobus.trans_dist::WriteResp              10973                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1666                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1666                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7085054                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1154                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27740                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      7129192                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95242                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95242                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3332                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3332                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                 7227766                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3542527                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2308                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13870                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total      3570795                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027752                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027752                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6664                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6664                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  6605211                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              2723904                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              5226000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 4000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                25000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                15000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            142528000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy              355000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              134000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            10403000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           252354975                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1032000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           303598000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            31582004                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1142000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47566                       # number of replacements
system.iocache.tags.tagsinuse                0.080066                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47582                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5000571333009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.080066                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005004                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.005004                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428589                       # Number of tag accesses
system.iocache.tags.data_accesses              428589                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          901                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              901                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::pc.south_bridge.ide          901                       # number of demand (read+write) misses
system.iocache.demand_misses::total               901                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          901                       # number of overall misses
system.iocache.overall_misses::total              901                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    129757279                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    129757279                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   6940731692                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   6940731692                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    129757279                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    129757279                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    129757279                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    129757279                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          901                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            901                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          901                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             901                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          901                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            901                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144014.738069                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 144014.738069                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 148560.181764                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 148560.181764                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 144014.738069                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 144014.738069                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 144014.738069                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 144014.738069                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         39427                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 5130                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.685575                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          749                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          749                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        26264                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        26264                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          749                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          749                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          749                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          749                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     90783279                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     90783279                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   5574995700                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   5574995700                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     90783279                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     90783279                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     90783279                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     90783279                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.831299                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.831299                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.562158                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.562158                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.831299                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.831299                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.831299                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.831299                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 121205.979973                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212267.579196                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212267.579196                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 121205.979973                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 121205.979973                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   104681                       # number of replacements
system.l2c.tags.tagsinuse                64826.811839                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3703362                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   168901                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    21.926229                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   51337.140952                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.134260                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1734.424462                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4936.447431                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      379.153025                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1982.017983                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    11.155297                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst      876.173345                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     3570.165084                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.783343                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.026465                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.075324                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.005785                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.030243                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000170                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.013369                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.054476                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.989179                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        64220                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3804                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         7293                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52804                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.979919                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 33932949                       # Number of tag accesses
system.l2c.tags.data_accesses                33932949                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        20141                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker        10481                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             313222                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             496902                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        12246                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6578                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             158014                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             219469                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        60958                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        13844                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             383974                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             598300                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2294129                       # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
system.l2c.Writeback_hits::writebacks         1547770                       # number of Writeback hits
system.l2c.Writeback_hits::total              1547770                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             135                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              31                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              93                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 259                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            63213                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            33842                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            63914                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               160969                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         20141                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker         10483                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              313222                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              560115                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         12246                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6578                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              158014                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              253311                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         60958                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         13844                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              383974                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              662214                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2455100                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        20141                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker        10483                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             313222                       # number of overall hits
system.l2c.overall_hits::cpu0.data             560115                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        12246                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6578                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             158014                       # number of overall hits
system.l2c.overall_hits::cpu1.data             253311                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        60958                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        13844                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             383974                       # number of overall hits
system.l2c.overall_hits::cpu2.data             662214                       # number of overall hits
system.l2c.overall_hits::total                2455100                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7401                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data            14691                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2364                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4876                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           40                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             5371                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data            13291                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                48039                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data           701                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           243                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           469                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1413                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          71656                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          25348                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          33283                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             130287                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7401                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             86347                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2364                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             30224                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           40                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              5371                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             46574                       # number of demand (read+write) misses
system.l2c.demand_misses::total                178326                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7401                       # number of overall misses
system.l2c.overall_misses::cpu0.data            86347                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2364                       # number of overall misses
system.l2c.overall_misses::cpu1.data            30224                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           40                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             5371                       # number of overall misses
system.l2c.overall_misses::cpu2.data            46574                       # number of overall misses
system.l2c.overall_misses::total               178326                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst    174689000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    373593750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      3390250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    422515750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data   1051180749                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2025369499                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      3329394                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data      5421778                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      8751172                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1725333913                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   2400435156                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   4125769069                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    174689000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2098927663                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      3390250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    422515750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   3451615905                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      6151138568                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    174689000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2098927663                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      3390250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    422515750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   3451615905                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     6151138568                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        20141                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        10486                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         320623                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         511593                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        12246                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6578                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         160378                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         224345                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        60998                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        13844                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         389345                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         611591                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2342168                       # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1547770                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1547770                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data          836                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          274                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          562                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1672                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       134869                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        59190                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        97197                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           291256                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        20141                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        10488                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          320623                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          646462                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        12246                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6578                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          160378                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          283535                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        60998                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        13844                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          389345                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          708788                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2633426                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        20141                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        10488                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         320623                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         646462                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        12246                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6578                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         160378                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         283535                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        60998                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        13844                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         389345                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         708788                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2633426                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000477                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.023083                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.028716                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.014740                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.021734                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000656                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.013795                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.021732                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.020510                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.838517                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.886861                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.834520                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.845096                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.531301                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.428248                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.342428                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.447328                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000477                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.023083                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.133569                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.014740                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.106597                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000656                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.013795                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.065709                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.067716                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000477                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.023083                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.133569                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.014740                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.106597                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000656                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.013795                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.065709                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.067716                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73895.516074                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76618.898687                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 84756.250000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78666.123627                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 79089.665864                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 42160.942130                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 13701.209877                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11560.294243                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6193.327672                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68065.879478                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 72121.958838                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 31666.774651                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 73895.516074                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 69445.727336                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 84756.250000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 78666.123627                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 74110.359965                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 34493.784238                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 73895.516074                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 69445.727336                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 84756.250000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 78666.123627                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 74110.359965                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 34493.784238                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               96575                       # number of writebacks
system.l2c.writebacks::total                    96575                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst         2364                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4876                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           40                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         5371                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data        13291                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           25942                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          243                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          469                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          712                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        25348                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        33283                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         58631                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2364                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        30224                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           40                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         5371                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        46574                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            84573                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2364                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        30224                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           40                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         5371                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        46574                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           84573                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    144701000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    312699250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2894250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    355314750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    886085249                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1701694499                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      3030731                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      4866963                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      7897694                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1399676087                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1973869844                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   3373545931                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    144701000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1712375337                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      2894250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    355314750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   2859955093                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   5075240430                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    144701000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1712375337                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2894250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    355314750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   2859955093                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   5075240430                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  27999108000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30259934500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  58259042500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    541915000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    672587500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1214502500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28541023000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  30932522000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  59473545000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014740                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.021734                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000656                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.013795                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.021732                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.011076                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.886861                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.834520                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.425837                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.428248                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.342428                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.201304                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014740                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.106597                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000656                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.013795                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.065709                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.032115                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014740                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.106597                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000656                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.013795                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.065709                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.032115                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61210.236887                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64130.280968                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 72356.250000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 66154.300875                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66668.064781                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 65596.118225                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12472.144033                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10377.319829                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11092.266854                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55218.403306                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59305.646847                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 57538.604680                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61210.236887                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56656.145348                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 72356.250000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 66154.300875                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61406.688131                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 60010.173814                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61210.236887                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56656.145348                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 72356.250000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66154.300875                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61406.688131                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 60010.173814                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq             5119623                       # Transaction distribution
system.membus.trans_dist::ReadResp            5119621                       # Transaction distribution
system.membus.trans_dist::WriteReq              13885                       # Transaction distribution
system.membus.trans_dist::WriteResp             13885                       # Transaction distribution
system.membus.trans_dist::Writeback            143242                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             1670                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1670                       # Transaction distribution
system.membus.trans_dist::ReadExReq            130030                       # Transaction distribution
system.membus.trans_dist::ReadExResp           130030                       # Transaction distribution
system.membus.trans_dist::MessageReq             1666                       # Transaction distribution
system.membus.trans_dist::MessageResp            1666                       # Transaction distribution
system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3332                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3332                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7129192                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3039944                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       455611                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total     10624751                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141603                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141603                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               10769686                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3570795                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6079885                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17550016                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     27200696                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6014848                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      6014848                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                33222208                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              744                       # Total snoops (count)
system.membus.snoop_fanout::samples            370602                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  370602    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              370602                       # Request fanout histogram
system.membus.reqLayer0.occupancy           163555999                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           314970500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             2284000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1078528499                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1142000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1669525375                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           33021996                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq            7445520                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           7444981                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13887                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13887                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          1547770                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        26264                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1672                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1672                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           291256                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          291256                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1740744                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     14998032                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        73579                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       215574                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17027929                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55702976                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213603640                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       275304                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       788512                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              270370432                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                           71210                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          4262409                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            3.011172                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.105107                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                4214788     98.88%     98.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  47621      1.12%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            4262409                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         5252515580                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           954000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2476922699                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4880781676                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          25221399                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          92014088                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------