path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.144107                       # Number of seconds simulated
sim_ticks                                5144107123500                       # Number of ticks simulated
final_tick                               5144107123500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 387693                       # Simulator instruction rate (inst/s)
host_op_rate                                   770744                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             8185899527                       # Simulator tick rate (ticks/s)
host_mem_usage                                 958064                       # Number of bytes of host memory used
host_seconds                                   628.41                       # Real time elapsed on the host
sim_insts                                   243630211                       # Number of instructions simulated
sim_ops                                     484343866                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           435328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5271168                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           167488                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2239424                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         2304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           369088                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          2863936                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11377408                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       435328                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       167488                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       369088                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          971904                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9177088                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9177088                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6802                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             82362                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2617                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             34991                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           36                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              5767                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             44749                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                177772                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          143392                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143392                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               84627                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1024700                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               32559                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              435338                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           448                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               71750                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              556741                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5512                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2211736                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          84627                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          32559                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          71750                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             188935                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1784000                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1784000                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1784000                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              84627                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1024700                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              32559                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             435338                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          448                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              71750                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             556741                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5512                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3995736                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         88604                       # Number of read requests accepted
system.physmem.writeReqs                       101715                       # Number of write requests accepted
system.physmem.readBursts                       88604                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     101715                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  5666496                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      4160                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6448384                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   5670656                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6509760                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       65                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                     959                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            894                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                5172                       # Per bank write bursts
system.physmem.perBankRdBursts::1                4675                       # Per bank write bursts
system.physmem.perBankRdBursts::2                4614                       # Per bank write bursts
system.physmem.perBankRdBursts::3                5517                       # Per bank write bursts
system.physmem.perBankRdBursts::4                6171                       # Per bank write bursts
system.physmem.perBankRdBursts::5                5192                       # Per bank write bursts
system.physmem.perBankRdBursts::6                5194                       # Per bank write bursts
system.physmem.perBankRdBursts::7                5097                       # Per bank write bursts
system.physmem.perBankRdBursts::8                5481                       # Per bank write bursts
system.physmem.perBankRdBursts::9                5563                       # Per bank write bursts
system.physmem.perBankRdBursts::10               5214                       # Per bank write bursts
system.physmem.perBankRdBursts::11               5694                       # Per bank write bursts
system.physmem.perBankRdBursts::12               5834                       # Per bank write bursts
system.physmem.perBankRdBursts::13               6887                       # Per bank write bursts
system.physmem.perBankRdBursts::14               6277                       # Per bank write bursts
system.physmem.perBankRdBursts::15               5957                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6561                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6098                       # Per bank write bursts
system.physmem.perBankWrBursts::2                5964                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5948                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7233                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6043                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6495                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6502                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5629                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6174                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5473                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6467                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6126                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6747                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6614                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6682                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    5140299284500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   88604                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 101715                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     84282                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      3378                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       424                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       127                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        40                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        42                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        36                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1538                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2746                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5738                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5880                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6627                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7000                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6756                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4632                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4439                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4359                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4271                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        40184                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      301.485168                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     176.308895                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     327.181387                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          15726     39.13%     39.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         9443     23.50%     62.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4063     10.11%     72.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2232      5.55%     78.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1531      3.81%     82.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1042      2.59%     84.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          702      1.75%     86.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          613      1.53%     87.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4832     12.02%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          40184                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4135                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.412092                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      185.359125                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            4132     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5632-6143            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9728-10239            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4135                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4135                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        24.366626                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.429404                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       24.022185                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-7                69      1.67%      1.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-15                9      0.22%      1.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            3347     80.94%     82.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31             165      3.99%     86.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             114      2.76%     89.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              31      0.75%     90.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             101      2.44%     92.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              11      0.27%     93.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              26      0.63%     93.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              40      0.97%     94.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87              54      1.31%     95.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95              10      0.24%     96.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103             75      1.81%     97.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             8      0.19%     98.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119            18      0.44%     98.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             7      0.17%     98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135            15      0.36%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             4      0.10%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            12      0.29%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             5      0.12%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             2      0.05%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             2      0.05%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             1      0.02%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             4      0.10%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             2      0.05%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4135                       # Writes before turning the bus around for reads
system.physmem.totQLat                      956383499                       # Total ticks spent queuing
system.physmem.totMemAccLat                2616489749                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    442695000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10801.83                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29551.83                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.10                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.25                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.10                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.27                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.42                       # Average write queue length when enqueuing
system.physmem.readRowHits                      70796                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     78315                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   79.96                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.73                       # Row buffer hit rate for writes
system.physmem.avgGap                     27008860.31                       # Average gap between requests
system.physmem.pageHitRate                      78.77                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  147178080                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   80086875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 324729600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                329469120                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           250566494880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            94792163085                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2243751115500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             2589991237140                       # Total energy per rank (pJ)
system.physmem_0.averagePower              667.838461                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   3691094925500                       # Time in different power states
system.physmem_0.memoryStateTime::REF    128101480000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     17513749500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  156612960                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   85300875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 365874600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                323429760                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           250566494880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            95660983305                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2237004864750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             2584163561130                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.053818                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   3689804823000                       # Time in different power states
system.physmem_1.memoryStateTime::REF    128101480000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     18778765250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
system.cpu0.numCycles                       906748886                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   71802590                       # Number of instructions committed
system.cpu0.committedOps                    146381299                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            134255761                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                     943296                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     14239563                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   134255761                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads          246209877                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         115427878                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            83592437                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           55838323                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     13658115                       # number of memory refs
system.cpu0.num_load_insts                   10127652                       # Number of load instructions
system.cpu0.num_store_insts                   3530463                       # Number of store instructions
system.cpu0.num_idle_cycles              859556134.264708                       # Number of idle cycles
system.cpu0.num_busy_cycles              47192751.735292                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.052046                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.947954                       # Percentage of idle cycles
system.cpu0.Branches                         15533640                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                89870      0.06%      0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu                132527069     90.54%     90.60% # Class of executed instruction
system.cpu0.op_class::IntMult                   58535      0.04%     90.64% # Class of executed instruction
system.cpu0.op_class::IntDiv                    49919      0.03%     90.67% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.67% # Class of executed instruction
system.cpu0.op_class::MemRead                10125945      6.92%     97.59% # Class of executed instruction
system.cpu0.op_class::MemWrite                3530463      2.41%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 146381801                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          1639020                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999449                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           19713831                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1639532                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            12.024060                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   129.995226                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   275.897813                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data   106.106411                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.253897                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.538863                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.207239                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          235                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88616075                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88616075                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      4923544                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      2619910                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4021776                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11565230                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3397085                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1858074                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2831900                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       8087059                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        19915                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10654                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        29231                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        59800                       # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8320629                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      4477984                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      6853676                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        19652289                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8340544                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      4488638                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      6882907                       # number of overall hits
system.cpu0.dcache.overall_hits::total       19712089                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       358740                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       166586                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       774812                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1300138                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       129303                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        72150                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       124071                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       325524                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       150487                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        66279                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       189615                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       406381                       # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data       488043                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       238736                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       898883                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1625662                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       638530                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       305015                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1088498                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2032043                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2329828500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  11922594046                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  14252422546                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2798605810                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3955887575                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   6754493385                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   5128434310                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  15878481621                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  21006915931                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   5128434310                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  15878481621                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  21006915931                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5282284                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      2786496                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4796588                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     12865368                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3526388                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1930224                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      2955971                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      8412583                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       170402                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        76933                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       218846                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       466181                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8808672                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      4716720                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7752559                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     21277951                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      8979074                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      4793653                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      7971405                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     21744132                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.067914                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.059783                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.161534                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.101057                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.036667                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.037379                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.041973                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.038695                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.883129                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.861516                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.866431                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.871724                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.055405                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.050615                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.115947                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.076401                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.071113                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.063629                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.136550                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.093452                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13985.740098                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15387.725082                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10962.238275                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38788.715315                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31884.062956                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20749.601827                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21481.612786                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17664.681189                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 12922.068629                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16813.711817                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14587.515660                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 10337.830415                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       128988                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            27777                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     4.643698                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      1548363                       # number of writebacks
system.cpu0.dcache.writebacks::total          1548363                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           50                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       354752                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       354802                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1695                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        30847                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        32542                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         1745                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       385599                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       387344                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         1745                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       385599                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       387344                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       166536                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       420060                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       586596                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        70455                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        93224                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       163679                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        66278                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       186071                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       252349                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       236991                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       513284                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       750275                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       303269                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       699355                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1002624                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1995417000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5681817065                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7677234065                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2564306918                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3209237662                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5773544580                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    908338500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2750087755                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3658426255                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4559723918                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   8891054727                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  13450778645                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5468062418                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11641142482                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  17109204900                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30379634500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33000290500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63379925000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    574626500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    695015500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1269642000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  30954261000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33695306000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64649567000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.059765                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.087575                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045595                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036501                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031538                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019456                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.861503                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.850237                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.541311                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.050245                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.066208                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.035261                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.063265                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087733                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.046110                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11981.895806                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13526.203554                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13087.770910                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36396.379505                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34425.015683                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35273.581706                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13704.977519                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14779.776295                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14497.486636                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19240.072062                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17321.901183                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17927.798001                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18030.403431                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16645.541223                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17064.427841                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements           869493                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.803035                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          129984824                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           870005                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           149.406985                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle     149054236250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   146.476673                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   257.387173                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst   106.939188                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.286087                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.502709                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.208866                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997662                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          281                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        131747901                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       131747901                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     87329682                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     39588904                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3066238                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      129984824                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     87329682                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     39588904                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3066238                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       129984824                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     87329682                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     39588904                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3066238                       # number of overall hits
system.cpu0.icache.overall_hits::total      129984824                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       312920                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       172473                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       407665                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       893058                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       312920                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       172473                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       407665                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        893058                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       312920                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       172473                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       407665                       # number of overall misses
system.cpu0.icache.overall_misses::total       893058                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2415923500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5732417941                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   8148341441                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2415923500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   5732417941                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   8148341441                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2415923500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   5732417941                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   8148341441                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     87642602                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     39761377                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      3473903                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    130877882                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     87642602                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     39761377                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      3473903                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    130877882                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     87642602                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     39761377                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      3473903                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    130877882                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003570                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004338                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.117351                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.006824                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003570                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004338                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.117351                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.006824                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003570                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004338                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.117351                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.006824                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14007.546109                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14061.589641                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9124.089859                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14007.546109                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14061.589641                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9124.089859                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14007.546109                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14061.589641                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9124.089859                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4572                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            6                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              241                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.970954                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets            6                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        23039                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        23039                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        23039                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        23039                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        23039                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        23039                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       172473                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       384626                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       557099                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       172473                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       384626                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       557099                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       172473                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       384626                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       557099                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2070011500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4726513433                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   6796524933                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2070011500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4726513433                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   6796524933                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2070011500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4726513433                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   6796524933                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004338                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.110719                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004257                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004338                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.110719                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.004257                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004338                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.110719                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.004257                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12001.945232                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12288.595761                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12199.851253                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12001.945232                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12288.595761                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12199.851253                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12001.945232                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12288.595761                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12199.851253                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                      2608020264                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   35983855                       # Number of instructions committed
system.cpu1.committedOps                     69821911                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             64889046                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     503439                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      6569343                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    64889046                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads          120388172                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          55814326                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            36581725                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           27247591                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      4980693                       # number of memory refs
system.cpu1.num_load_insts                    3049501                       # Number of load instructions
system.cpu1.num_store_insts                   1931192                       # Number of store instructions
system.cpu1.num_idle_cycles              2477411639.002949                       # Number of idle cycles
system.cpu1.num_busy_cycles              130608624.997051                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.050080                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.949920                       # Percentage of idle cycles
system.cpu1.Branches                          7257729                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                34768      0.05%      0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu                 64752658     92.74%     92.79% # Class of executed instruction
system.cpu1.op_class::IntMult                   32117      0.05%     92.84% # Class of executed instruction
system.cpu1.op_class::IntDiv                    23661      0.03%     92.87% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     92.87% # Class of executed instruction
system.cpu1.op_class::MemRead                 3047883      4.37%     97.23% # Class of executed instruction
system.cpu1.op_class::MemWrite                1931192      2.77%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  69822279                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups               29145274                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         29145274                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           322260                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            26440523                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               25789579                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            97.538082                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 584080                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             63924                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                       153878746                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles          10764874                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                     143615831                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   29145274                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          26373659                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                    141609884                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 675175                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                     95795                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles                6373                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             7380                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        61565                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles           20                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          458                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  3473911                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               167436                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   3564                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples         152883285                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.850280                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            3.030640                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                97765346     63.95%     63.95% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  837203      0.55%     64.50% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                23601513     15.44%     79.93% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  591420      0.39%     80.32% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  819374      0.54%     80.86% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  838216      0.55%     81.40% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  577391      0.38%     81.78% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  693159      0.45%     82.24% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                27159663     17.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total           152883285                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.189404                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.933305                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 9834703                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             93251994                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 21466938                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles              4884733                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                338239                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts             279965546                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                338239                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                11923429                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               75993663                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       4610925                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 24032799                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles             12877614                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts             278749384                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents               221936                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents               5866894                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                 51314                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               4911660                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands          333127303                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            607942521                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       373256279                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups              196                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps            320819170                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                12308133                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            159156                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        160655                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                 23900033                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6505190                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3599973                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           377004                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          316512                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                 276808275                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             423236                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                274695170                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued           101004                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        8754938                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     13676659                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved         65243                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples    152883285                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.796764                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       2.395757                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           90394017     59.13%     59.13% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            5385946      3.52%     62.65% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            3961954      2.59%     65.24% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            3603407      2.36%     67.60% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4           22510778     14.72%     82.32% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5            2513602      1.64%     83.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6           23841558     15.59%     99.56% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             461559      0.30%     99.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8             210464      0.14%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total      152883285                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                1679391     85.86%     85.86% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     6      0.00%     85.86% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                    133      0.01%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     85.87% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                216471     11.07%     96.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                59961      3.07%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            81534      0.03%      0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu            264357889     96.24%     96.27% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               55368      0.02%     96.29% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                50253      0.02%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                 68      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.30% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             6828846      2.49%     98.79% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3321212      1.21%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total             274695170                       # Type of FU issued
system.cpu2.iq.rate                          1.785140                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    1955962                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.007120                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         704330322                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes        285990572                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses    273107568                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                269                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes               242                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses          106                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses             276569466                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                    132                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          697735                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1221587                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         6074                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         4844                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       639616                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads       755983                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        21219                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                338239                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles               70808815                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles              1780684                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts          277231511                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            42116                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6505190                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3599973                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            246009                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                189602                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents              1292389                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          4844                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        181953                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       192646                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              374599                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts            274123146                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              6692505                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           521898                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
system.cpu2.iew.exec_refs                     9929733                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                27833627                       # Number of branches executed
system.cpu2.iew.exec_stores                   3237228                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.781423                       # Inst execution rate
system.cpu2.iew.wb_sent                     273932637                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                    273107674                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                213006118                       # num instructions producing a value
system.cpu2.iew.wb_consumers                349346589                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.774824                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.609727                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        9088854                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         357993                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           325291                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples    151524726                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.769617                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.649272                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     94238602     62.19%     62.19% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4221946      2.79%     64.98% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1274040      0.84%     65.82% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3     24556134     16.21%     82.03% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4      1017367      0.67%     82.70% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       681486      0.45%     83.15% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       477034      0.31%     83.46% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7     23101810     15.25%     98.71% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      1956307      1.29%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total    151524726                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts           135843766                       # Number of instructions committed
system.cpu2.commit.committedOps             268140656                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8243960                       # Number of memory references committed
system.cpu2.commit.loads                      5283603                       # Number of loads committed
system.cpu2.commit.membars                     162116                       # Number of memory barriers committed
system.cpu2.commit.branches                  27422801                       # Number of branches committed
system.cpu2.commit.fp_insts                        48                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                244944567                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              433353                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        47848      0.02%      0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu       259747107     96.87%     96.89% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          53065      0.02%     96.91% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv           48699      0.02%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.93% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        5283564      1.97%     98.90% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       2960357      1.10%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total        268140656                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              1956307                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                   426769551                       # The number of ROB reads
system.cpu2.rob.rob_writes                  555823820                       # The number of ROB writes
system.cpu2.timesIdled                         116899                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                         995461                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  4917307163                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                  135843766                       # Number of Instructions Simulated
system.cpu2.committedOps                    268140656                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.132763                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.132763                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.882797                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.882797                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               364780652                       # number of integer regfile reads
system.cpu2.int_regfile_writes              218921020                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    73130                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   73024                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                139296056                       # number of cc regfile reads
system.cpu2.cc_regfile_writes               107100465                       # number of cc regfile writes
system.cpu2.misc_regfile_reads               89036481                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                137201                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq              3554570                       # Transaction distribution
system.iobus.trans_dist::ReadResp             3554570                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57725                       # Transaction distribution
system.iobus.trans_dist::WriteResp              11005                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1681                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1681                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7085054                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1154                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27896                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      7129348                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95242                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95242                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3362                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3362                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                 7227952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3542527                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2308                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13948                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total      3570873                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027752                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027752                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6724                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6724                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  6605349                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              2588568                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              4563000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 4000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            142528000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy              404000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              134000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            10340000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           221126240                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1032000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           302697000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            28304753                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1088000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47566                       # number of replacements
system.iocache.tags.tagsinuse                0.112009                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47582                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5000571390009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.112009                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007001                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.007001                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428589                       # Number of tag accesses
system.iocache.tags.data_accesses              428589                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          901                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              901                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::pc.south_bridge.ide          901                       # number of demand (read+write) misses
system.iocache.demand_misses::total               901                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          901                       # number of overall misses
system.iocache.overall_misses::total              901                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    132764027                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    132764027                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   6059046460                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   6059046460                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    132764027                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    132764027                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    132764027                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    132764027                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          901                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            901                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          901                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             901                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          901                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            901                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 147351.861265                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 147351.861265                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 129688.494435                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 129688.494435                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147351.861265                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 147351.861265                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147351.861265                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 147351.861265                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         34598                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 4497                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.693573                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          738                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          738                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        23008                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        23008                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          738                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          738                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          738                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          738                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     94361527                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     94361527                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   4862624466                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4862624466                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     94361527                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     94361527                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     94361527                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     94361527                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.819090                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.819090                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.492466                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.492466                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.819090                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.819090                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.819090                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.819090                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 127861.147696                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 211344.943759                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 211344.943759                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 127861.147696                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 127861.147696                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   104970                       # number of replacements
system.l2c.tags.tagsinuse                64826.298792                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3700737                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169148                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    21.878692                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   51221.575879                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.131319                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1714.525389                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     5051.845543                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.003637                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      364.783966                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1988.075845                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker     9.500719                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst      853.175626                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     3622.680869                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.781579                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.026162                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.077085                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.005566                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.030336                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000145                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.013018                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.055278                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.989171                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        64178                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          278                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2747                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6462                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54646                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.979279                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 33928519                       # Number of tag accesses
system.l2c.tags.data_accesses                33928519                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        20269                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker        10932                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             306104                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             491683                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        12164                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6423                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             169856                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             227750                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        59393                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        13568                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             378835                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             595825                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2292802                       # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
system.l2c.Writeback_hits::writebacks         1548363                       # number of Writeback hits
system.l2c.Writeback_hits::total              1548363                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             100                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              71                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data             101                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 272                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            63359                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            39945                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            57961                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               161265                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         20269                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker         10934                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              306104                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              555042                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         12164                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6423                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              169856                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              267695                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         59393                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         13568                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              378835                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              653786                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2454069                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        20269                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker        10934                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             306104                       # number of overall hits
system.l2c.overall_hits::cpu0.data             555042                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        12164                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6423                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             169856                       # number of overall hits
system.l2c.overall_hits::cpu1.data             267695                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        59393                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        13568                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             378835                       # number of overall hits
system.l2c.overall_hits::cpu2.data             653786                       # number of overall hits
system.l2c.overall_hits::total                2454069                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6803                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data            17544                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2617                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             5064                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           36                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             5767                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data            10237                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                48073                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data           615                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           285                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           446                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1346                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          65229                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          30166                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          34786                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             130181                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6803                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             82773                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2617                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             35230                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           36                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              5767                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             45023                       # number of demand (read+write) misses
system.l2c.demand_misses::total                178254                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6803                       # number of overall misses
system.l2c.overall_misses::cpu0.data            82773                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2617                       # number of overall misses
system.l2c.overall_misses::cpu1.data            35230                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           36                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             5767                       # number of overall misses
system.l2c.overall_misses::cpu2.data            45023                       # number of overall misses
system.l2c.overall_misses::total               178254                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    190653500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    384787000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      2953999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    449712500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data    795071749                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1823253248                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      3961367                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data      5247781                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      9209148                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   2078566202                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   2496913123                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   4575479325                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        74500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    190653500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2463353202                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      2953999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    449712500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   3291984872                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      6398732573                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        74500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    190653500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2463353202                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      2953999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    449712500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   3291984872                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     6398732573                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        20269                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        10936                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         312907                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         509227                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        12164                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6424                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         172473                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         232814                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        59429                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        13568                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         384602                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         606062                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2340875                       # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1548363                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1548363                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data          715                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          356                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          547                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1618                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       128588                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        70111                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        92747                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           291446                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        20269                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        10938                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          312907                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          637815                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        12164                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6424                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          172473                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          302925                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        59429                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        13568                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          384602                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          698809                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2632323                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        20269                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        10938                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         312907                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         637815                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        12164                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6424                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         172473                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         302925                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        59429                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        13568                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         384602                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         698809                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2632323                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000366                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.021741                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.034452                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000156                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.015173                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.021751                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000606                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.014995                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.016891                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.020536                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.860140                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.800562                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.815356                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.831891                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.507271                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.430261                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.375063                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.446673                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000366                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.021741                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.129776                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000156                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.015173                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.116299                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000606                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.014995                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.064428                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.067717                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000366                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.021741                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.129776                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000156                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.015173                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.116299                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000606                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.014995                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.064428                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.067717                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72851.929690                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 75984.794629                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 82055.527778                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77980.319057                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 77666.479340                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 37926.762382                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 13899.533333                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11766.325112                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6841.863299                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68904.269774                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71779.253809                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 35147.059287                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72851.929690                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 69922.032416                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 82055.527778                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 77980.319057                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 73117.848033                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 35896.712405                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72851.929690                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 69922.032416                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 82055.527778                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 77980.319057                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 73117.848033                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 35896.712405                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               96725                       # number of writebacks
system.l2c.writebacks::total                    96725                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         2617                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         5064                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           36                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         5767                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data        10236                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           23721                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          285                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          446                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          731                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        30166                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        34786                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         64952                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2617                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        35230                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           36                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         5767                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        45022                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            88673                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2617                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        35230                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           36                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         5767                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        45022                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           88673                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    157432500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    321524500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2508499                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    377524500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    667618251                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1526670750                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      3450773                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      4577444                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      8028217                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1690819298                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2050981877                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   3741801175                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    157432500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   2012343798                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      2508499                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    377524500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   2718600128                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   5268471925                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    157432500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   2012343798                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2508499                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    377524500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   2718600128                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   5268471925                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  27931457000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30246385500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  58177842500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    534826000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    653150000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1187976000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28466283000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  30899535500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  59365818500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000156                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.015173                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.021751                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000606                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.014995                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.016889                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.010133                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.800562                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.815356                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.451792                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.430261                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.375063                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.222861                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000156                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.015173                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.116299                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000606                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014995                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.064427                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.033686                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000156                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.015173                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.116299                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000606                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014995                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.064427                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.033686                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60157.623233                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63492.199842                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65462.892318                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65222.572392                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 64359.459972                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12107.975439                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10263.327354                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10982.512996                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56050.497182                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58959.980366                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 57608.713742                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60157.623233                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57120.175930                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65462.892318                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60383.815201                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59414.612396                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60157.623233                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57120.175930                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65462.892318                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60383.815201                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59414.612396                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq             5122083                       # Transaction distribution
system.membus.trans_dist::ReadResp            5122081                       # Transaction distribution
system.membus.trans_dist::WriteReq              13936                       # Transaction distribution
system.membus.trans_dist::WriteResp             13936                       # Transaction distribution
system.membus.trans_dist::Writeback            143392                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             1613                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1613                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129914                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129914                       # Transaction distribution
system.membus.trans_dist::MessageReq             1681                       # Transaction distribution
system.membus.trans_dist::MessageResp            1681                       # Transaction distribution
system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3362                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3362                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7129348                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3044744                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       455572                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total     10629668                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141614                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141614                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               10774644                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6724                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6724                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3570873                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6089485                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17560128                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     27220486                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6015552                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      6015552                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                33242762                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              642                       # Total snoops (count)
system.membus.snoop_fanout::samples            370612                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  370612    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              370612                       # Request fanout histogram
system.membus.reqLayer0.occupancy           162893500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           314579500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             2176000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1055146498                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1088000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1708813357                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           29666247                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq            7441673                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           7441143                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13938                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13938                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          1548363                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        23008                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1618                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1618                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           291446                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          291446                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1740014                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15004999                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        72834                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       207249                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17025096                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55679680                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213700038                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       269360                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       773664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              270422742                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                           67345                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          4256875                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            3.011187                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.105175                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                4209254     98.88%     98.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  47621      1.12%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            4256875                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         5306709352                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           945000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2510055059                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4923615960                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          25531897                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          85751327                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------