path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.133872                       # Number of seconds simulated
sim_ticks                                5133872107500                       # Number of ticks simulated
final_tick                               5133872107500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 332026                       # Simulator instruction rate (inst/s)
host_op_rate                                   659988                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6979227984                       # Simulator tick rate (ticks/s)
host_mem_usage                                 973372                       # Number of bytes of host memory used
host_seconds                                   735.59                       # Real time elapsed on the host
sim_insts                                   244235751                       # Number of instructions simulated
sim_ops                                     485482573                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           396736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5572928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           164928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          1639680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         2240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           412864                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          3220800                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11438848                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       396736                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       164928                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       412864                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          974528                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6205312                       # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9195392                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6199                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             87077                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2577                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             25620                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           35                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              6451                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             50325                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                178732                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           96958                       # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143678                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide         5523                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               77278                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1085521                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               32125                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              319385                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           436                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               80420                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              627363                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2228113                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          77278                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          32125                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          80420                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             189823                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1208700                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide       582422                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1791122                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1208700                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       587945                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              77278                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1085521                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              32125                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             319385                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          436                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              80420                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             627363                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4019235                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         85451                       # Number of read requests accepted
system.physmem.writeReqs                        85019                       # Number of write requests accepted
system.physmem.readBursts                       85451                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      85019                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  5457024                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     11840                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   5440128                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   5468864                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                5441216                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      185                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            868                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                5096                       # Per bank write bursts
system.physmem.perBankRdBursts::1                5035                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5503                       # Per bank write bursts
system.physmem.perBankRdBursts::3                5713                       # Per bank write bursts
system.physmem.perBankRdBursts::4                5011                       # Per bank write bursts
system.physmem.perBankRdBursts::5                4756                       # Per bank write bursts
system.physmem.perBankRdBursts::6                4921                       # Per bank write bursts
system.physmem.perBankRdBursts::7                5413                       # Per bank write bursts
system.physmem.perBankRdBursts::8                5128                       # Per bank write bursts
system.physmem.perBankRdBursts::9                4999                       # Per bank write bursts
system.physmem.perBankRdBursts::10               4701                       # Per bank write bursts
system.physmem.perBankRdBursts::11               5348                       # Per bank write bursts
system.physmem.perBankRdBursts::12               5396                       # Per bank write bursts
system.physmem.perBankRdBursts::13               6167                       # Per bank write bursts
system.physmem.perBankRdBursts::14               6376                       # Per bank write bursts
system.physmem.perBankRdBursts::15               5703                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5743                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5870                       # Per bank write bursts
system.physmem.perBankWrBursts::2                5006                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5323                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4689                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4481                       # Per bank write bursts
system.physmem.perBankWrBursts::6                5327                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5300                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5281                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5131                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5421                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5658                       # Per bank write bursts
system.physmem.perBankWrBursts::12               5171                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5597                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5966                       # Per bank write bursts
system.physmem.perBankWrBursts::15               5038                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    5132871981000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   85451                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  85019                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     78990                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4833                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       949                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       171                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        40                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1477                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1895                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4053                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4808                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5006                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5424                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5828                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5996                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5052                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4932                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4301                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        39962                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      272.686252                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     163.690614                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     301.316153                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          16345     40.90%     40.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         9834     24.61%     65.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4112     10.29%     75.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2230      5.58%     81.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1552      3.88%     85.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1069      2.68%     87.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          711      1.78%     89.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          597      1.49%     91.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3512      8.79%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          39962                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4105                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.770767                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      117.592245                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-255            4095     99.76%     99.76% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-511             7      0.17%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-767             1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-2815            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6656-6911            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4105                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4105                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.706943                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.214534                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.616872                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                63      1.53%      1.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 7      0.17%      1.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                1      0.02%      1.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               4      0.10%      1.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            3359     81.83%     83.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              49      1.19%     84.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              26      0.63%     85.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             173      4.21%     89.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             182      4.43%     94.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               7      0.17%     94.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              12      0.29%     94.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               8      0.19%     94.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              10      0.24%     95.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               2      0.05%     95.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               1      0.02%     95.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               1      0.02%     95.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             157      3.82%     98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               1      0.02%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               3      0.07%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              10      0.24%     99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               7      0.17%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.05%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.05%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             5      0.12%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.05%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             8      0.19%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.05%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4105                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1041221500                       # Total ticks spent queuing
system.physmem.totMemAccLat                2639959000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    426330000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12211.45                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30961.45                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.06                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.06                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.07                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.06                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         6.94                       # Average write queue length when enqueuing
system.physmem.readRowHits                      67077                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     63228                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   78.67                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.37                       # Row buffer hit rate for writes
system.physmem.avgGap                     30110118.97                       # Average gap between requests
system.physmem.pageHitRate                      76.52                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     4938526642750                       # Time in different power states
system.physmem.memoryStateTime::REF      171431260000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       23914099250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 145575360                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 156537360                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                  79431000                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                  85412250                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                323294400                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                341772600                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               270468720                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               280344240                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          335319544560                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          335319544560                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          122941148535                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          123404461065                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          2972480080500                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          2972073666000                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            3431559543075                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            3431661738075                       # Total energy per rank (pJ)
system.physmem.averagePower::0             668.415487                       # Core power per rank (mW)
system.physmem.averagePower::1             668.435393                       # Core power per rank (mW)
system.membus.trans_dist::ReadReq             5056260                       # Transaction distribution
system.membus.trans_dist::ReadResp            5056258                       # Transaction distribution
system.membus.trans_dist::WriteReq              13754                       # Transaction distribution
system.membus.trans_dist::WriteResp             13754                       # Transaction distribution
system.membus.trans_dist::Writeback             96958                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             1654                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1654                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129924                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129924                       # Transaction distribution
system.membus.trans_dist::MessageReq             1664                       # Transaction distribution
system.membus.trans_dist::MessageResp            1664                       # Transaction distribution
system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3328                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3328                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7028524                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3012958                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       456844                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total     10498330                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94955                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        94955                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               10596613                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6656                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6656                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3520458                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6025913                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17615808                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     27162179                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3029056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3029056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                30197891                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              297                       # Total snoops (count)
system.membus.snoop_fanout::samples            324529                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  324529    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              324529                       # Request fanout histogram
system.membus.reqLayer0.occupancy           165183000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           315920500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1960000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy           897247500                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy             980000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1679098885                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           35042997                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   105529                       # number of replacements
system.l2c.tags.tagsinuse                64826.632454                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3692969                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169653                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    21.767779                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   50921.041202                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.134275                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1022.158767                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3887.538850                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      285.540185                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1563.161522                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    13.370475                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1774.545144                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     5359.142034                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.776993                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.015597                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.059319                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.004357                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.023852                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000204                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.027077                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.081774                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.989176                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        64124                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          541                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3271                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         7391                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52860                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.978455                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 33891981                       # Number of tag accesses
system.l2c.tags.data_accesses                33891981                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        19672                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker        10574                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             322011                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             496358                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        11305                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6290                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             162787                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             241655                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        55032                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        13181                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             370296                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             572247                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2281408                       # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
system.l2c.Writeback_hits::writebacks         1548978                       # number of Writeback hits
system.l2c.Writeback_hits::total              1548978                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             124                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              47                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              90                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 261                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            66428                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            37696                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            62332                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               166456                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         19672                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker         10576                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              322011                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              562786                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         11305                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6290                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              162787                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              279351                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         55032                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         13181                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              370296                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              634579                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2447866                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        19672                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker        10576                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             322011                       # number of overall hits
system.l2c.overall_hits::cpu0.data             562786                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        11305                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6290                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             162787                       # number of overall hits
system.l2c.overall_hits::cpu1.data             279351                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        55032                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        13181                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             370296                       # number of overall hits
system.l2c.overall_hits::cpu2.data             634579                       # number of overall hits
system.l2c.overall_hits::total                2447866                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6199                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data            12693                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2577                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4439                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           35                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             6453                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data            15968                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                48369                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data           700                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           296                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           406                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1402                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          74470                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          21268                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          34438                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             130176                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6199                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             87163                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2577                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             25707                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           35                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              6453                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             50406                       # number of demand (read+write) misses
system.l2c.demand_misses::total                178545                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6199                       # number of overall misses
system.l2c.overall_misses::cpu0.data            87163                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2577                       # number of overall misses
system.l2c.overall_misses::cpu1.data            25707                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           35                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             6453                       # number of overall misses
system.l2c.overall_misses::cpu2.data            50406                       # number of overall misses
system.l2c.overall_misses::total               178545                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst    188438000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    344143000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      2792750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    504402750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data   1264657500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2304434000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      3069868                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data      4534805                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      7604673                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1465791412                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   2496772674                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   3962564086                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    188438000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1809934412                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      2792750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    504402750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   3761430174                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      6266998086                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    188438000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1809934412                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      2792750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    504402750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   3761430174                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     6266998086                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        19672                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        10579                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         328210                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         509051                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        11305                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6290                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         165364                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         246094                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        55067                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        13181                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         376749                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         588215                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2329777                       # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1548978                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1548978                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data          824                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          343                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          496                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1663                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       140898                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        58964                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        96770                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296632                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        19672                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        10581                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          328210                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          649949                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        11305                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6290                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          165364                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          305058                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        55067                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        13181                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          376749                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          684985                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2626411                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        19672                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        10581                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         328210                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         649949                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        11305                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6290                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         165364                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         305058                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        55067                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        13181                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         376749                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         684985                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2626411                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000473                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.018887                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.024935                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.015584                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.018038                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000636                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.017128                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.027147                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.020761                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.849515                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.862974                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.818548                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.843055                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.528538                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.360695                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.355875                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.438847                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000473                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.018887                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.134107                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.015584                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.084269                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000636                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.017128                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.073587                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.067981                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000473                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.018887                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.134107                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.015584                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.084269                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000636                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.017128                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.073587                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.067981                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73123.011253                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77527.145754                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 79792.857143                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78165.620642                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 79199.492735                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 47642.787736                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10371.175676                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11169.470443                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  5424.160485                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68920.040060                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 72500.513212                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 30440.051054                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 73123.011253                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 70406.286692                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 79792.857143                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 78165.620642                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 74622.667421                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 35100.384138                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 73123.011253                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 70406.286692                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 79792.857143                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 78165.620642                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 74622.667421                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 35100.384138                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               96958                       # number of writebacks
system.l2c.writebacks::total                    96958                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.inst         2577                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4439                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           35                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         6451                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data        15968                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           29470                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          296                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          406                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          702                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        21268                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        34438                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         55706                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2577                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        25707                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           35                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         6451                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        50406                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            85176                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2577                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        25707                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           35                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         6451                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        50406                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           85176                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    155734000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    288607000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2363250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    423558250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data   1065933000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1936195500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      2960296                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      4096905                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      7057201                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1193338588                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2055185326                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   3248523914                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    155734000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1481945588                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      2363250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    423558250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   3121118326                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   5184719414                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    155734000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1481945588                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2363250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    423558250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   3121118326                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   5184719414                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28199786500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30478398000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  58678184500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    496533000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    763698500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1260231500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28696319500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31242096500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  59938416000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.015584                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.018038                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000636                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.017123                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.027147                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.012649                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.862974                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.818548                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.422129                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.360695                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.355875                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.187795                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.015584                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.084269                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000636                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.017123                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.073587                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.032431                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.015584                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.084269                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000636                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.017123                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.073587                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.032431                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60432.285603                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65016.219869                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65657.766238                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66754.321142                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 65700.559891                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10090.899015                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.992877                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56109.581907                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59677.836285                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 58315.512045                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60432.285603                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57647.550784                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65657.766238                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61919.579534                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 60870.660914                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60432.285603                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57647.550784                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65657.766238                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61919.579534                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 60870.660914                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                47571                       # number of replacements
system.iocache.tags.tagsinuse                0.081570                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47587                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5000192639009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.081570                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005098                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.005098                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428634                       # Number of tag accesses
system.iocache.tags.data_accesses              428634                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::pc.south_bridge.ide          906                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              906                       # number of ReadReq misses
system.iocache.demand_misses::pc.south_bridge.ide          906                       # number of demand (read+write) misses
system.iocache.demand_misses::total               906                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          906                       # number of overall misses
system.iocache.overall_misses::total              906                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    132202779                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    132202779                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    132202779                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    132202779                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    132202779                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    132202779                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          906                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            906                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          906                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             906                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          906                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            906                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145919.182119                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 145919.182119                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145919.182119                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 145919.182119                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145919.182119                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 145919.182119                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           471                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   39                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.076923                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      46720                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          740                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          740                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        28368                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        28368                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          740                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          740                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          740                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          740                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     93698779                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     93698779                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   1718205368                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   1718205368                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     93698779                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     93698779                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     93698779                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     93698779                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.816777                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.816777                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.607192                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.607192                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.816777                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.816777                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.816777                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.816777                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 126619.971622                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60568.435138                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60568.435138                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 126619.971622                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 126619.971622                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq            7367165                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           7366643                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13756                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13756                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          1548978                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        28368                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1663                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1663                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296632                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296632                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1740682                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     14873990                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        71302                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       198555                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              16884529                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55700736                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213654403                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       264160                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       728920                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              270348219                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                           69633                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          4254339                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            3.011195                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.105211                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                4206713     98.88%     98.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  47626      1.12%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            4254339                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         5229007845                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           990000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2442789502                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4872933864                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          24776404                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          82986153                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq              3504325                       # Transaction distribution
system.iobus.trans_dist::ReadResp             3504325                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57563                       # Transaction distribution
system.iobus.trans_dist::WriteResp              39211                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        18352                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1664                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1664                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      6984892                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1154                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27280                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      7028524                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95252                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95252                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3328                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3328                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                 7127104                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3492446                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2308                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13640                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total      3520458                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027792                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027792                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6656                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6656                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  6554906                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              2324808                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 4000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              4502000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 1000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                30000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                15000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            143632000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy              361000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            11636000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           256433144                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1024000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           306163000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            33668003                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy              980000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
system.cpu0.numCycles                      1069607129                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   70538619                       # Number of instructions committed
system.cpu0.committedOps                    143755687                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            131850662                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                     928819                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     13976393                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   131850662                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads          241989475                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         113259644                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            82136389                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           54810829                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     13501731                       # number of memory refs
system.cpu0.num_load_insts                    9912408                       # Number of load instructions
system.cpu0.num_store_insts                   3589323                       # Number of store instructions
system.cpu0.num_idle_cycles              1016224343.330366                       # Number of idle cycles
system.cpu0.num_busy_cycles              53382785.669634                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.049909                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.950091                       # Percentage of idle cycles
system.cpu0.Branches                         15238819                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                94852      0.07%      0.07% # Class of executed instruction
system.cpu0.op_class::IntAlu                130054750     90.47%     90.53% # Class of executed instruction
system.cpu0.op_class::IntMult                   56051      0.04%     90.57% # Class of executed instruction
system.cpu0.op_class::IntDiv                    48845      0.03%     90.61% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.61% # Class of executed instruction
system.cpu0.op_class::MemRead                 9912408      6.90%     97.50% # Class of executed instruction
system.cpu0.op_class::MemWrite                3589323      2.50%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 143756229                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           869835                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.810026                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          128546541                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           870347                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           147.695736                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle     147420125000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   125.953257                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   137.567270                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst   247.289498                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.246002                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.268686                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.482987                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997676                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          116                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          228                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          168                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        130310898                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       130310898                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     85798477                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     39676062                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3072002                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      128546541                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     85798477                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     39676062                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3072002                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       128546541                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     85798477                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     39676062                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3072002                       # number of overall hits
system.cpu0.icache.overall_hits::total      128546541                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       328211                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       165364                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       400424                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       893999                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       328211                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       165364                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       400424                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        893999                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       328211                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       165364                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       400424                       # number of overall misses
system.cpu0.icache.overall_misses::total       893999                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2321256000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5686834829                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   8008090829                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2321256000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   5686834829                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   8008090829                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2321256000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   5686834829                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   8008090829                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     86126688                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     39841426                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      3472426                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    129440540                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     86126688                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     39841426                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      3472426                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    129440540                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     86126688                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     39841426                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      3472426                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    129440540                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003811                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004151                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.115315                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.006907                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003811                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004151                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.115315                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.006907                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003811                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004151                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.115315                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.006907                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14037.251155                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14202.032918                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8957.606025                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14037.251155                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14202.032918                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8957.606025                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14037.251155                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14202.032918                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8957.606025                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4468                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              254                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.590551                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        23641                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        23641                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        23641                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        23641                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        23641                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        23641                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       165364                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       376783                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       542147                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       165364                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       376783                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       542147                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       165364                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       376783                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       542147                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1989596000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4688278233                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   6677874233                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1989596000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4688278233                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   6677874233                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1989596000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4688278233                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   6677874233                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004151                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.108507                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004188                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004151                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.108507                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.004188                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004151                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.108507                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.004188                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12031.615104                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12442.913383                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12317.460454                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12031.615104                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12442.913383                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12317.460454                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12031.615104                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12442.913383                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12317.460454                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          1639466                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999450                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           19633257                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1639978                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            11.971659                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   254.719707                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   235.128668                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data    22.151075                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.497499                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.459236                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.043264                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88291742                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88291742                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      4780114                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      2623103                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4098065                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11501282                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3444198                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1705247                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2919966                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       8069411                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        17741                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        11962                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        31134                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        60837                       # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8224312                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      4328350                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      7018031                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        19570693                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8242053                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      4340312                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      7049165                       # number of overall hits
system.cpu0.dcache.overall_hits::total       19631530                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       360631                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       171099                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       767926                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1299656                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       141722                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        60933                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       123702                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       326357                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       148420                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        75080                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       181895                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       405395                       # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data       502353                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       232032                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       891628                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1626013                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       650773                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       307112                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1073523                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2031408                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2363215000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  13135142401                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  15498357401                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2121316122                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   4027899410                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   6149215532                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   4484531122                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  17163041811                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  21647572933                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   4484531122                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  17163041811                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  21647572933                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5140745                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      2794202                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4865991                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     12800938                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3585920                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1766180                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      3043668                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      8395768                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       166161                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        87042                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       213029                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       466232                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8726665                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      4560382                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7909659                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     21196706                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      8892826                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      4647424                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      8122688                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     21662938                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.070152                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.061234                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.157815                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.101528                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.039522                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.034500                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.040642                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.038872                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.893230                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.862572                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.853851                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.869513                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.057565                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.050880                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.112726                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.076711                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.073180                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.066082                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.132164                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.093773                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13811.974354                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17104.698110                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11924.968916                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34813.912363                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32561.311943                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 18841.990618                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19327.209704                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 19249.105917                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13313.284047                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 14602.266020                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15987.586490                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 10656.437768                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       138914                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            26241                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     5.293777                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      1548978                       # number of writebacks
system.cpu0.dcache.writebacks::total          1548978                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           70                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       359132                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       359202                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1638                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        26497                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        28135                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         1708                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       385629                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       387337                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         1708                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       385629                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       387337                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       171029                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       408794                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       579823                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        59295                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        97205                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       156500                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        75065                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       179480                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       254545                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       230324                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       505999                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       736323                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       305389                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       685479                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       990868                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2019901500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5830950588                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7850852088                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1912820354                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3255992760                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5168813114                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    995266500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2770573261                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3765839761                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3932721854                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9086943348                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  13019665202                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4927988354                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11857516609                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  16785504963                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30674705000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33246369000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63921074000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    534053500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    811227000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1345280500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31208758500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  34057596000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65266354500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.061209                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.084010                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045295                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033572                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031937                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018640                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.862400                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.842514                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.545962                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.050505                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.063972                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.034738                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.065711                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.084391                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.045740                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11810.286560                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14263.787110                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13540.083936                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32259.387031                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33496.144849                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33027.559834                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13258.729101                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15436.668492                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.396908                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17074.737561                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17958.421554                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17682.002602                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16136.757886                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17298.147148                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16940.202896                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                      2604021576                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   35901808                       # Number of instructions committed
system.cpu1.committedOps                     69778761                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             64893692                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     487874                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      6598396                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    64893692                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads          119938204                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          55974127                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            36929560                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           27415142                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      4838216                       # number of memory refs
system.cpu1.num_load_insts                    3070311                       # Number of load instructions
system.cpu1.num_store_insts                   1767905                       # Number of store instructions
system.cpu1.num_idle_cycles              2474835372.874957                       # Number of idle cycles
system.cpu1.num_busy_cycles              129186203.125043                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.049610                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.950390                       # Percentage of idle cycles
system.cpu1.Branches                          7267731                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                34873      0.05%      0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu                 64849393     92.94%     92.99% # Class of executed instruction
system.cpu1.op_class::IntMult                   30804      0.04%     93.03% # Class of executed instruction
system.cpu1.op_class::IntDiv                    25762      0.04%     93.07% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.07% # Class of executed instruction
system.cpu1.op_class::MemRead                 3070311      4.40%     97.47% # Class of executed instruction
system.cpu1.op_class::MemWrite                1767905      2.53%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  69779048                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups               29537500                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         29537500                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           323734                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            26929505                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               26224950                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            97.383706                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 595117                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             63666                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                       155672620                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles          10607285                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                     145694636                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   29537500                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          26820067                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                    143529975                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 676631                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                     97153                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles                5039                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             8049                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        56841                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles         4424                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          421                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  3472431                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               167012                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   3661                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples         154646852                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.855079                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            3.032629                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                98720699     63.84%     63.84% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  840447      0.54%     64.38% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                23990695     15.51%     79.89% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  599923      0.39%     80.28% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  812589      0.53%     80.81% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  861055      0.56%     81.36% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  574182      0.37%     81.73% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  718315      0.46%     82.20% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                27528947     17.80%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total           154646852                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.189741                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.935904                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                10277789                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             95381782                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 22559618                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles              5904125                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                338966                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts             283871353                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                338966                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                12885148                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               76664692                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       4829048                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 25619792                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles             14124701                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts             282624473                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents               211024                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents               6375709                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                 73879                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               5159969                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands          337473501                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            616062521                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       378507156                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups               50                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps            325128635                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                12344864                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            162095                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        163797                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                 28599466                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6606628                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3716011                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           425441                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          346966                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                 280674873                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             430305                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                278581977                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued           102725                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        8814114                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     13599788                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved         65362                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples    154646852                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.801407                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       2.400759                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           91425932     59.12%     59.12% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            5392264      3.49%     62.61% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            3912324      2.53%     65.14% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            4126244      2.67%     67.80% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4           21795400     14.09%     81.90% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5            3071037      1.99%     83.88% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6           24235245     15.67%     99.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             469170      0.30%     99.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8             219236      0.14%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total      154646852                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                2310389     89.01%     89.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                   246      0.01%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     89.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                223101      8.59%     97.61% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                62004      2.39%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            76436      0.03%      0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu            268041478     96.22%     96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               58746      0.02%     96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                49744      0.02%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             6933130      2.49%     98.77% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3422443      1.23%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total             278581977                       # Type of FU issued
system.cpu2.iq.rate                          1.789537                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    2595740                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.009318                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         714509188                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes        289923619                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses    276984093                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                 82                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                98                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses           18                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses             281101244                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                     37                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          733638                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1227908                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         6601                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         5025                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       667461                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads       754863                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        24022                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                338966                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles               71689555                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles              1628683                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts          281105178                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            39439                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6606628                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3716011                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            250069                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                194031                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents              1131651                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          5025                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        186633                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       188127                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              374760                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts            278001109                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              6795315                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           530943                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
system.cpu2.iew.exec_refs                    10133053                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                28226522                       # Number of branches executed
system.cpu2.iew.exec_stores                   3337738                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.785806                       # Inst execution rate
system.cpu2.iew.wb_sent                     277806882                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                    276984111                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                215977189                       # num instructions producing a value
system.cpu2.iew.wb_consumers                354208085                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.779273                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.609747                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        9156375                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         364943                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           326343                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples    153280377                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.774187                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.653000                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     95267512     62.15%     62.15% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4211429      2.75%     64.90% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1288351      0.84%     65.74% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3     24928908     16.26%     82.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       992667      0.65%     82.65% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       656859      0.43%     83.08% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       436979      0.29%     83.37% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7     23484943     15.32%     98.69% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      2012729      1.31%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total    153280377                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts           137795324                       # Number of instructions committed
system.cpu2.commit.committedOps             271948125                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8427269                       # Number of memory references committed
system.cpu2.commit.loads                      5378719                       # Number of loads committed
system.cpu2.commit.membars                     165391                       # Number of memory barriers committed
system.cpu2.commit.branches                  27813078                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                248363308                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              444774                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        44974      0.02%      0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu       263371453     96.85%     96.86% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          56553      0.02%     96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv           47876      0.02%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        5378719      1.98%     98.88% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       3048550      1.12%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total        271948125                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              2012729                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                   432344700                       # The number of ROB reads
system.cpu2.rob.rob_writes                  563581737                       # The number of ROB writes
system.cpu2.timesIdled                         114304                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                        1025768                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  4904031691                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                  137795324                       # Number of Instructions Simulated
system.cpu2.committedOps                    271948125                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.129738                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.129738                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.885161                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.885161                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               370036745                       # number of integer regfile reads
system.cpu2.int_regfile_writes              221903617                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    72874                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   72912                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                140867740                       # number of cc regfile reads
system.cpu2.cc_regfile_writes               108480868                       # number of cc regfile writes
system.cpu2.misc_regfile_reads               90412070                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                138782                       # number of misc regfile writes
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------