path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.142303                       # Number of seconds simulated
sim_ticks                                5142302696000                       # Number of ticks simulated
final_tick                               5142302696000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 292534                       # Simulator instruction rate (inst/s)
host_op_rate                                   581577                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6171937350                       # Simulator tick rate (ticks/s)
host_mem_usage                                 967756                       # Number of bytes of host memory used
host_seconds                                   833.17                       # Real time elapsed on the host
sim_insts                                   243732330                       # Number of instructions simulated
sim_ops                                     484555405                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           495360                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5776768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           125248                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2074112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         3968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           322688                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          2420672                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11247552                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       495360                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       125248                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       322688                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          943296                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9049984                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9049984                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              7740                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             90262                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1957                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             32408                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           62                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              5042                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             37823                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175743                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          141406                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               141406                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               96330                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1123382                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               24356                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              403343                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           772                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               62752                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              470737                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5513                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2187260                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          96330                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          24356                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          62752                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             183438                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1759909                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1759909                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1759909                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              96330                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1123382                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              24356                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             403343                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          772                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              62752                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             470737                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5513                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3947169                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         77737                       # Number of read requests accepted
system.physmem.writeReqs                        69857                       # Number of write requests accepted
system.physmem.readBursts                       77737                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      69857                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  4969408                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      5760                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4469312                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   4975168                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4470848                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       90                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                4738                       # Per bank write bursts
system.physmem.perBankRdBursts::1                4587                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5683                       # Per bank write bursts
system.physmem.perBankRdBursts::3                5272                       # Per bank write bursts
system.physmem.perBankRdBursts::4                4460                       # Per bank write bursts
system.physmem.perBankRdBursts::5                4242                       # Per bank write bursts
system.physmem.perBankRdBursts::6                4391                       # Per bank write bursts
system.physmem.perBankRdBursts::7                4725                       # Per bank write bursts
system.physmem.perBankRdBursts::8                4783                       # Per bank write bursts
system.physmem.perBankRdBursts::9                4859                       # Per bank write bursts
system.physmem.perBankRdBursts::10               4723                       # Per bank write bursts
system.physmem.perBankRdBursts::11               4859                       # Per bank write bursts
system.physmem.perBankRdBursts::12               4897                       # Per bank write bursts
system.physmem.perBankRdBursts::13               5764                       # Per bank write bursts
system.physmem.perBankRdBursts::14               5025                       # Per bank write bursts
system.physmem.perBankRdBursts::15               4639                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4788                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4346                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4813                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4456                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4399                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4368                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4481                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4596                       # Per bank write bursts
system.physmem.perBankWrBursts::8                3541                       # Per bank write bursts
system.physmem.perBankWrBursts::9                3660                       # Per bank write bursts
system.physmem.perBankWrBursts::10               3623                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4308                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4463                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5017                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4599                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4375                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    5141302561000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   77737                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  69857                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     73816                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      3057                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       363                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        36                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        34                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       24                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       24                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                        70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2083                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3603                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3481                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3524                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4830                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5601                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     3967                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     3931                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     3499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     3423                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     3455                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        34726                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      271.798192                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     162.605386                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     302.611478                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14316     41.23%     41.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         8644     24.89%     66.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3494     10.06%     76.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1847      5.32%     81.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1254      3.61%     85.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          948      2.73%     87.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          605      1.74%     89.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          474      1.36%     90.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3144      9.05%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          34726                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          3354                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        23.146989                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      204.184053                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            3351     99.91%     99.91% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535            1      0.03%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5632-6143            1      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9728-10239            1      0.03%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            3354                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          3354                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.820811                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.786469                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.927460                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                11      0.33%      0.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 7      0.21%      0.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               8      0.24%      0.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            2796     83.36%     84.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              40      1.19%     85.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              43      1.28%     86.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              85      2.53%     89.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             115      3.43%     92.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              62      1.85%     94.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              12      0.36%     94.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               6      0.18%     94.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              11      0.33%     95.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               4      0.12%     95.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               2      0.06%     95.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               2      0.06%     95.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             122      3.64%     99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               2      0.06%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               1      0.03%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               2      0.06%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               3      0.09%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.03%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.03%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.03%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.03%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.03%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             8      0.24%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.03%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.03%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.03%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.03%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             2      0.06%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            3354                       # Writes before turning the bus around for reads
system.physmem.totQLat                      822128507                       # Total ticks spent queuing
system.physmem.totMemAccLat                2278009757                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    388235000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10588.03                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29338.03                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.97                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.87                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.97                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.87                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         3.53                       # Average write queue length when enqueuing
system.physmem.readRowHits                      61504                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     51248                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   79.21                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.36                       # Row buffer hit rate for writes
system.physmem.avgGap                     34834089.20                       # Average gap between requests
system.physmem.pageHitRate                      76.44                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  129729600                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   70607625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 297164400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                234880560                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           250511061840                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            94606706745                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2237443433250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             2583293584020                       # Total energy per rank (pJ)
system.physmem_0.averagePower              667.968853                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   3690534116962                       # Time in different power states
system.physmem_0.memoryStateTime::REF    128073140000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     17232140788                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  132798960                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   72319500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 308451000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                217637280                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           250511061840                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            94562869185                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2235084583500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             2580889721265                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.037449                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   3690605945988                       # Time in different power states
system.physmem_1.memoryStateTime::REF    128073140000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     17153124512                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
system.cpu0.numCycles                       902046715                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu0.committedInsts                   73959427                       # Number of instructions committed
system.cpu0.committedOps                    150307597                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            138246700                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                    1066960                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     14495182                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   138246700                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads          254560897                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         118518911                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            85690938                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           57098279                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     14889374                       # number of memory refs
system.cpu0.num_load_insts                   10848208                       # Number of load instructions
system.cpu0.num_store_insts                   4041166                       # Number of store instructions
system.cpu0.num_idle_cycles              853760386.040518                       # Number of idle cycles
system.cpu0.num_busy_cycles              48286328.959482                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.053530                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.946470                       # Percentage of idle cycles
system.cpu0.Branches                         15948833                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                97349      0.06%      0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu                135200596     89.95%     90.01% # Class of executed instruction
system.cpu0.op_class::IntMult                   70034      0.05%     90.06% # Class of executed instruction
system.cpu0.op_class::IntDiv                    52579      0.03%     90.10% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.10% # Class of executed instruction
system.cpu0.op_class::MemRead                10846498      7.22%     97.31% # Class of executed instruction
system.cpu0.op_class::MemWrite                4041166      2.69%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 150308222                       # Class of executed instruction
system.cpu0.dcache.tags.replacements          1651251                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.996861                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           20452818                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1651763                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            12.382417                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   417.977148                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data    68.931894                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data    25.087819                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.816362                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.134633                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.049000                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          165                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         91512129                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        91512129                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5600779                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      2451508                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4254630                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       12306917                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3889675                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1677991                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2514442                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       8082108                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        23860                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10736                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        27491                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        62087                       # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9490454                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      4129499                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      6769072                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        20389025                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9514314                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      4140235                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      6796563                       # number of overall hits
system.cpu0.dcache.overall_hits::total       20451112                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       387262                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       176472                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       719884                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1283618                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       146675                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        64233                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       112265                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       323173                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       158823                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        68896                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       179464                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       407183                       # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data       533937                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       240705                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       832149                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1606791                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       692760                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       309601                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1011613                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2013974                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2460813500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9669943500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  12130757000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2732722991                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3586634440                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   6319357431                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   5193536491                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  13256577940                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  18450114431                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   5193536491                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  13256577940                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  18450114431                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5988041                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      2627980                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4974514                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     13590535                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4036350                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1742224                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      2626707                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      8405281                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       182683                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        79632                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       206955                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       469270                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     10024391                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      4370204                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7601221                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     21995816                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     10207074                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      4449836                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      7808176                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     22465086                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.064673                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.067151                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.144714                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.094449                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.036339                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.036868                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.042740                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.038449                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.869391                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.865180                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.867164                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.867695                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.053264                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.055079                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.109476                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.073050                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.067871                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069576                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.129558                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.089649                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13944.498277                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 13432.641231                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total  9450.441642                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42543.910311                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31947.930700                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19554.100841                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21576.354837                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 15930.534003                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 11482.585122                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16774.934483                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 13104.396582                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total  9161.048966                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       149019                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            19247                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     7.742453                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      1557863                       # number of writebacks
system.cpu0.dcache.writebacks::total          1557863                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           49                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       325442                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       325491                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1624                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        29845                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        31469                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         1673                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       355287                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       356960                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         1673                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       355287                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       356960                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       176423                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       394442                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       570865                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        62609                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        82420                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       145029                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        68896                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       176057                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       244953                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       239032                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       476862                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       715894                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       307928                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       652919                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       960847                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       175968                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       193387                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total       369355                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         2768                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4032                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total         6800                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       178736                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       197419                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total       376155                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2283564500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5222076000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7505640500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2580696991                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2983674940                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5564371931                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   1020231000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2452891500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3473122500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4864261491                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   8205750940                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  13070012431                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5884492491                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  10658642440                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  16543134931                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30715210000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33235671500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63950881500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  30715210000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33235671500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  63950881500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.067133                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.079293                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.042005                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.035936                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031378                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017255                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.865180                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.850702                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.521987                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.054696                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.062735                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.032547                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069200                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.083620                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.042771                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12943.689315                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13239.147961                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13147.837930                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41219.265457                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36200.860713                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38367.305373                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14808.276242                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13932.371334                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14178.730205                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20349.833876                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17207.810520                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18256.910145                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19109.962365                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16324.601428                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17217.241591                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174549.974995                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 171860.939463                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173142.048977                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171846.801987                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 168350.926203                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170012.046896                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements           956706                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.794700                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          133067935                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           957218                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           139.015287                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle     150766905000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   303.387688                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst    65.665696                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst   141.741316                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.592554                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.128253                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.276839                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997646                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          235                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        135039924                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       135039924                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     90259731                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     39032907                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3775297                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      133067935                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     90259731                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     39032907                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3775297                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       133067935                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     90259731                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     39032907                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3775297                       # number of overall hits
system.cpu0.icache.overall_hits::total      133067935                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       368418                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       164616                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       481723                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1014757                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       368418                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       164616                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       481723                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1014757                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       368418                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       164616                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       481723                       # number of overall misses
system.cpu0.icache.overall_misses::total      1014757                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2280778000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6376139484                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   8656917484                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2280778000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   6376139484                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   8656917484                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2280778000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   6376139484                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   8656917484                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     90628149                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     39197523                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      4257020                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    134082692                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     90628149                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     39197523                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      4257020                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    134082692                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     90628149                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     39197523                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      4257020                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    134082692                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.004065                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004200                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.113160                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.007568                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.004065                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004200                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.113160                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.007568                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.004065                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004200                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.113160                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.007568                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13855.141663                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13236.111799                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8531.025146                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13855.141663                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13236.111799                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8531.025146                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13855.141663                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13236.111799                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8531.025146                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3656                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              267                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.692884                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks       956706                       # number of writebacks
system.cpu0.icache.writebacks::total           956706                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        57525                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        57525                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        57525                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        57525                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        57525                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        57525                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       164616                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       424198                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       588814                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       164616                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       424198                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       588814                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       164616                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       424198                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       588814                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2116162000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5491871486                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   7608033486                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2116162000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5491871486                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   7608033486                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2116162000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5491871486                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   7608033486                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004200                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.099647                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004391                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004200                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.099647                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.004391                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004200                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.099647                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.004391                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12855.141663                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12946.481327                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12920.945300                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12855.141663                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12946.481327                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12920.945300                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12855.141663                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12946.481327                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12920.945300                       # average overall mshr miss latency
system.cpu1.numCycles                      2608017339                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                   35627427                       # Number of instructions committed
system.cpu1.committedOps                     68998423                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             64051827                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     468203                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      6587290                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    64051827                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads          118624529                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          55196381                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            36419223                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           27076219                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      4628508                       # number of memory refs
system.cpu1.num_load_insts                    2883555                       # Number of load instructions
system.cpu1.num_store_insts                   1744953                       # Number of store instructions
system.cpu1.num_idle_cycles              2479194289.218051                       # Number of idle cycles
system.cpu1.num_busy_cycles              128823049.781949                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.049395                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.950605                       # Percentage of idle cycles
system.cpu1.Branches                          7222524                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                27694      0.04%      0.04% # Class of executed instruction
system.cpu1.op_class::IntAlu                 64285165     93.17%     93.21% # Class of executed instruction
system.cpu1.op_class::IntMult                   28263      0.04%     93.25% # Class of executed instruction
system.cpu1.op_class::IntDiv                    29212      0.04%     93.29% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.29% # Class of executed instruction
system.cpu1.op_class::MemRead                 2883455      4.18%     97.47% # Class of executed instruction
system.cpu1.op_class::MemWrite                1744953      2.53%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  68998742                       # Class of executed instruction
system.cpu2.branchPred.lookups               31199361                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         31199361                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           851763                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            30042490                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 863549                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect            181695                       # Number of incorrect RAS predictions.
system.cpu2.branchPred.indirectLookups       30042490                       # Number of indirect predictor lookups.
system.cpu2.branchPred.indirectHits          24994810                       # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses         5047680                       # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted       585906                       # Number of mispredicted indirect branches.
system.cpu2.numCycles                       154015967                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles          10525182                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                     153136013                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   31199361                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          25858359                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                    140984091                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                1735783                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                    143780                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles               16316                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             7923                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        66490                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles           26                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          488                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  4257020                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               368090                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   3025                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples         152611536                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.969429                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            3.111517                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                95212585     62.39%     62.39% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  896814      0.59%     62.98% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                23718994     15.54%     78.52% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  549190      0.36%     78.88% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  778244      0.51%     79.39% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  799023      0.52%     79.91% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  532989      0.35%     80.26% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  720428      0.47%     80.73% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                29403269     19.27%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total           152611536                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.202572                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.994287                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                10167862                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             90185488                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 25340442                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles              4831486                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                868543                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts             293911699                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                868543                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                12378234                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               76415835                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       3891181                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 27683635                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles             10156457                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts             290176548                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents               179480                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents               5269403                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                 20140                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               2921556                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands          344456385                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            633379614                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       389227303                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups              120                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps            317474127                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                26982256                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            189266                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        192828                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                 22388341                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             7330700                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            4149427                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           414211                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          341335                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                 283979915                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             425629                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                278392066                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued           405323                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined       19156154                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     28402257                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved         93435                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples    152611536                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.824188                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       2.420511                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           90358507     59.21%     59.21% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            4845557      3.18%     62.38% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            3452107      2.26%     64.65% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            3415281      2.24%     66.88% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4           22680576     14.86%     81.74% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5            2703807      1.77%     83.52% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6           24243891     15.89%     99.40% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             602713      0.39%     99.80% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8             309097      0.20%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total      152611536                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                1789790     87.09%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     87.09% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                208308     10.14%     97.22% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                57058      2.78%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass           101487      0.04%      0.04% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu            267636712     96.14%     96.17% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               50542      0.02%     96.19% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                41904      0.02%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                 34      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             7148788      2.57%     98.77% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3412599      1.23%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total             278392066                       # Type of FU issued
system.cpu2.iq.rate                          1.807553                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    2055156                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.007382                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         711855943                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes        303565687                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses    275033680                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                203                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes               174                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses           83                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses             280345636                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                     99                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          602114                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      2634716                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses        13210                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         5396                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores      1520030                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads       706535                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        19267                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                868543                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles               71343644                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles              2239546                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts          284405544                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            59883                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              7330707                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             4149427                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            256703                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                145075                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents              1788429                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          5396                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        270430                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       847907                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts             1118337                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts            276410000                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              6693207                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts          1826872                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
system.cpu2.iew.exec_refs                     9818298                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                27929809                       # Number of branches executed
system.cpu2.iew.exec_stores                   3125091                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.794684                       # Inst execution rate
system.cpu2.iew.wb_sent                     275971770                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                    275033763                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                214243041                       # num instructions producing a value
system.cpu2.iew.wb_consumers                350261962                       # num instructions consuming a value
system.cpu2.iew.wb_rate                      1.785748                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.611665                       # average fanout of values written-back
system.cpu2.commit.commitSquashedInsts       19130941                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         332194                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           855634                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples    149565660                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.773464                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.653305                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     93221920     62.33%     62.33% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      3884084      2.60%     64.93% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1108913      0.74%     65.67% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3     24362236     16.29%     81.96% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       961331      0.64%     82.60% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       644406      0.43%     83.03% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       409687      0.27%     83.30% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7     23249373     15.54%     98.85% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      1723710      1.15%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total    149565660                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts           134145476                       # Number of instructions committed
system.cpu2.commit.committedOps             265249385                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       7325387                       # Number of memory references committed
system.cpu2.commit.loads                      4695990                       # Number of loads committed
system.cpu2.commit.membars                     151817                       # Number of memory barriers committed
system.cpu2.commit.branches                  27066281                       # Number of branches committed
system.cpu2.commit.fp_insts                        48                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                241954507                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              387238                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        47651      0.02%      0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu       257791047     97.19%     97.21% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          45496      0.02%     97.22% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv           40577      0.02%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.24% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        4695201      1.77%     99.01% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       2629397      0.99%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total        265249385                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              1723710                       # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads                   432186718                       # The number of ROB reads
system.cpu2.rob.rob_writes                  571865889                       # The number of ROB writes
system.cpu2.timesIdled                         138407                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                        1404431                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  4914533165                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                  134145476                       # Number of Instructions Simulated
system.cpu2.committedOps                    265249385                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.148126                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.148126                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.870984                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.870984                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               365815904                       # number of integer regfile reads
system.cpu2.int_regfile_writes              220629753                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    73051                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   73024                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                138624705                       # number of cc regfile reads
system.cpu2.cc_regfile_writes               107019387                       # number of cc regfile writes
system.cpu2.misc_regfile_reads               89775262                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                129105                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq              3544820                       # Transaction distribution
system.iobus.trans_dist::ReadResp             3544820                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57702                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57702                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1686                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1686                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7065558                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1126                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27910                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio         2308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      7109792                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95252                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95252                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3372                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3372                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                 7208416                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3532779                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2252                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13955                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio         4477                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total      3561050                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027792                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027792                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6744                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6744                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  6595586                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              2583988                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                36000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              4499500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               934500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                19000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                17500                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                21000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy            199160500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy               352000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               77500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            13461500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           119181081                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1081000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           283709000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            25934000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1055000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47571                       # number of replacements
system.iocache.tags.tagsinuse                0.093993                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47587                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5004596403009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.093993                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005875                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.005875                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428634                       # Number of tag accesses
system.iocache.tags.data_accesses              428634                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          906                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              906                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47626                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47626                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47626                       # number of overall misses
system.iocache.overall_misses::total            47626                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    120463801                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    120463801                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   2718328280                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   2718328280                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide   2838792081                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   2838792081                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide   2838792081                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   2838792081                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          906                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            906                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47626                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47626                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47626                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47626                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 132962.252759                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 132962.252759                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 58183.396404                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 58183.396404                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 59605.931235                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 59605.931235                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 59605.931235                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 59605.931235                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           354                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   28                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.642857                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          711                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          711                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        22880                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        22880                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        23591                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        23591                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        23591                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        23591                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     84913801                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     84913801                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1572541335                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   1572541335                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   1657455136                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1657455136                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   1657455136                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1657455136                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.784768                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.784768                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.489726                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.489726                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.495339                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.495339                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.495339                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.495339                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119428.693390                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 119428.693390                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68729.953453                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68729.953453                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 70257.943114                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70257.943114                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 70257.943114                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70257.943114                       # average overall mshr miss latency
system.l2c.tags.replacements                   102742                       # number of replacements
system.l2c.tags.tagsinuse                64807.232548                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4917874                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   166881                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    29.469346                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   50676.768734                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.131121                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1597.619840                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     5190.937172                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.003338                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      233.485852                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1577.800752                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    27.152241                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker     0.957955                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1336.692253                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     4165.683291                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.773266                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.024378                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.079207                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.003563                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.024075                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000414                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.020396                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.063563                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.988880                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        64139                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          571                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3312                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         7441                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52737                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.978683                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 43620877                       # Number of tag accesses
system.l2c.tags.data_accesses                43620877                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        21700                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker        11096                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         4762                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         2301                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker       121788                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        15231                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 176878                       # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
system.l2c.WritebackDirty_hits::writebacks      1557863                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         1557863                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks       955842                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total          955842                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data             146                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              66                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              62                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 274                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            74219                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            34448                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            53501                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               162168                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        360664                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        162659                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst        419122                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total            942445                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       526913                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       240478                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data       560799                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          1328190                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         21700                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker         11098                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              360664                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              601132                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          4762                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          2301                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              162659                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              274926                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker        121788                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         15231                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              419122                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              614300                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2609683                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        21700                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker        11098                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             360664                       # number of overall hits
system.l2c.overall_hits::cpu0.data             601132                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         4762                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         2301                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             162659                       # number of overall hits
system.l2c.overall_hits::cpu1.data             274926                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker       121788                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        15231                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             419122                       # number of overall hits
system.l2c.overall_hits::cpu2.data             614300                       # number of overall hits
system.l2c.overall_hits::total                2609683                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           62                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                   68                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data           768                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           293                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           283                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1344                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          71542                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          27814                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          28615                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             127971                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         7741                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         1957                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst         5043                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           14741                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data        19172                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         4841                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data         9660                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          33673                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.itb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7741                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             90714                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1957                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             32655                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           62                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              5043                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             38275                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176453                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7741                       # number of overall misses
system.l2c.overall_misses::cpu0.data            90714                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1957                       # number of overall misses
system.l2c.overall_misses::cpu1.data            32655                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           62                       # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             5043                       # number of overall misses
system.l2c.overall_misses::cpu2.data            38275                       # number of overall misses
system.l2c.overall_misses::total               176453                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        83500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      5420500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker        83500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total        5587500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      4987500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data      4499000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      9486500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   2114236500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   2284326500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   4398563000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    159298500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst    429808000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total    589106500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    409237000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data    815088000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1224325000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        83500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    159298500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2523473500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      5420500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker        83500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    429808000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   3099414500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      6217582000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        83500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    159298500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2523473500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      5420500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker        83500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    429808000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   3099414500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     6217582000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        21700                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        11100                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         4762                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         2302                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker       121850                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        15232                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             176946                       # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      1557863                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      1557863                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks       955842                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total       955842                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data          914                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          359                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          345                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1618                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       145761                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        62262                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        82116                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           290139                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       368405                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       164616                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst       424165                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total        957186                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       546085                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       245319                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data       570459                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      1361863                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        21700                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        11102                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          368405                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          691846                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         4762                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         2302                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          164616                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          307581                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker       121850                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        15232                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          424165                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          652575                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2786136                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        21700                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        11102                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         368405                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         691846                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         4762                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         2302                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         164616                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         307581                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker       121850                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        15232                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         424165                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         652575                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2786136                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000360                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000434                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000509                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000066                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.000384                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.840263                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.816156                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.820290                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.830655                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.490817                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.446725                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.348470                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.441068                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.021012                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011888                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.011889                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.015400                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.035108                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.019733                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.016934                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.024726                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000360                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.021012                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.131119                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000434                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011888                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.106167                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000509                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker     0.000066                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.011889                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.058652                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.063333                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000360                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.021012                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.131119                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000434                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011888                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.106167                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000509                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker     0.000066                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.011889                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.058652                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.063333                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        83500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87427.419355                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        83500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 82169.117647                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17022.184300                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15897.526502                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  7058.407738                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76013.392536                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79829.687227                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 34371.560744                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81399.335718                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 85228.633750                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 39963.808425                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84535.633134                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 84377.639752                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 36359.249250                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 81399.335718                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 77276.787628                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87427.419355                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker        83500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 85228.633750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 80977.517962                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 35236.476569                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 81399.335718                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 77276.787628                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87427.419355                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker        83500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 85228.633750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 80977.517962                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 35236.476569                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               94739                       # number of writebacks
system.l2c.writebacks::total                    94739                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           62                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total              64                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          293                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          283                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          576                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        27814                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        28615                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         56429                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1957                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5042                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total         6999                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         4841                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data         9660                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        14501                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1957                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        32655                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           62                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         5042                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        38275                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            77993                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1957                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        32655                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           62                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         5042                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        38275                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           77993                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data       175968                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data       193387                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total       369355                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2768                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4032                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total         6800                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data       178736                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data       197419                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       376155                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        73500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      4800500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker        73500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total      4947500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      6159500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      5718500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     11878000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1836096500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1998176500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   3834273000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    139728500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    379329000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total    519057500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    360827000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data    746886000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1107713000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    139728500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   2196923500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      4800500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    379329000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   2745062500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   5465991000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        73500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    139728500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   2196923500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      4800500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker        73500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    379329000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   2745062500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   5465991000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28515609500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30818304000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  59333913500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28515609500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  30818304000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  59333913500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000434                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000509                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000066                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.000362                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.816156                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.820290                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.355995                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.446725                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.348470                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.194490                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011888                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.011887                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.007312                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.019733                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.016934                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.010648                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000434                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011888                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.106167                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000509                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000066                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011887                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.058652                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.027993                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000434                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011888                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.106167                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000509                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000066                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011887                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.058652                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.027993                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        73500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 77304.687500                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21022.184300                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20206.713781                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20621.527778                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66013.392536                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69829.687227                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 67948.625707                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71399.335718                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75233.835779                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74161.665952                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74535.633134                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77317.391304                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76388.731812                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71399.335718                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67276.787628                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        73500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75233.835779                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71719.464402                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 70083.097201                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71399.335718                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67276.787628                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        73500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75233.835779                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71719.464402                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 70083.097201                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162049.972154                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 159360.784334                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160641.966401                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159540.380785                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 156106.068818                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 157737.936489                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        375707                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       160970                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         1170                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq             5049003                       # Transaction distribution
system.membus.trans_dist::ReadResp            5098173                       # Transaction distribution
system.membus.trans_dist::WriteReq              13918                       # Transaction distribution
system.membus.trans_dist::WriteResp             13918                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       141406                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8879                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             1627                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             897                       # Transaction distribution
system.membus.trans_dist::ReadExReq            127688                       # Transaction distribution
system.membus.trans_dist::ReadExResp           127688                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         49387                       # Transaction distribution
system.membus.trans_dist::MessageReq             1686                       # Transaction distribution
system.membus.trans_dist::MessageResp            1686                       # Transaction distribution
system.membus.trans_dist::BadAddressError          217                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        23840                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3372                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3372                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7109792                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3016050                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       456814                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          434                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total     10583090                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       119675                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       119675                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               10706137                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6744                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6744                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3561050                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6032097                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17304384                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     26897531                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3027520                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3027520                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                29931795                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              596                       # Total snoops (count)
system.membus.snoop_fanout::samples           5365465                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.001972                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.044366                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 5354883     99.80%     99.80% # Request fanout histogram
system.membus.snoop_fanout::1                   10582      0.20%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             5365465                       # Request fanout histogram
system.membus.reqLayer0.occupancy           219694000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           286587500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             2585012                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy           464604174                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy              267500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1530012                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1157102500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy            3622087                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.toL2Bus.snoop_filter.tot_requests      5251700                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2642649                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         1467                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            797                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          797                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq            5252356                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           7571420                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13920                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13920                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      1604861                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean       956706                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict           97687                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1618                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1618                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           290139                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          290139                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq        957232                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      1362205                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError          217                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4436                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2871137                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15084519                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        67785                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       321441                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              18344882                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    122489920                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    215022523                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       256088                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side      1230880                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              338999411                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          130547                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          9049191                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.003896                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.062298                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                9013933     99.61%     99.61% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  35258      0.39%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            9049191                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         3319937995                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           330397                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         883646129                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1813359528                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          21309973                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         140489176                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------