path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.139557                       # Number of seconds simulated
sim_ticks                                5139557121500                       # Number of ticks simulated
final_tick                               5139557121500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 183644                       # Simulator instruction rate (inst/s)
host_op_rate                                   364835                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3871369364                       # Simulator tick rate (ticks/s)
host_mem_usage                                 967408                       # Number of bytes of host memory used
host_seconds                                  1327.58                       # Real time elapsed on the host
sim_insts                                   243802016                       # Number of instructions simulated
sim_ops                                     484348047                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2455296                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           466944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5828928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           127616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          1842944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         1536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           356032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          2734144                       # Number of bytes read from this memory
system.physmem.bytes_read::total             13813760                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       466944                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       127616                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       356032                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          950592                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9154048                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9154048                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        38364                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              7296                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             91077                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1994                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             28796                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           24                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              5563                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             42721                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                215840                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          143032                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143032                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       477725                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               90853                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1134130                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               24830                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              358580                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           299                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               69273                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              531980                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2687734                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          90853                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          24830                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          69273                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             184956                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1781097                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1781097                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1781097                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       477725                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              90853                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1134130                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              24830                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             358580                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          299                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              69273                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             531980                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4468830                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         99105                       # Total number of read requests seen
system.physmem.writeReqs                        78746                       # Total number of write requests seen
system.physmem.cpureqs                         178569                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                      6342720                       # Total number of bytes read from memory
system.physmem.bytesWritten                   5039744                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                6342720                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                5039744                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       11                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                712                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                  6100                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                  5671                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                  5539                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                  6946                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                  5876                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                  5654                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                  5883                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                  7012                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                  6334                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                  6064                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                 5868                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                 7100                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                 5762                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                 5656                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                 6255                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                 7374                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  4754                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  4366                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  4230                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  5859                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  4494                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  4387                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  4605                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  5921                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  5001                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  4809                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 4668                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 5984                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 4422                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 4352                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 4757                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 6137                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           6                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5135869541000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                   99105                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  78746                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                     75637                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      7751                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      3409                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1725                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      1554                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      1226                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       983                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       957                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       916                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       876                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      581                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      527                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      479                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      448                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      405                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      409                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      465                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      448                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      189                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2865                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3038                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3360                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3426                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      3422                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      3426                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     3424                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     3421                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     3419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     3417                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     3415                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3414                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3412                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3404                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     3400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      412                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        7                       # What write queue length does an incoming req see
system.physmem.totQLat                     2229520000                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                4250910000                       # Sum of mem lat for all requests
system.physmem.totBusLat                    495470000                       # Total cycles spent in databus access
system.physmem.totBankLat                  1525920000                       # Total cycles spent in bank access
system.physmem.avgQLat                       22499.04                       # Average queueing delay per request
system.physmem.avgBankLat                    15398.71                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  42897.75                       # Average memory access latency
system.physmem.avgRdBW                           1.23                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.98                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   1.23                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.98                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                         0.10                       # Average write queue length over time
system.physmem.readRowHits                      83478                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     56534                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   84.24                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  71.79                       # Row buffer hit rate for writes
system.physmem.avgGap                     28877372.30                       # Average gap between requests
system.l2c.replacements                        104936                       # number of replacements
system.l2c.tagsinuse                     64827.217537                       # Cycle average of tags in use
system.l2c.total_refs                         3630977                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        168979                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         21.487741                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        50639.454481                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.125451                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          1092.997242                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          4517.674660                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           223.356063                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          1300.523613                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.dtb.walker       6.306120                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst          1891.819622                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data          5154.960284                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.772697                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000002                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.016678                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.068934                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.003408                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.019844                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.dtb.walker      0.000096                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.028867                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.078658                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.989185                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        20688                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker        11397                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             368018                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             524840                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         3790                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         1830                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             151783                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             229669                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        45217                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker         8673                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             312711                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             544544                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2223160                       # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
system.l2c.Writeback_hits::writebacks         1544951                       # number of Writeback hits
system.l2c.Writeback_hits::total              1544951                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             152                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              41                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              67                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 260                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            71407                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            43953                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            57565                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               172925                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         20688                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker         11399                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              368018                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              596247                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          3790                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          1830                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              151783                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              273622                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         45217                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker          8673                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              312711                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              602109                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2396087                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        20688                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker        11399                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             368018                       # number of overall hits
system.l2c.overall_hits::cpu0.data             596247                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         3790                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         1830                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             151783                       # number of overall hits
system.l2c.overall_hits::cpu1.data             273622                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        45217                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker         8673                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             312711                       # number of overall hits
system.l2c.overall_hits::cpu2.data             602109                       # number of overall hits
system.l2c.overall_hits::total                2396087                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7296                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data            14431                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1994                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4052                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           24                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             5567                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data            14790                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                48159                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data           746                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           231                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           361                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1338                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          77254                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          24966                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          28044                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             130264                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7296                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             91685                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1994                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             29018                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           24                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              5567                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             42834                       # number of demand (read+write) misses
system.l2c.demand_misses::total                178423                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7296                       # number of overall misses
system.l2c.overall_misses::cpu0.data            91685                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1994                       # number of overall misses
system.l2c.overall_misses::cpu1.data            29018                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           24                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             5567                       # number of overall misses
system.l2c.overall_misses::cpu2.data            42834                       # number of overall misses
system.l2c.overall_misses::total               178423                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst    122911000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    250826000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      1797000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    390878500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data    976895991                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1743308491                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1987000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data      4443500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      6430500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1303821500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   1552905500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2856727000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    122911000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1554647500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      1797000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    390878500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   2529801491                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      4600035491                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    122911000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1554647500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      1797000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    390878500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   2529801491                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     4600035491                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        20688                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        11402                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         375314                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         539271                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         3790                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         1830                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         153777                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         233721                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        45241                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker         8673                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         318278                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         559334                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2271319                       # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1544951                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1544951                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data          898                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          272                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          428                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1598                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       148661                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        68919                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        85609                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           303189                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        20688                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        11404                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          375314                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          687932                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         3790                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         1830                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          153777                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          302640                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        45241                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker         8673                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          318278                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          644943                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2574510                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        20688                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        11404                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         375314                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         687932                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         3790                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         1830                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         153777                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         302640                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        45241                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker         8673                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         318278                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         644943                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2574510                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000439                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.019440                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.026760                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.012967                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.017337                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000530                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.017491                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.026442                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.021203                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.830735                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.849265                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.843458                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.837297                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.519666                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.362251                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.327582                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.429646                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000438                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.019440                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.133276                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.012967                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.095883                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000530                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.017491                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.066415                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.069304                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000438                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.019440                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.133276                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.012967                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.095883                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000530                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.017491                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.066415                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.069304                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 61640.421264                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 61901.776900                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker        74875                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70213.490210                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 66051.115010                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 36199.017650                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  8601.731602                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12308.864266                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  4806.053812                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52223.884483                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 55373.894594                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 21930.287723                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 61640.421264                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 53575.280860                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker        74875                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 70213.490210                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 59060.594178                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 25781.628439                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 61640.421264                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 53575.280860                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker        74875                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 70213.490210                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 59060.594178                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 25781.628439                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               96365                       # number of writebacks
system.l2c.writebacks::total                    96365                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 4                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  4                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 4                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.inst         1994                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4052                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           24                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         5563                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data        14790                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           26423                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          231                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          361                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          592                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        24966                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        28044                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         53010                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1994                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        29018                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           24                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         5563                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        42834                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            79433                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1994                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        29018                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           24                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         5563                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        42834                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           79433                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     97847743                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    200215627                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      1495274                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    321284586                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    792603807                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1413447037                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      2410729                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      3666859                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      6077588                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    988776449                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1199056726                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2187833175                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     97847743                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1188992076                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      1495274                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    321284586                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   1991660533                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   3601280212                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     97847743                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1188992076                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      1495274                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    321284586                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   1991660533                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   3601280212                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28659296500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30447811500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  59107108000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    345721500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    690071500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1035793000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  29005018000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31137883000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  60142901000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.012967                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017337                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000530                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.017478                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.026442                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.011633                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.849265                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.843458                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.370463                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.362251                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.327582                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.174841                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.012967                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.095883                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000530                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.017478                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.066415                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.030854                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.012967                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.095883                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000530                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.017478                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.066415                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.030854                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 49071.084754                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49411.556515                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57753.835341                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 53590.521095                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 53493.056693                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10436.056277                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10157.504155                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10266.195946                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 39604.920652                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 42756.266082                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41272.084041                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 49071.084754                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40974.294438                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57753.835341                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46497.187585                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 45337.330983                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 49071.084754                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40974.294438                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57753.835341                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46497.187585                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 45337.330983                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     47571                       # number of replacements
system.iocache.tagsinuse                     0.100524                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47587                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              4999700789059                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.100524                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.006283                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.006283                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          906                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              906                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47626                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47626                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47626                       # number of overall misses
system.iocache.overall_misses::total            47626                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide     21701996                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21701996                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   5260229904                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   5260229904                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide   5281931900                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   5281931900                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide   5281931900                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   5281931900                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          906                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            906                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47626                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47626                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47626                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47626                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 23953.637969                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 23953.637969                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 112590.537329                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 112590.537329                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 110904.377861                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 110904.377861                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 110904.377861                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 110904.377861                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         67344                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 6552                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.278388                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          169                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          169                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        24864                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        24864                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        25033                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        25033                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        25033                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        25033                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     12912498                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12912498                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   3966572850                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   3966572850                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   3979485348                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3979485348                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   3979485348                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3979485348                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.186534                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.186534                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide     0.532192                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total     0.532192                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.525616                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.525616                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.525616                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.525616                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 76405.313609                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76405.313609                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 159530.761342                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 159530.761342                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 158969.574082                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 158969.574082                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu0.numCycles                      1838156995                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   73261263                       # Number of instructions committed
system.cpu0.committedOps                    148566469                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            136919559                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                    1069041                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     14289344                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   136919559                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads          336929611                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         173945922                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     14717824                       # number of memory refs
system.cpu0.num_load_insts                   10660250                       # Number of load instructions
system.cpu0.num_store_insts                   4057574                       # Number of store instructions
system.cpu0.num_idle_cycles              1090327710419.609375                       # Number of idle cycles
system.cpu0.num_busy_cycles              -1088489553424.609375                       # Number of busy cycles
system.cpu0.not_idle_fraction             -592.163540                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                  593.163540                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu0.icache.replacements                846873                       # number of replacements
system.cpu0.icache.tagsinuse               510.809979                       # Cycle average of tags in use
system.cpu0.icache.total_refs               129726169                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                847385                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                153.089999                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle          147287067000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   322.415881                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst    27.501112                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu2.inst   160.892986                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.629719                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst     0.053713                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu2.inst     0.314244                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.997676                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     89310227                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     37866681                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      2549261                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      129726169                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     89310227                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     37866681                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      2549261                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       129726169                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     89310227                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     37866681                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      2549261                       # number of overall hits
system.cpu0.icache.overall_hits::total      129726169                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       375314                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       153777                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       335702                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       864793                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       375314                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       153777                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       335702                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        864793                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       375314                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       153777                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       335702                       # number of overall misses
system.cpu0.icache.overall_misses::total       864793                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2109411000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4767990981                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6877401981                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2109411000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   4767990981                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6877401981                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2109411000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   4767990981                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6877401981                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     89685541                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     38020458                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      2884963                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    130590962                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     89685541                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     38020458                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      2884963                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    130590962                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     89685541                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     38020458                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      2884963                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    130590962                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.004185                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004045                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.116363                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.006622                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.004185                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004045                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.116363                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.006622                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.004185                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004045                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.116363                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.006622                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13717.337443                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14203.046097                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  7952.656857                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13717.337443                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14203.046097                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  7952.656857                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13717.337443                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14203.046097                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  7952.656857                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         6416                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              225                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    28.515556                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        17396                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        17396                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        17396                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        17396                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        17396                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        17396                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       153777                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       318306                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       472083                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       153777                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       318306                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       472083                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       153777                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       318306                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       472083                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1801857000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3960171483                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   5762028483                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1801857000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3960171483                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   5762028483                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1801857000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3960171483                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   5762028483                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004045                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.110333                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.003615                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004045                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.110333                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.003615                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004045                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.110333                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.003615                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11717.337443                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12441.397533                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12205.541151                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11717.337443                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12441.397533                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12205.541151                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11717.337443                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12441.397533                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12205.541151                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1634958                       # number of replacements
system.cpu0.dcache.tagsinuse               511.999366                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                19655982                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1635470                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 12.018552                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle               7549500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   482.608033                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data    17.353549                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu2.data    12.037784                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.942594                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data     0.033894                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu2.data     0.023511                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      5624800                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      2207994                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      3726568                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11559362                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3904284                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1548034                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2642598                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       8094916                       # number of WriteReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9529084                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      3756028                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      6369166                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        19654278                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9529084                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      3756028                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      6369166                       # number of overall hits
system.cpu0.dcache.overall_hits::total       19654278                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       539271                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       233721                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       917659                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1690651                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       149559                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        69191                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data        97336                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       316086                       # number of WriteReq misses
system.cpu0.dcache.demand_misses::cpu0.data       688830                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       302912                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1014995                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2006737                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       688830                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       302912                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1014995                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2006737                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3256389500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  15046703000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  18303092500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1959155500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   2564161499                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   4523316999                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   5215545000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  17610864499                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  22826409499                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   5215545000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  17610864499                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  22826409499                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6164071                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      2441715                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4644227                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     13250013                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4053843                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1617225                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      2739934                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      8411002                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     10217914                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      4058940                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7384161                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     21661015                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     10217914                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      4058940                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      7384161                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     21661015                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.087486                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.095720                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.197591                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.127596                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.036893                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.042784                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.035525                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.037580                       # miss rate for WriteReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.067414                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.074628                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.137456                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.092643                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.067414                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.074628                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.137456                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.092643                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13932.806637                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16396.834772                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10826.061973                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28315.178275                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26343.403253                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 14310.399698                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17218.020415                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17350.690889                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 11374.888438                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17218.020415                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17350.690889                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 11374.888438                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       180086                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            11859                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.185597                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      1544951                       # number of writebacks
system.cpu0.dcache.writebacks::total          1544951                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       358302                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       358302                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        11322                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        11322                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       369624                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       369624                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       369624                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       369624                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       233721                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       559357                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       793078                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        69191                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        86014                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       155205                       # number of WriteReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       302912                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       645371                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       948283                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       302912                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       645371                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       948283                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2788947500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   8180959500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  10969907000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1820773500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2270883499                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4091656999                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4609721000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  10451842999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  15061563999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4609721000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  10451842999                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  15061563999                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  31167993500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33212773000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  64380766500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    368756500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    730986500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1099743000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31536750000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33943759500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65480509500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.095720                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.120441                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.059855                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.042784                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031393                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018453                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.074628                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.087399                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.043778                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.074628                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087399                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.043778                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11932.806637                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14625.649630                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13832.065698                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26315.178275                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26401.324191                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26362.920003                       # average WriteReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15218.020415                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16195.092434                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15882.984298                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15218.020415                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16195.092434                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15882.984298                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                      2606004355                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   34463532                       # Number of instructions committed
system.cpu1.committedOps                     67005357                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             62150402                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     411236                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      6382216                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    62150402                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads          149729485                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          79937808                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      4253944                       # number of memory refs
system.cpu1.num_load_insts                    2634755                       # Number of load instructions
system.cpu1.num_store_insts                   1619189                       # Number of store instructions
system.cpu1.num_idle_cycles              7677367348.593150                       # Number of idle cycles
system.cpu1.num_busy_cycles              -5071362993.593150                       # Number of busy cycles
system.cpu1.not_idle_fraction               -1.946030                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    2.946030                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups               28657213                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         28657213                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           282528                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            26332341                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               25809696                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            98.015197                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 509678                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             56598                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                       152138342                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles           8765036                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                     141230370                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   28657213                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          26319374                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                     54195726                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                1350224                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                     59186                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.BlockedCycles              22546148                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                3184                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             6465                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        18223                       # Number of stall cycles due to pending traps
system.cpu2.fetch.IcacheWaitRetryStallCycles          777                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  2884967                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               126552                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   1685                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples          86648155                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             3.214672                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            3.414816                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                32565830     37.58%     37.58% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  546380      0.63%     38.21% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                23846422     27.52%     65.74% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  287955      0.33%     66.07% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  558507      0.64%     66.71% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  803239      0.93%     67.64% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  320738      0.37%     68.01% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  484990      0.56%     68.57% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                27234094     31.43%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            86648155                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.188363                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.928302                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                10203383                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             21434341                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 42926723                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles              1270829                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles               1056674                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts             277800524                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts                   10                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles               1056674                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                11171095                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               12732005                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       3756843                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 43068844                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles              5106557                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts             276894625                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                 6426                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents               2483944                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents              1961652                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.FullRegisterEvents            2548                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands          331033770                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            601753258                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       601753178                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups               80                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps            321557178                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                 9476592                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            136008                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        137084                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                 11206153                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             5917951                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3223233                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           365517                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          302609                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                 275352384                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             397965                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                273886109                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            53996                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        6700477                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     10323870                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved         50144                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     86648155                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        3.160899                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       2.377923                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           23779115     27.44%     27.44% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            5842995      6.74%     34.19% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            3792974      4.38%     38.56% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            2596888      3.00%     41.56% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4           25119641     28.99%     70.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5            1266341      1.46%     72.01% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6           23944050     27.63%     99.65% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             257275      0.30%     99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8              48876      0.06%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       86648155                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                 118795     33.06%     33.06% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                   241      0.07%     33.13% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                     86      0.02%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     33.15% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                188736     52.53%     85.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                51440     14.32%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            68063      0.02%      0.02% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu            264478225     96.57%     96.59% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               51078      0.02%     96.61% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                47173      0.02%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.63% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             6223177      2.27%     98.90% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3018393      1.10%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total             273886109                       # Type of FU issued
system.cpu2.iq.rate                          1.800244                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                     359298                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001312                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         634870698                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes        282454128                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses    272600027                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                 31                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                36                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            8                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses             274177330                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                     14                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          614321                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads       929558                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         6267                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         3704                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       478908                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads       656133                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        10377                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles               1056674                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                8226180                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles               803204                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts          275750349                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            63685                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              5917951                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3223233                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            220549                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                623968                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                 3956                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          3704                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        161931                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       157888                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              319819                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts            273437676                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              6124763                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           448433                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
system.cpu2.iew.exec_refs                     9083662                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                27821550                       # Number of branches executed
system.cpu2.iew.exec_stores                   2958899                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.797296                       # Inst execution rate
system.cpu2.iew.wb_sent                     273301697                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                    272600035                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                212879972                       # num instructions producing a value
system.cpu2.iew.wb_consumers                348297595                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.791790                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.611201                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        6973062                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         347821                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           284653                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     85591481                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     3.140222                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.867307                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     28429929     33.22%     33.22% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4148762      4.85%     38.06% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1193631      1.39%     39.46% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3     24678313     28.83%     68.29% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       797871      0.93%     69.22% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       541346      0.63%     69.85% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       330295      0.39%     70.24% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7     23445398     27.39%     97.63% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      2025936      2.37%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     85591481                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts           136077221                       # Number of instructions committed
system.cpu2.commit.committedOps             268776221                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       7732718                       # Number of memory references committed
system.cpu2.commit.loads                      4988393                       # Number of loads committed
system.cpu2.commit.membars                     163760                       # Number of memory barriers committed
system.cpu2.commit.branches                  27507890                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                245262632                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              414873                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events              2025936                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                   359289994                       # The number of ROB reads
system.cpu2.rob.rob_writes                  552558663                       # The number of ROB writes
system.cpu2.timesIdled                         454161                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                       65490187                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  4914041775                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                  136077221                       # Number of Instructions Simulated
system.cpu2.committedOps                    268776221                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total            136077221                       # Number of Instructions Simulated
system.cpu2.cpi                              1.118029                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.118029                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.894431                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.894431                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               502349004                       # number of integer regfile reads
system.cpu2.int_regfile_writes              325553024                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    62552                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   62544                       # number of floating regfile writes
system.cpu2.misc_regfile_reads               88383748                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                121022                       # number of misc regfile writes
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------