path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.140310                       # Number of seconds simulated
sim_ticks                                5140310078000                       # Number of ticks simulated
final_tick                               5140310078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 269101                       # Simulator instruction rate (inst/s)
host_op_rate                                   534933                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5691143534                       # Simulator tick rate (ticks/s)
host_mem_usage                                1043812                       # Number of bytes of host memory used
host_seconds                                   903.21                       # Real time elapsed on the host
sim_insts                                   243055556                       # Number of instructions simulated
sim_ops                                     483158347                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           444224                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5333440                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           157504                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          1822656                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         1984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           355648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          3199424                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11343552                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       444224                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       157504                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       355648                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          957376                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9153408                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9153408                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6941                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             83335                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2461                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             28479                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           31                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              5557                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             49991                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                177243                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          143022                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143022                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               86420                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1037572                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               30641                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              354581                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           386                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               69188                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              622418                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5516                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2206784                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          86420                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          30641                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          69188                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             186249                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1780711                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1780711                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1780711                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              86420                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1037572                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              30641                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             354581                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          386                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              69188                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             622418                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5516                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3987495                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         86962                       # Number of read requests accepted
system.physmem.writeReqs                        83127                       # Number of write requests accepted
system.physmem.readBursts                       86962                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      83127                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  5558208                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   5320128                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   5565568                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                5320128                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          33935                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                5197                       # Per bank write bursts
system.physmem.perBankRdBursts::1                4660                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5410                       # Per bank write bursts
system.physmem.perBankRdBursts::3                5303                       # Per bank write bursts
system.physmem.perBankRdBursts::4                5131                       # Per bank write bursts
system.physmem.perBankRdBursts::5                4781                       # Per bank write bursts
system.physmem.perBankRdBursts::6                5593                       # Per bank write bursts
system.physmem.perBankRdBursts::7                5451                       # Per bank write bursts
system.physmem.perBankRdBursts::8                5257                       # Per bank write bursts
system.physmem.perBankRdBursts::9                4895                       # Per bank write bursts
system.physmem.perBankRdBursts::10               5205                       # Per bank write bursts
system.physmem.perBankRdBursts::11               5208                       # Per bank write bursts
system.physmem.perBankRdBursts::12               5485                       # Per bank write bursts
system.physmem.perBankRdBursts::13               6574                       # Per bank write bursts
system.physmem.perBankRdBursts::14               6603                       # Per bank write bursts
system.physmem.perBankRdBursts::15               6094                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5588                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5124                       # Per bank write bursts
system.physmem.perBankWrBursts::2                5267                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4836                       # Per bank write bursts
system.physmem.perBankWrBursts::4                5431                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5206                       # Per bank write bursts
system.physmem.perBankWrBursts::6                5103                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5105                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5093                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5184                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5317                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5091                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4613                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5354                       # Per bank write bursts
system.physmem.perBankWrBursts::15               5452                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
system.physmem.totGap                    5136428746000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   86962                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  83127                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     81204                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4342                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       810                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       173                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        44                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        34                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       24                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       24                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1437                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1785                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4088                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4015                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4455                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4826                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5556                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6655                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5012                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4540                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4596                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4073                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4016                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        39704                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      273.985896                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     164.719261                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     301.548634                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          16089     40.52%     40.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         9815     24.72%     65.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4115     10.36%     75.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2259      5.69%     81.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1546      3.89%     85.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1077      2.71%     87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          717      1.81%     89.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          581      1.46%     91.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3505      8.83%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          39704                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4014                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.636024                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      232.585773                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            4011     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-14847            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4014                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4014                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.709268                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.149216                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.865339                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                66      1.64%      1.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 4      0.10%      1.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                1      0.02%      1.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               5      0.12%      1.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            3286     81.86%     83.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             102      2.54%     86.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              31      0.77%     87.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             110      2.74%     89.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              16      0.40%     90.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             107      2.67%     92.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              56      1.40%     94.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               3      0.07%     94.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              12      0.30%     94.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              20      0.50%     95.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               2      0.05%     95.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               4      0.10%     95.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             148      3.69%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.10%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              15      0.37%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.02%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.07%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            10      0.25%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.05%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4014                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1058164225                       # Total ticks spent queuing
system.physmem.totMemAccLat                2686545475                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    434235000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12184.23                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30934.23                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.08                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.03                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.08                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.03                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.23                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         6.40                       # Average write queue length when enqueuing
system.physmem.readRowHits                      68775                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     61495                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   79.19                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.98                       # Row buffer hit rate for writes
system.physmem.avgGap                     30198476.95                       # Average gap between requests
system.physmem.pageHitRate                      76.64                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  145461960                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   79191750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 323902800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                269956800                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           250383413280                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            96312598470                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2240118682500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             2587633207560                       # Total energy per rank (pJ)
system.physmem_0.averagePower              667.890236                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   3686035921978                       # Time in different power states
system.physmem_0.memoryStateTime::REF    128007880000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     19846503022                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  154700280                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   84191250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 353503800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                268706160                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           250383413280                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            96598721655                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2233305647250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             2581148883675                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.102542                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   3685636098978                       # Time in different power states
system.physmem_1.memoryStateTime::REF    128007880000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     20213469772                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
system.cpu0.numCycles                      1072285216                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu0.committedInsts                   71949475                       # Number of instructions committed
system.cpu0.committedOps                    146629560                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            134558001                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                     963710                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     14252688                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   134558001                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads          246915369                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         115616478                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            83804950                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           55920141                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     13826864                       # number of memory refs
system.cpu0.num_load_insts                   10217566                       # Number of load instructions
system.cpu0.num_store_insts                   3609298                       # Number of store instructions
system.cpu0.num_idle_cycles              1017808473.109560                       # Number of idle cycles
system.cpu0.num_busy_cycles              54476742.890440                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.050804                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.949196                       # Percentage of idle cycles
system.cpu0.Branches                         15573120                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                93860      0.06%      0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu                132602493     90.43%     90.50% # Class of executed instruction
system.cpu0.op_class::IntMult                   58992      0.04%     90.54% # Class of executed instruction
system.cpu0.op_class::IntDiv                    49730      0.03%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::MemRead                10215736      6.97%     97.54% # Class of executed instruction
system.cpu0.op_class::MemWrite                3609298      2.46%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 146630109                       # Class of executed instruction
system.cpu0.dcache.tags.replacements          1637599                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999082                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           19598772                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1638111                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            11.964252                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   184.195837                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   211.604771                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data   116.198475                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.359757                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.413291                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.226950                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999998                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          241                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          250                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88194499                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88194499                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      4977444                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      2398985                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4079357                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11455786                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3466929                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1632241                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2982365                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       8081535                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        21705                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data         9720                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        28159                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        59584                       # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8444373                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      4031226                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      7061722                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        19537321                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8466078                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      4040946                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      7089881                       # number of overall hits
system.cpu0.dcache.overall_hits::total       19596905                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       370513                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       153426                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       785141                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1309080                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       138237                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        55177                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       133227                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       326641                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       157440                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        58723                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       190305                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       406468                       # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data       508750                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       208603                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       918368                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1635721                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       666190                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       267326                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1108673                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2042189                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2248360000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  12710748500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  14959108500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   3673730495                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   6566018901                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  10239749396                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   5922090495                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  19276767401                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  25198857896                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   5922090495                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  19276767401                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  25198857896                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5347957                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      2552411                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4864498                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     12764866                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3605166                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1687418                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      3115592                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      8408176                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       179145                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        68443                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       218464                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       466052                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8953123                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      4239829                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7980090                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     21173042                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      9132268                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      4308272                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      8198554                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     21639094                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.069281                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.060110                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.161402                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.102553                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.038344                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.032699                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.042761                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.038848                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.878841                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.857984                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.871105                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.872152                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.056824                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.049201                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.115082                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.077255                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.072949                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.062049                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.135228                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.094375                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14654.361060                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16189.128450                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11427.191997                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 66580.830690                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 49284.446103                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 31348.634727                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28389.287283                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20990.242910                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15405.352072                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22153.065901                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17387.243489                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12339.140939                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       206703                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            22011                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.390895                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      1548077                       # number of writebacks
system.cpu0.dcache.writebacks::total          1548077                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           70                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       363716                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       363786                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1660                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        33557                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        35217                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         1730                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       397273                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       399003                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         1730                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       397273                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       399003                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       153356                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       421425                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       574781                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        53517                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        99670                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       153187                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        58722                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       186896                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       245618                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       206873                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       521095                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       727968                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       265595                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       707991                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       973586                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       176326                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       193522                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total       369848                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3494                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         2876                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total         6370                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       179820                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       196398                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total       376218                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2092039500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   6051222000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8143261500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   3446784995                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5707170401                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9153955396                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   1012070500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2960619500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3972690000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   5538824495                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  11758392401                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  17297216896                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   6550894995                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  14719011901                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  21269906896                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30675451000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  32998765500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63674216500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    673827500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    612020000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1285847500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31349278500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33610785500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64960064000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.060083                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086633                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045028                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.031715                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031991                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018219                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.857969                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.855500                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.527018                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.048793                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065299                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.034382                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061648                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.086356                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.044992                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13641.719268                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14358.953550                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14167.589917                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 64405.422483                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57260.664202                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59756.737817                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17234.946017                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15840.999807                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.262473                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26774.032837                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22564.776866                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23760.957756                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24664.978614                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20789.829109                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21846.972837                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173970.095165                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170516.868883                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172163.203532                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192852.747567                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212802.503477                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201859.890110                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174336.995329                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171136.088453                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172666.018107                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements           862079                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.743965                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          129387157                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           862591                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           149.998269                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle     149036221500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   146.474513                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   126.887139                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst   237.382314                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.286083                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.247826                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.463637                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997547                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          152                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          277                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        131136403                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       131136403                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     87656734                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     38708215                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3022208                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      129387157                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     87656734                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     38708215                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3022208                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       129387157                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     87656734                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     38708215                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3022208                       # number of overall hits
system.cpu0.icache.overall_hits::total      129387157                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       322605                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       163640                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       400399                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       886644                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       322605                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       163640                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       400399                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        886644                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       322605                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       163640                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       400399                       # number of overall misses
system.cpu0.icache.overall_misses::total       886644                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2424218000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5939623464                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   8363841464                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2424218000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   5939623464                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   8363841464                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2424218000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   5939623464                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   8363841464                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     87979339                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     38871855                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      3422607                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    130273801                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     87979339                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     38871855                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      3422607                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    130273801                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     87979339                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     38871855                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      3422607                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    130273801                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003667                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004210                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.116987                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.006806                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003667                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004210                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.116987                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.006806                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003667                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004210                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.116987                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.006806                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14814.336348                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14834.261484                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9433.145055                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14814.336348                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14834.261484                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9433.145055                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14814.336348                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14834.261484                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9433.145055                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        13267                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              575                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.073043                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks       862079                       # number of writebacks
system.cpu0.icache.writebacks::total           862079                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        24042                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        24042                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        24042                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        24042                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        24042                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        24042                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       163640                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       376357                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       539997                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       163640                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       376357                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       539997                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       163640                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       376357                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       539997                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2260578000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5251926966                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   7512504966                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2260578000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5251926966                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   7512504966                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2260578000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5251926966                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   7512504966                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004210                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.109962                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004145                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004210                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.109962                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.004145                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004210                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.109962                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.004145                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13814.336348                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13954.641380                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13912.123523                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13814.336348                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13954.641380                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13912.123523                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13814.336348                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13954.641380                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13912.123523                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                      2606017772                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                   35434797                       # Number of instructions committed
system.cpu1.committedOps                     68967057                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             63950611                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     471158                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      6540301                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    63950611                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads          118144126                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          55187106                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            36132535                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           26987071                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      4484181                       # number of memory refs
system.cpu1.num_load_insts                    2795215                       # Number of load instructions
system.cpu1.num_store_insts                   1688966                       # Number of store instructions
system.cpu1.num_idle_cycles              2475079667.780020                       # Number of idle cycles
system.cpu1.num_busy_cycles              130938104.219980                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.050245                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.949755                       # Percentage of idle cycles
system.cpu1.Branches                          7181908                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                31577      0.05%      0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu                 64398957     93.38%     93.42% # Class of executed instruction
system.cpu1.op_class::IntMult                   30119      0.04%     93.47% # Class of executed instruction
system.cpu1.op_class::IntDiv                    23752      0.03%     93.50% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.50% # Class of executed instruction
system.cpu1.op_class::MemRead                 2793855      4.05%     97.55% # Class of executed instruction
system.cpu1.op_class::MemWrite                1688966      2.45%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  68967226                       # Class of executed instruction
system.cpu2.branchPred.lookups               28923329                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         28923329                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           299282                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            26177543                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               25594622                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            97.773202                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 576797                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             63162                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                       157005453                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles          10540975                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                     142872413                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   28923329                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          26171419                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                    144748563                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 631577                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                    103277                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles               10569                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             7821                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        68344                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles           26                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles         1893                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  3422619                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               155063                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   2960                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples         155796605                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.805087                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            3.007326                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0               100986274     64.82%     64.82% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  876971      0.56%     65.38% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                23450168     15.05%     80.43% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  581136      0.37%     80.81% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  798057      0.51%     81.32% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  839354      0.54%     81.86% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  536255      0.34%     82.20% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  727896      0.47%     82.67% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                27000494     17.33%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total           155796605                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.184219                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.909984                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 9166270                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             95860787                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 22254534                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles              3994693                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                316440                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts             278480395                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                316440                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                10781716                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               77380942                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       5123914                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 24366684                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles             13623085                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts             277321096                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents               194260                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents               5340054                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                 70865                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               6669514                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands          331396172                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            605049332                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       371619608                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups              206                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps            320040545                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                11355627                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            162880                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        164114                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                 19801512                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6563978                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3714528                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           447098                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          397095                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                 275506715                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             407720                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                273559358                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            95175                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        8352705                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     12694060                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved         62726                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples    155796605                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.755875                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       2.385543                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           93882329     60.26%     60.26% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            5118192      3.29%     63.54% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            3721128      2.39%     65.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            3254343      2.09%     68.02% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4           23198440     14.89%     82.91% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5            2207021      1.42%     84.33% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6           23723391     15.23%     99.56% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             467418      0.30%     99.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8             224343      0.14%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total      155796605                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                1207560     81.79%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     81.79% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                207213     14.03%     95.82% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                61669      4.18%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            77609      0.03%      0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu            263069409     96.17%     96.19% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               56423      0.02%     96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                50250      0.02%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                 74      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             6863260      2.51%     98.74% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3442333      1.26%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total             273559358                       # Type of FU issued
system.cpu2.iq.rate                          1.742356                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    1476442                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.005397                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         704486629                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes        284271419                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses    272061524                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                309                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes               294                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses          118                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses             274958042                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                    149                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          723498                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1134318                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         5680                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         5091                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       595155                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads       712054                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        23601                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                316440                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles               69933639                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles              4486006                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts          275914435                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            35023                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6563978                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3714528                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            243237                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                162474                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents              4012628                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          5091                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        167077                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       180895                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              347972                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts            273011944                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              6727791                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           497508                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
system.cpu2.iew.exec_refs                    10089541                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                27708179                       # Number of branches executed
system.cpu2.iew.exec_stores                   3361750                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.738869                       # Inst execution rate
system.cpu2.iew.wb_sent                     272840114                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                    272061642                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                212265363                       # num instructions producing a value
system.cpu2.iew.wb_consumers                348191102                       # num instructions consuming a value
system.cpu2.iew.wb_rate                      1.732817                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.609623                       # average fanout of values written-back
system.cpu2.commit.commitSquashedInsts        8350016                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         344994                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           302940                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples    154548999                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.731242                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.636335                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     97452573     63.06%     63.06% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4255618      2.75%     65.81% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1276058      0.83%     66.64% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3     24388972     15.78%     82.42% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       952831      0.62%     83.03% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       707614      0.46%     83.49% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       433779      0.28%     83.77% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7     23017420     14.89%     98.66% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      2064134      1.34%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total    154548999                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts           135671284                       # Number of instructions committed
system.cpu2.commit.committedOps             267561730                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8549033                       # Number of memory references committed
system.cpu2.commit.loads                      5429660                       # Number of loads committed
system.cpu2.commit.membars                     149565                       # Number of memory barriers committed
system.cpu2.commit.branches                  27339879                       # Number of branches committed
system.cpu2.commit.fp_insts                        48                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                244517945                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              438137                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        46306      0.02%      0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu       258863559     96.75%     96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          54521      0.02%     96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv           48345      0.02%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        5429610      2.03%     98.83% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       3119373      1.17%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total        267561730                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              2064134                       # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads                   428366748                       # The number of ROB reads
system.cpu2.rob.rob_writes                  553077080                       # The number of ROB writes
system.cpu2.timesIdled                         112413                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                        1208848                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  4910585835                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                  135671284                       # Number of Instructions Simulated
system.cpu2.committedOps                    267561730                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.157249                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.157249                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.864118                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.864118                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               363754203                       # number of integer regfile reads
system.cpu2.int_regfile_writes              218036965                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    73086                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                138800226                       # number of cc regfile reads
system.cpu2.cc_regfile_writes               106739606                       # number of cc regfile writes
system.cpu2.misc_regfile_reads               88774953                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                143862                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq              3545348                       # Transaction distribution
system.iobus.trans_dist::ReadResp             3545348                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57726                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57726                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1644                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1644                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7066648                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      7110880                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3288                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3288                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                 7209436                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3533324                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total      3561720                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027856                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027856                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6576                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  6596152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              2378920                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                41500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 2000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              5419500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               921000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                40500                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                21000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            199977500                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy              507000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            11026500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           144387981                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1052000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           283491000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            31080000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy              979000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47579                       # number of replacements
system.iocache.tags.tagsinuse                0.099877                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47595                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5000697713509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.099877                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006242                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.006242                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428706                       # Number of tag accesses
system.iocache.tags.data_accesses              428706                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          914                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              914                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide          914                       # number of demand (read+write) misses
system.iocache.demand_misses::total               914                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          914                       # number of overall misses
system.iocache.overall_misses::total              914                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    126880276                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    126880276                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   3631346705                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   3631346705                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    126880276                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    126880276                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    126880276                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    126880276                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          914                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            914                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          914                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             914                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          914                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            914                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138818.682713                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 138818.682713                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 77725.742830                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 77725.742830                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138818.682713                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 138818.682713                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138818.682713                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 138818.682713                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           745                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   69                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.797101                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          756                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          756                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        27936                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        27936                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          756                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          756                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          756                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          756                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     89080276                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     89080276                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   2234546705                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2234546705                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     89080276                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     89080276                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     89080276                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     89080276                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.827133                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.827133                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.597945                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.597945                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.827133                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.827133                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.827133                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.827133                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 117831.052910                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79988.069337                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79988.069337                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 117831.052910                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 117831.052910                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   104604                       # number of replacements
system.l2c.tags.tagsinuse                64807.192442                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4639119                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   168682                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    27.502158                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   51005.596123                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.135096                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1646.370611                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4933.032602                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      515.170721                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1886.198863                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker     9.247587                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst      884.114832                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     3927.326006                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.778284                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.025122                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.075272                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.007861                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.028781                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000141                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.013491                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.059926                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.988879                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        64078                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          267                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2840                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6913                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54019                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.977753                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 41426818                       # Number of tag accesses
system.l2c.tags.data_accesses                41426818                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        20684                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker        10937                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        10806                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         5737                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        57360                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        12726                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 118250                       # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
system.l2c.WritebackDirty_hits::writebacks      1548077                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         1548077                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks       861736                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total          861736                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data             130                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              31                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data             113                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 274                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            69082                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            29187                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            61550                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               159819                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        315651                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        161179                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst        370786                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total            847616                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       512536                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       207467                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data       595550                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          1315553                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker         20684                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker         10939                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              315651                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              581618                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         10806                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5737                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              161179                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              236654                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         57360                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         12726                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              370786                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              657100                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2441240                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        20684                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker        10939                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             315651                       # number of overall hits
system.l2c.overall_hits::cpu0.data             581618                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        10806                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5737                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             161179                       # number of overall hits
system.l2c.overall_hits::cpu1.data             236654                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        57360                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        12726                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             370786                       # number of overall hits
system.l2c.overall_hits::cpu2.data             657100                       # number of overall hits
system.l2c.overall_hits::total                2441240                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           31                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                   36                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data           706                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           151                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           525                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1382                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          68319                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          24150                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          37534                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             130003                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         6941                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         2461                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst         5558                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           14960                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data        15417                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         4611                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data        12720                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          32748                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6941                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             83736                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2461                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             28761                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           31                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              5558                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             50254                       # number of demand (read+write) misses
system.l2c.demand_misses::total                177747                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6941                       # number of overall misses
system.l2c.overall_misses::cpu0.data            83736                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2461                       # number of overall misses
system.l2c.overall_misses::cpu1.data            28761                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           31                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             5558                       # number of overall misses
system.l2c.overall_misses::cpu2.data            50254                       # number of overall misses
system.l2c.overall_misses::total               177747                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      4350500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total        4350500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      6534500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data     19951500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     26486000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   3047020000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   4863369000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7910389000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    320798500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst    757296000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   1078094500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    606081000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data   1751621500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   2357702500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    320798500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   3653101000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      4350500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    757296000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   6614990500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     11350536500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    320798500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   3653101000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      4350500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    757296000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   6614990500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    11350536500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        20684                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        10942                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        10806                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         5737                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        57391                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        12726                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             118286                       # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      1548077                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      1548077                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks       861736                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total       861736                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data          836                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          182                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          638                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1656                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       137401                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        53337                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        99084                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           289822                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       322592                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       163640                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst       376344                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total        862576                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       527953                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       212078                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data       608270                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      1348301                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        20684                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        10944                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          322592                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          665354                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        10806                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5737                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          163640                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          265415                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        57391                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        12726                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          376344                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          707354                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2618987                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        20684                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        10944                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         322592                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         665354                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        10806                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5737                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         163640                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         265415                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        57391                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        12726                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         376344                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         707354                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2618987                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000457                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000540                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.000304                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.844498                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.829670                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.822884                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.834541                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.497223                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.452781                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.378810                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.448562                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.021516                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.015039                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.014768                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.017343                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.029201                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.021742                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.020912                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.024288                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000457                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.021516                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.125852                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.015039                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.108362                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000540                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.014768                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.071045                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.067869                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000457                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.021516                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.125852                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.015039                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.108362                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000540                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.014768                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.071045                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.067869                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 140338.709677                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 120847.222222                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 43274.834437                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 38002.857143                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 19164.978292                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126170.600414                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 129572.361059                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 60847.741975                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130352.905323                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 136253.328535                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 72065.140374                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131442.420299                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 137706.092767                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 71995.312691                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 130352.905323                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 127015.785265                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 140338.709677                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 136253.328535                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 131631.123891                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 63857.823198                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 130352.905323                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 127015.785265                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 140338.709677                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 136253.328535                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 131631.123891                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 63857.823198                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               96355                       # number of writebacks
system.l2c.writebacks::total                    96355                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           31                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total              31                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          151                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          525                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          676                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        24150                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        37534                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         61684                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         2461                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5557                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total         8018                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         4611                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data        12720                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        17331                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2461                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        28761                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           31                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         5557                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        50254                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            87064                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2461                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        28761                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           31                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         5557                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        50254                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           87064                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data       176326                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data       193522                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total       369848                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3494                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         2876                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total         6370                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data       179820                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data       196398                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       376218                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      4040500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total      4040500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     10668000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     37156500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     47824500                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2805520000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   4488029000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   7293549000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    296188500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    701637000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total    997825500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    559971000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1624421500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   2184392500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    296188500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3365491000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      4040500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    701637000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   6112450500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  10479807500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    296188500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3365491000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      4040500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    701637000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   6112450500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  10479807500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28471375500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30579722500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  59051098000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    633646000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    578928500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1212574500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  29105021500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31158651000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  60263672500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000540                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.000262                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.829670                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.822884                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.408213                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.452781                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.378810                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.212834                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.015039                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.014766                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.009295                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.021742                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.020912                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.012854                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.015039                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.108362                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000540                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014766                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.071045                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.033243                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.015039                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.108362                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000540                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014766                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.071045                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.033243                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 130338.709677                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70649.006623                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70774.285714                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70746.301775                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116170.600414                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119572.361059                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 118240.532391                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120352.905323                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126261.831924                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124448.179097                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121442.420299                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 127706.092767                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126039.611101                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120352.905323                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117015.785265                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126261.831924                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121631.123891                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 120369.010153                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120352.905323                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117015.785265                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126261.831924                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121631.123891                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 120369.010153                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161470.092329                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 158016.775870                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159663.153512                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181352.604465                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 201296.418637                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 190357.064364                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161856.420309                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158650.551431                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 160182.852761                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq             5063565                       # Transaction distribution
system.membus.trans_dist::ReadResp            5112222                       # Transaction distribution
system.membus.trans_dist::WriteReq              13898                       # Transaction distribution
system.membus.trans_dist::WriteResp             13898                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       143022                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8552                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             1672                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1672                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129713                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129713                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         48657                       # Transaction distribution
system.membus.trans_dist::MessageReq             1644                       # Transaction distribution
system.membus.trans_dist::MessageResp            1644                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3288                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3288                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7110880                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3044046                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       462447                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total     10617373                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141987                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141987                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               10762648                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6576                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3561720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6088089                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17501760                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     27151569                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3025152                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3025152                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                30183297                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              664                       # Total snoops (count)
system.membus.snoop_fanout::samples           5457993                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.000301                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.017353                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 5456349     99.97%     99.97% # Request fanout histogram
system.membus.snoop_fanout::2                    1644      0.03%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total             5457993                       # Request fanout histogram
system.membus.reqLayer0.occupancy           219248500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           286800000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             2377080                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy           547350354                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1398080                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1208209380                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           52355698                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.toL2Bus.snoop_filter.tot_requests      5045321                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2544604                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests          482                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           1171                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         1171                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq            5213952                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           7425084                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13900                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13900                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      1631207                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean       861736                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict           94941                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1656                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1656                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           289822                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          289822                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq        862602                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      1349057                       # Transaction distribution
system.toL2Bus.trans_dist::MessageReq             979                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        27936                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2586927                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15072185                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        70382                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       205946                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17935440                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    110356800                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213581265                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       259408                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       748104                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              324945577                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          226314                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          8918759                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.005043                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.070832                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                8873785     99.50%     99.50% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  44974      0.50%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            8918759                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         3217757998                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           405376                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         810539408                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1832719254                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          24003478                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          87328075                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------