path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.135764                       # Number of seconds simulated
sim_ticks                                5135763847500                       # Number of ticks simulated
final_tick                               5135763847500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 259782                       # Simulator instruction rate (inst/s)
host_op_rate                                   516376                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5470381356                       # Simulator tick rate (ticks/s)
host_mem_usage                                 959692                       # Number of bytes of host memory used
host_seconds                                   938.83                       # Real time elapsed on the host
sim_insts                                   243891279                       # Number of instructions simulated
sim_ops                                     484789360                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide      2442432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           470912                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          6169536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           114240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          1582592                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         2240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           379456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          2632640                       # Number of bytes read from this memory
system.physmem.bytes_read::total             13794368                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       470912                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       114240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       379456                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          964608                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9131520                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9131520                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        38163                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              7358                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             96399                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1785                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             24728                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           35                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              5929                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             41135                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                215537                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          142680                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               142680                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       475573                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               91693                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1201289                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               22244                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              308151                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           436                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               73885                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              512609                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2685943                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          91693                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          22244                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          73885                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             187822                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1778026                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1778026                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1778026                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       475573                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              91693                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1201289                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              22244                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             308151                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          436                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              73885                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             512609                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4463968                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         94056                       # Number of read requests accepted
system.physmem.writeReqs                        72760                       # Number of write requests accepted
system.physmem.readBursts                       94056                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      72760                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  6015488                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      4096                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4656640                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   6019584                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4656640                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       64                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            766                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                5609                       # Per bank write bursts
system.physmem.perBankRdBursts::1                5668                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5585                       # Per bank write bursts
system.physmem.perBankRdBursts::3                5594                       # Per bank write bursts
system.physmem.perBankRdBursts::4                6037                       # Per bank write bursts
system.physmem.perBankRdBursts::5                6612                       # Per bank write bursts
system.physmem.perBankRdBursts::6                5733                       # Per bank write bursts
system.physmem.perBankRdBursts::7                5990                       # Per bank write bursts
system.physmem.perBankRdBursts::8                5523                       # Per bank write bursts
system.physmem.perBankRdBursts::9                5460                       # Per bank write bursts
system.physmem.perBankRdBursts::10               5647                       # Per bank write bursts
system.physmem.perBankRdBursts::11               6128                       # Per bank write bursts
system.physmem.perBankRdBursts::12               6059                       # Per bank write bursts
system.physmem.perBankRdBursts::13               6267                       # Per bank write bursts
system.physmem.perBankRdBursts::14               6194                       # Per bank write bursts
system.physmem.perBankRdBursts::15               5886                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4545                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4402                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4127                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4299                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4675                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5126                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4327                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4679                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4360                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4207                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4528                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4822                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4836                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4641                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4944                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4242                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
system.physmem.totGap                    5131947184500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   94056                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  72760                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     71094                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4372                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2882                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1652                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      1622                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      1995                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1751                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1697                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1317                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       996                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      893                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      759                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      598                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      528                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      422                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      379                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      352                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      273                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      218                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      184                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1038                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2990                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     3405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     3645                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     3779                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4031                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4369                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4401                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4387                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4409                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1056                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1028                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1031                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      961                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      898                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      557                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      463                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      343                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        3                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        35723                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      298.746690                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     173.799684                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     327.095227                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14318     40.08%     40.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         8282     23.18%     63.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3507      9.82%     73.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1954      5.47%     78.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1307      3.66%     82.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          922      2.58%     84.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          623      1.74%     86.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          530      1.48%     88.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4280     11.98%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          35723                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          3978                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        23.627954                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      119.433357                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-255            3969     99.77%     99.77% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-511             7      0.18%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-2815            1      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6656-6911            1      0.03%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            3978                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          3978                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.290598                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.208175                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.685696                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-1                45      1.13%      1.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2-3                 5      0.13%      1.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-5                 3      0.08%      1.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6-7                 4      0.10%      1.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::10-11               1      0.03%      1.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::14-15               5      0.13%      1.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            2627     66.04%     67.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19             818     20.56%     88.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              28      0.70%     88.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              32      0.80%     89.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              32      0.80%     90.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              35      0.88%     91.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29              65      1.63%     93.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31              48      1.21%     94.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33              35      0.88%     95.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35              29      0.73%     95.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37              29      0.73%     96.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39              26      0.65%     97.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41              31      0.78%     97.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43              18      0.45%     98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45              10      0.25%     98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47              17      0.43%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49               8      0.20%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51               6      0.15%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53               2      0.05%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54-55               2      0.05%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-57               7      0.18%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59               1      0.03%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-61               3      0.08%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::62-63               4      0.10%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::66-67               2      0.05%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            3978                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2424873249                       # Total ticks spent queuing
system.physmem.totMemAccLat                4187223249                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    469960000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25798.72                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44548.72                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.17                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.91                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.17                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.91                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         6.97                       # Average write queue length when enqueuing
system.physmem.readRowHits                      76538                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     54491                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.43                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.89                       # Row buffer hit rate for writes
system.physmem.avgGap                     30764118.46                       # Average gap between requests
system.physmem.pageHitRate                      78.58                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     4942425043001                       # Time in different power states
system.physmem.memoryStateTime::REF      171494180000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       21844559499                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                      6452408                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              421921                       # Transaction distribution
system.membus.trans_dist::ReadResp             421919                       # Transaction distribution
system.membus.trans_dist::WriteReq               5915                       # Transaction distribution
system.membus.trans_dist::WriteResp              5915                       # Transaction distribution
system.membus.trans_dist::Writeback             72760                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              778                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             778                       # Transaction distribution
system.membus.trans_dist::ReadExReq             75224                       # Transaction distribution
system.membus.trans_dist::ReadExResp            75224                       # Transaction distribution
system.membus.trans_dist::MessageReq              825                       # Transaction distribution
system.membus.trans_dist::MessageResp             825                       # Transaction distribution
system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         1650                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         1650                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       308134                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio       497586                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       196326                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      1002050                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72232                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72232                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1075932                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         3300                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total         3300                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       157715                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio       995169                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      7734720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total      8887604                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2941504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      2941504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            11832408                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               32744958                       # Total data (bytes)
system.membus.snoop_data_through_bus           393088                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           161596500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           315113000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1650000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy           794070497                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                2000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy             825000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1569908183                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy          236956000                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   104346                       # number of replacements
system.l2c.tags.tagsinuse                64811.945905                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3669840                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   168730                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    21.749778                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   51276.768453                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.121941                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1221.298902                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4234.138382                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.002961                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      249.507225                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1581.676468                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker     7.253356                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1493.843089                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     4747.335130                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.782421                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.018636                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.064608                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.003807                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.024134                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000111                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.022794                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.072439                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.988952                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        64384                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          269                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2861                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         7799                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53379                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.982422                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 33692585                       # Number of tag accesses
system.l2c.tags.data_accesses                33692585                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        19944                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker        10836                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             348846                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             522725                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         9533                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         5021                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             144714                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             221166                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        56163                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        10079                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             347465                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             563204                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2259696                       # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
system.l2c.Writeback_hits::writebacks         1546042                       # number of Writeback hits
system.l2c.Writeback_hits::total              1546042                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             139                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              47                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              73                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 259                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            69718                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            41748                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            55006                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               166472                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         19944                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker         10838                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              348846                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              592443                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          9533                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5021                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              144714                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              262914                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         56163                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         10079                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              347465                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              618210                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2426170                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        19944                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker        10838                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             348846                       # number of overall hits
system.l2c.overall_hits::cpu0.data             592443                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         9533                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5021                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             144714                       # number of overall hits
system.l2c.overall_hits::cpu1.data             262914                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        56163                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        10079                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             347465                       # number of overall hits
system.l2c.overall_hits::cpu2.data             618210                       # number of overall hits
system.l2c.overall_hits::total                2426170                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7359                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data            16415                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1785                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4252                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           35                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             5929                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data            12239                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                48019                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data           765                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           259                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           351                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1375                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          80419                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          20642                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          29214                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             130275                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7359                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             96834                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1785                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             24894                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           35                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              5929                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             41453                       # number of demand (read+write) misses
system.l2c.demand_misses::total                178294                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7359                       # number of overall misses
system.l2c.overall_misses::cpu0.data            96834                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1785                       # number of overall misses
system.l2c.overall_misses::cpu1.data            24894                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           35                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             5929                       # number of overall misses
system.l2c.overall_misses::cpu2.data            41453                       # number of overall misses
system.l2c.overall_misses::total               178294                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    131076749                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    324093246                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      2710500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    449940247                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data    930919976                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1838815218                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      3606379                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data      3766341                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      7372720                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1430517449                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   2081702090                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   3512219539                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        74500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    131076749                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1754610695                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      2710500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    449940247                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   3012622066                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      5351034757                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        74500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    131076749                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1754610695                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      2710500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    449940247                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   3012622066                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     5351034757                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        19944                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        10840                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         356205                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         539140                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         9533                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         5022                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         146499                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         225418                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        56198                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        10079                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         353394                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         575443                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2307715                       # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1546042                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1546042                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data          904                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          306                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          424                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1634                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       150137                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        62390                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        84220                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296747                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        19944                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        10842                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          356205                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          689277                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         9533                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5022                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          146499                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          287808                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        56198                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        10079                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          353394                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          659663                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2604464                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        19944                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        10842                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         356205                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         689277                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         9533                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5022                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         146499                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         287808                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        56198                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        10079                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         353394                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         659663                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2604464                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000369                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.020659                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.030447                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000199                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.012184                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.018863                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000623                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.016777                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.021269                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.020808                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.846239                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.846405                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.827830                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.841493                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.535637                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.330854                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.346877                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.439010                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000369                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.020659                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.140486                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000199                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.012184                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.086495                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000623                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.016777                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.062840                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.068457                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000369                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.020659                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.140486                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000199                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.012184                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.086495                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000623                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.016777                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.062840                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.068457                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73432.352381                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76221.365475                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 77442.857143                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75888.049755                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 76061.767791                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 38293.492534                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 13924.243243                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 10730.316239                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  5361.978182                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69301.300698                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71257.003149                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 26960.042518                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 73432.352381                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 70483.276894                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 77442.857143                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 75888.049755                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 72675.610113                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 30012.421938                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 73432.352381                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 70483.276894                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 77442.857143                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 75888.049755                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 72675.610113                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 30012.421938                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               96013                       # number of writebacks
system.l2c.writebacks::total                    96013                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1785                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4252                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           35                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         5929                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data        12239                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           24241                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          259                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          351                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          610                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        20642                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        29214                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         49856                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1785                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        24894                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           35                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         5929                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        41453                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            74097                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1785                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        24894                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           35                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         5929                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        41453                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           74097                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    108413751                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    270880754                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2276000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    375699253                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    777979024                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1535311282                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      3140248                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      3570349                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      6710597                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1166132051                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1707521864                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2873653915                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    108413751                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1437012805                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      2276000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    375699253                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   2485500888                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   4408965197                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    108413751                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1437012805                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2276000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    375699253                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   2485500888                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   4408965197                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28030608000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30401443000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  58432051000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    366838500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    681386000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1048224500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28397446500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31082829000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  59480275500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000199                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.012184                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.018863                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000623                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.016777                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.021269                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.010504                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.846405                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.827830                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.373317                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.330854                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.346877                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.168008                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000199                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.012184                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.086495                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000623                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.016777                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.062840                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.028450                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000199                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.012184                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.086495                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000623                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.016777                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.062840                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.028450                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60735.994958                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63706.668391                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 65028.571429                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63366.377635                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63565.571043                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 63335.311332                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12124.509653                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10171.934473                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11000.978689                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56493.171737                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58448.752790                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 57639.078847                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60735.994958                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57725.267333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 65028.571429                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63366.377635                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59959.493595                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59502.614100                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60735.994958                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57725.267333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 65028.571429                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63366.377635                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59959.493595                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59502.614100                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                47573                       # number of replacements
system.iocache.tags.tagsinuse                0.095086                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47589                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5000199085509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.095086                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005943                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.005943                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428652                       # Number of tag accesses
system.iocache.tags.data_accesses              428652                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          908                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              908                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47628                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47628                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47628                       # number of overall misses
system.iocache.overall_misses::total            47628                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    130701291                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    130701291                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6017123258                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   6017123258                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide   6147824549                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   6147824549                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide   6147824549                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   6147824549                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          908                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            908                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47628                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47628                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47628                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47628                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 143944.153084                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 143944.153084                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 128791.165625                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 128791.165625                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 129080.048480                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 129080.048480                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 129080.048480                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 129080.048480                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         86048                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7909                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.879757                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          735                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          735                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        25536                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        25536                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        26271                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        26271                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        26271                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        26271                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     92456791                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     92456791                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4688241758                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   4688241758                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4780698549                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   4780698549                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4780698549                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   4780698549                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.809471                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.809471                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide     0.546575                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total     0.546575                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.551587                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.551587                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.551587                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.551587                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125791.552381                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 125791.552381                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 183593.427240                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 183593.427240                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 181976.268471                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 181976.268471                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.toL2Bus.throughput                    52407719                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            1793633                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           1793101                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq              5915                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp             5915                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           899960                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             730                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            730                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           172146                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          146613                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       999818                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3602290                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        34349                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       141650                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               4778107                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     31993152                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    119401652                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       120808                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       525848                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          152041460                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             269011854                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus          141816                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         5025953302                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           936000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2251918114                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4677619434                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          19272449                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          76057203                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                       1276582                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq               149714                       # Transaction distribution
system.iobus.trans_dist::ReadResp              149714                       # Transaction distribution
system.iobus.trans_dist::WriteReq               30624                       # Transaction distribution
system.iobus.trans_dist::WriteResp              30624                       # Transaction distribution
system.iobus.trans_dist::MessageReq               825                       # Transaction distribution
system.iobus.trans_dist::MessageResp              825                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio         4890                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio          588                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           18                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       287208                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio          156                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        13026                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2064                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       308134                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        52542                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        52542                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         1650                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         1650                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  362326                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         2760                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf            4                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          294                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           12                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio            9                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       143604                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio          312                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio         6513                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            2                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4128                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       157715                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      1670648                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      1670648                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3300                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         3300                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              1831663                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 6556225                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              1987954                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                28000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 2000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              4046000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 1000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               387000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                21000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            143605000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy              124000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy               86000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy             9774000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                4000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           232428549                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1032000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           303046000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            31488000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy              825000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
system.cpu0.numCycles                      1167096017                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   72932334                       # Number of instructions committed
system.cpu0.committedOps                    148186849                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            136173063                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                    1014433                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     14332221                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   136173063                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads          250637191                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         116800630                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            84487712                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           56367816                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     14369378                       # number of memory refs
system.cpu0.num_load_insts                   10451844                       # Number of load instructions
system.cpu0.num_store_insts                   3917534                       # Number of store instructions
system.cpu0.num_idle_cycles              1108227141.183960                       # Number of idle cycles
system.cpu0.num_busy_cycles              58868875.816040                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.050440                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.949560                       # Percentage of idle cycles
system.cpu0.Branches                         15712912                       # Number of branches fetched
system.cpu0.op_class::No_OpClass               100385      0.07%      0.07% # Class of executed instruction
system.cpu0.op_class::IntAlu                133601927     90.16%     90.23% # Class of executed instruction
system.cpu0.op_class::IntMult                   62763      0.04%     90.27% # Class of executed instruction
system.cpu0.op_class::IntDiv                    53014      0.04%     90.30% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.30% # Class of executed instruction
system.cpu0.op_class::MemRead                10451844      7.05%     97.36% # Class of executed instruction
system.cpu0.op_class::MemWrite                3917534      2.64%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 148187467                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           855609                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.820181                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          129797062                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           856121                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           151.610651                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle     147456803500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   296.387192                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   131.510981                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    82.922008                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.578881                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.256857                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.161957                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997696                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          116                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        131529533                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       131529533                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     88736608                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     38254506                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      2805948                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      129797062                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     88736608                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     38254506                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      2805948                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       129797062                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     88736608                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     38254506                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      2805948                       # number of overall hits
system.cpu0.icache.overall_hits::total      129797062                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       356206                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       146499                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       373635                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       876340                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       356206                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       146499                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       373635                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        876340                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       356206                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       146499                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       373635                       # number of overall misses
system.cpu0.icache.overall_misses::total       876340                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2025173751                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5266260197                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   7291433948                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2025173751                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   5266260197                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   7291433948                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2025173751                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   5266260197                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   7291433948                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     89092814                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     38401005                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      3179583                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    130673402                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     89092814                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     38401005                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      3179583                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    130673402                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     89092814                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     38401005                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      3179583                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    130673402                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003998                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.003815                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.117511                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.006706                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003998                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.003815                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.117511                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.006706                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003998                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.003815                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.117511                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.006706                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13823.805971                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14094.665106                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8320.325385                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13823.805971                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14094.665106                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8320.325385                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13823.805971                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14094.665106                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8320.325385                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3206                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              169                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.970414                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        20209                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        20209                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        20209                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        20209                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        20209                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        20209                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       146499                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       353426                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       499925                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       146499                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       353426                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       499925                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       146499                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       353426                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       499925                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1731523249                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4361398381                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   6092921630                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1731523249                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4361398381                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   6092921630                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1731523249                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4361398381                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   6092921630                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.003815                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.111155                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.003826                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.003815                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.111155                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.003826                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.003815                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.111155                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.003826                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11819.352002                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12340.343894                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12187.671411                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11819.352002                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12340.343894                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12187.671411                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11819.352002                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12340.343894                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12187.671411                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          1636191                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999281                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           19675203                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1636703                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            12.021242                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   273.563820                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   233.097338                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.338124                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.534304                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.455268                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.010426                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          210                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          278                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88326830                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88326830                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5302140                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      2350453                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      3934991                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11587584                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3761995                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1605612                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2718349                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       8085956                       # number of WriteReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9064135                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      3956065                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      6653340                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        19673540                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9064135                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      3956065                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      6653340                       # number of overall hits
system.cpu0.dcache.overall_hits::total       19673540                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       539140                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       225418                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       918731                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1683289                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       151041                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        62696                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       101955                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       315692                       # number of WriteReq misses
system.cpu0.dcache.demand_misses::cpu0.data       690181                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       288114                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1020686                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1998981                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       690181                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       288114                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1020686                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1998981                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3220560254                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  14575132809                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  17795693063                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2058114299                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3117330338                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   5175444637                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   5278674553                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  17692463147                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  22971137700                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   5278674553                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  17692463147                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  22971137700                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5841280                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      2575871                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4853722                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     13270873                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3913036                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1668308                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      2820304                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      8401648                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      9754316                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      4244179                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7674026                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     21672521                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      9754316                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      4244179                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      7674026                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     21672521                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.092298                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.087511                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.189284                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.126841                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.038599                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.037581                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.036150                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.037575                       # miss rate for WriteReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.070756                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.067885                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.133005                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.092236                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.070756                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.067885                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.133005                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.092236                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14287.058948                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15864.418213                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10571.977280                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32826.883677                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30575.551351                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 16393.968289                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18321.478835                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17333.894211                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 11491.423730                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18321.478835                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17333.894211                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 11491.423730                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        80099                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            18060                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     4.435161                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      1546042                       # number of writebacks
system.cpu0.dcache.writebacks::total          1546042                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       343252                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       343252                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        17347                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        17347                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       360599                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       360599                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       360599                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       360599                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       225418                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       575479                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       800897                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        62696                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        84608                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       147304                       # number of WriteReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       288114                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       660087                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       948201                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       288114                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       660087                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       948201                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2768607746                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   8066658535                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  10835266281                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1923226701                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2756691504                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4679918205                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4691834447                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  10823350039                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  15515184486                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4691834447                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  10823350039                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  15515184486                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30492689000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33165040000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63657729000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    394150500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    725206000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1119356500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  30886839500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33890246000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64777085500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.087511                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.118564                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.060350                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.037581                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.030000                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017533                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.067885                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.086016                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.043751                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.067885                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.086016                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.043751                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12282.105892                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14017.294350                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13528.913557                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30675.429070                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32581.924924                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31770.476056                       # average WriteReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16284.645824                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16396.853807                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16362.759042                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16284.645824                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16396.853807                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16362.759042                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                      2604023259                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   34762499                       # Number of instructions committed
system.cpu1.committedOps                     67606793                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             62736553                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     437056                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      6403696                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    62736553                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads          115724590                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          54164636                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            35537675                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           26584960                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      4433444                       # number of memory refs
system.cpu1.num_load_insts                    2764122                       # Number of load instructions
system.cpu1.num_store_insts                   1669322                       # Number of store instructions
system.cpu1.num_idle_cycles              2476870816.288117                       # Number of idle cycles
system.cpu1.num_busy_cycles              127152442.711883                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.048829                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.951171                       # Percentage of idle cycles
system.cpu1.Branches                          7001569                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                28648      0.04%      0.04% # Class of executed instruction
system.cpu1.op_class::IntAlu                 63095899     93.33%     93.37% # Class of executed instruction
system.cpu1.op_class::IntMult                   28577      0.04%     93.41% # Class of executed instruction
system.cpu1.op_class::IntDiv                    20525      0.03%     93.44% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.44% # Class of executed instruction
system.cpu1.op_class::MemRead                 2764122      4.09%     97.53% # Class of executed instruction
system.cpu1.op_class::MemWrite                1669322      2.47%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  67607093                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups               28894520                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         28894520                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           314484                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            26386768                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               25807983                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            97.806533                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 541788                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             61672                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                       154118891                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles           9526926                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                     142222809                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   28894520                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          26349771                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                     54464711                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                1558370                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                     64917                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.BlockedCycles              23183087                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                4981                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             6096                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        25004                       # Number of stall cycles due to pending traps
system.cpu2.fetch.IcacheWaitRetryStallCycles          241                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  3179586                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               151181                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   1925                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples          88503258                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             3.167922                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            3.413230                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                34173678     38.61%     38.61% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  596420      0.67%     39.29% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                23721602     26.80%     66.09% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  320974      0.36%     66.45% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  619988      0.70%     67.15% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  815233      0.92%     68.07% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  353145      0.40%     68.47% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  523827      0.59%     69.07% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                27378391     30.93%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            88503258                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.187482                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.922812                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                10770329                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             22316529                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 33210052                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles               993418                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles               1230628                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts             279539625                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts                   15                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles               1230628                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                11632631                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               11620518                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       4366536                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 33251587                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles              6419117                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts             278526444                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents               145793                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents               2942087                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                 39888                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               2722851                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands          332982462                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            606515542                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       372413837                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups               42                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps            321866415                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                11116047                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            145000                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        146469                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  9034946                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6263244                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3375371                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           381006                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          309187                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                 276743563                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             411647                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                274777165                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            83308                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        7862427                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     12385425                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved         57804                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     88503258                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        3.104712                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       2.400001                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           25772149     29.12%     29.12% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            5479119      6.19%     35.31% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            3780646      4.27%     39.58% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            2658058      3.00%     42.59% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4           25098242     28.36%     70.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5            1415095      1.60%     72.54% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6           23897363     27.00%     99.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             310729      0.35%     99.90% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8              91857      0.10%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       88503258                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                 130084     34.74%     34.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     34.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                    103      0.03%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     34.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                196279     52.42%     87.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                48005     12.82%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            79957      0.03%      0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu            264964709     96.43%     96.46% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               54296      0.02%     96.48% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                50937      0.02%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.50% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             6495012      2.36%     98.86% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3132254      1.14%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total             274777165                       # Type of FU issued
system.cpu2.iq.rate                          1.782891                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                     374471                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001363                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         638559252                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes        285021199                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses    273394851                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                 45                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                74                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses           14                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses             275071659                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                     20                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          655974                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1102337                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         6308                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         4079                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       550460                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads       656385                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked         7890                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles               1230628                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                6003858                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles              2680102                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts          277155210                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            55656                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6263266                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3375371                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            233323                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                631738                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents              1840063                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          4079                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        177700                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       182074                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              359774                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts            274266101                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              6377623                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           511064                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
system.cpu2.iew.exec_refs                     9440682                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                27899539                       # Number of branches executed
system.cpu2.iew.exec_stores                   3063059                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.779575                       # Inst execution rate
system.cpu2.iew.wb_sent                     274107922                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                    273394865                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                213810949                       # num instructions producing a value
system.cpu2.iew.wb_consumers                349940477                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.773922                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.610992                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        8157845                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         353843                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           317282                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     87272630                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     3.082246                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.874009                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     30201439     34.61%     34.61% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4017102      4.60%     39.21% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1154677      1.32%     40.53% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3     24628965     28.22%     68.75% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       905267      1.04%     69.79% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       589610      0.68%     70.47% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       344278      0.39%     70.86% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7     23302755     26.70%     97.56% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      2128537      2.44%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     87272630                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts           136196446                       # Number of instructions committed
system.cpu2.commit.committedOps             268995718                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       7985840                       # Number of memory references committed
system.cpu2.commit.loads                      5160929                       # Number of loads committed
system.cpu2.commit.membars                     163767                       # Number of memory barriers committed
system.cpu2.commit.branches                  27540439                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                245590309                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              428081                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        46387      0.02%      0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu       260861796     96.98%     96.99% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          52266      0.02%     97.01% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv           49429      0.02%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.03% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        5160929      1.92%     98.95% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       2824911      1.05%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total        268995718                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              2128537                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                   362270810                       # The number of ROB reads
system.cpu2.rob.rob_writes                  555542201                       # The number of ROB writes
system.cpu2.timesIdled                         475518                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                       65615633                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  4908375985                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                  136196446                       # Number of Instructions Simulated
system.cpu2.committedOps                    268995718                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.131593                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.131593                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.883710                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.883710                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               364616127                       # number of integer regfile reads
system.cpu2.int_regfile_writes              219111496                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    72926                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   72912                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                139466740                       # number of cc regfile reads
system.cpu2.cc_regfile_writes               107376389                       # number of cc regfile writes
system.cpu2.misc_regfile_reads               88828545                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                129118                       # number of misc regfile writes
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------