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|
{
"name": null,
"sim_quantum": 0,
"system": {
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"mmap_using_noreserve": false,
"kernel_addr_check": true,
"rom": {
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"latency": 60,
"name": "rom",
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"default_p_state": "UNDEFINED",
"clk_domain": "system.clk_domain",
"power_model": null,
"latency_var": 0,
"bandwidth": "0.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
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"path": "system.rom",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[3]",
"role": "SLAVE"
},
"in_addr_map": true
},
"bridge": {
"ranges": [
"133412421632:133412421639",
"134217728000:554050781183",
"644245094400:652835028991",
"725849473024:1095485095935",
"1099255955456:1099255955463"
],
"slave": {
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},
"name": "bridge",
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"cxx_class": "Bridge",
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"delay": 100,
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"master": {
"peer": "system.iobus.slave[0]",
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},
"default_p_state": "UNDEFINED",
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"path": "system.bridge",
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},
"iobus": {
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],
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},
"name": "iobus",
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"width": 16,
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"master": {
"peer": [
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"system.t1000.fake_membnks.pio",
"system.t1000.fake_l2_1.pio",
"system.t1000.fake_l2_2.pio",
"system.t1000.fake_l2_3.pio",
"system.t1000.fake_l2_4.pio",
"system.t1000.fake_l2esr_1.pio",
"system.t1000.fake_l2esr_2.pio",
"system.t1000.fake_l2esr_3.pio",
"system.t1000.fake_l2esr_4.pio",
"system.t1000.fake_ssi.pio",
"system.t1000.fake_jbi.pio",
"system.t1000.puart0.pio",
"system.t1000.hvuart.pio",
"system.disk0.pio"
],
"role": "MASTER"
},
"response_latency": 2,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 2000000000,
"path": "system.iobus",
"type": "NoncoherentXBar",
"use_default_range": false,
"frontend_latency": 2
},
"t1000": {
"htod": {
"name": "htod",
"p_state_clk_gate_min": 2,
"pio": {
"peer": "system.membus.master[1]",
"role": "SLAVE"
},
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"cxx_class": "DumbTOD",
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"clk_domain": "system.clk_domain",
"power_model": null,
"system": "system",
"eventq_index": 0,
"time": "Thu Jan 1 00:00:00 2009",
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 2000000000,
"path": "system.t1000.htod",
"pio_addr": 1099255906296,
"type": "DumbTOD"
},
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"pio": {
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},
"p_state_clk_gate_bins": 20,
"cxx_class": "Uart8250",
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"clk_domain": "system.clk_domain",
"power_model": null,
"system": "system",
"terminal": "system.t1000.pterm",
"platform": "system.t1000",
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 2000000000,
"path": "system.t1000.puart0",
"pio_addr": 133412421632,
"type": "Uart8250"
},
"fake_membnks": {
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},
"ret_data64": 0,
"fake_mem": false,
"clk_domain": "system.clk_domain",
"cxx_class": "IsaFake",
"pio_addr": 648540061696,
"update_data": false,
"warn_access": "",
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"p_state_clk_gate_max": 2000000000,
"type": "IsaFake",
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"ret_data32": 4294967295,
"path": "system.t1000.fake_membnks",
"ret_data16": 65535,
"ret_data8": 255,
"name": "fake_membnks",
"ret_bad_addr": false,
"pio_size": 16384,
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},
"cxx_class": "T1000",
"fake_jbi": {
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},
"ret_data64": 18446744073709551615,
"fake_mem": false,
"clk_domain": "system.clk_domain",
"cxx_class": "IsaFake",
"pio_addr": 549755813888,
"update_data": false,
"warn_access": "",
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"system": "system",
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"type": "IsaFake",
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"path": "system.t1000.fake_jbi",
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"name": "fake_jbi",
"ret_bad_addr": false,
"pio_size": 4294967296,
"p_state_clk_gate_bins": 20
},
"intrctrl": "system.intrctrl",
"fake_l2esr_2": {
"pio": {
"peer": "system.iobus.master[7]",
"role": "SLAVE"
},
"ret_data64": 0,
"fake_mem": false,
"clk_domain": "system.clk_domain",
"cxx_class": "IsaFake",
"pio_addr": 734439407680,
"update_data": true,
"warn_access": "",
"pio_latency": 200,
"system": "system",
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"type": "IsaFake",
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"path": "system.t1000.fake_l2esr_2",
"ret_data16": 65535,
"ret_data8": 255,
"name": "fake_l2esr_2",
"ret_bad_addr": false,
"pio_size": 8,
"p_state_clk_gate_bins": 20
},
"system": "system",
"eventq_index": 0,
"hterm": {
"name": "hterm",
"output": true,
"number": 0,
"intr_control": "system.intrctrl",
"eventq_index": 0,
"cxx_class": "Terminal",
"path": "system.t1000.hterm",
"type": "Terminal",
"port": 3456
},
"type": "T1000",
"fake_l2_4": {
"pio": {
"peer": "system.iobus.master[5]",
"role": "SLAVE"
},
"ret_data64": 1,
"fake_mem": false,
"clk_domain": "system.clk_domain",
"cxx_class": "IsaFake",
"pio_addr": 725849473216,
"update_data": true,
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"path": "system.t1000.fake_l2_4",
"ret_data16": 65535,
"ret_data8": 255,
"name": "fake_l2_4",
"ret_bad_addr": false,
"pio_size": 8,
"p_state_clk_gate_bins": 20
},
"fake_l2_1": {
"pio": {
"peer": "system.iobus.master[2]",
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},
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"fake_mem": false,
"clk_domain": "system.clk_domain",
"cxx_class": "IsaFake",
"pio_addr": 725849473024,
"update_data": true,
"warn_access": "",
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"path": "system.t1000.fake_l2_1",
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"ret_data8": 255,
"name": "fake_l2_1",
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"pio_size": 8,
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},
"fake_l2_2": {
"pio": {
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},
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"clk_domain": "system.clk_domain",
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"pio_addr": 725849473088,
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"path": "system.t1000.fake_l2_2",
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"name": "fake_l2_2",
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"pio_size": 8,
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},
"fake_l2_3": {
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},
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},
"pterm": {
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"number": 0,
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"cxx_class": "Terminal",
"path": "system.t1000.pterm",
"type": "Terminal",
"port": 3456
},
"path": "system.t1000",
"iob": {
"name": "iob",
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"pio": {
"peer": "system.membus.master[0]",
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},
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"cxx_class": "Iob",
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"system": "system",
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"default_p_state": "UNDEFINED",
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"path": "system.t1000.iob",
"type": "Iob"
},
"hvuart": {
"name": "hvuart",
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"pio": {
"peer": "system.iobus.master[13]",
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},
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"system": "system",
"terminal": "system.t1000.hterm",
"platform": "system.t1000",
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"path": "system.t1000.hvuart",
"pio_addr": 1099255955456,
"type": "Uart8250"
},
"name": "t1000",
"fake_l2esr_3": {
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},
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"cxx_class": "IsaFake",
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"update_data": true,
"warn_access": "",
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"path": "system.t1000.fake_l2esr_3",
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"name": "fake_l2esr_3",
"ret_bad_addr": false,
"pio_size": 8,
"p_state_clk_gate_bins": 20
},
"fake_ssi": {
"pio": {
"peer": "system.iobus.master[10]",
"role": "SLAVE"
},
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