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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.269731 # Number of seconds simulated
sim_ticks 269730745500 # Number of ticks simulated
final_tick 269730745500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 168515 # Simulator instruction rate (inst/s)
host_op_rate 168515 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 75522303 # Simulator tick rate (ticks/s)
host_mem_usage 218132 # Number of bytes of host memory used
host_seconds 3571.54 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1628992 # Number of bytes read from this memory
system.physmem.bytes_read::total 1682816 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 64896 # Number of bytes written to this memory
system.physmem.bytes_written::total 64896 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 25453 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 199547 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 6039326 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6238873 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 199547 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 199547 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 240595 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 240595 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 240595 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 199547 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6039326 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6479469 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 26294 # Total number of read requests seen
system.physmem.writeReqs 1014 # Total number of write requests seen
system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1682816 # Total number of bytes read from memory
system.physmem.bytesWritten 64896 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1682816 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1718 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1732 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1568 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1581 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1708 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1632 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1673 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1665 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1558 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1618 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1600 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1550 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1652 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1697 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1675 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 76 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 51 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 81 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 53 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 58 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 74 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 269730693500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 26294 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 1014 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 17613 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 6143 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1651 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 360576187 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 1020404187 # Sum of mem lat for all requests
system.physmem.totBusLat 105120000 # Total cycles spent in databus access
system.physmem.totBankLat 554708000 # Total cycles spent in bank access
system.physmem.avgQLat 13720.56 # Average queueing delay per request
system.physmem.avgBankLat 21107.61 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 38828.17 # Average memory access latency
system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 12.19 # Average write queue length over time
system.physmem.readRowHits 17405 # Number of row buffer hits during reads
system.physmem.writeRowHits 51 # Number of row buffer hits during writes
system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes
system.physmem.avgGap 9877350.72 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114517567 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114520198 # DTB read accesses
system.cpu.dtb.write_hits 39453373 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39455675 # DTB write accesses
system.cpu.dtb.data_hits 153970940 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 153975873 # DTB accesses
system.cpu.itb.fetch_hits 25065868 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 25065890 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 539461492 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 86297721 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 81352852 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 36357676 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 52914836 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 34319624 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 64.858226 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 36896934 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49400787 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541636673 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1005491519 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 254989713 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 155053642 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 33759621 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2593068 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36352689 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 26195221 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.119750 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 412334808 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 535900413 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 295985 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 50743768 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 488717724 # Number of cycles cpu stages are processed.
system.cpu.activity 90.593626 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed
system.cpu.comNops 36304520 # Number of Nop instructions committed
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
system.cpu.comInts 349039879 # Number of Integer instructions committed
system.cpu.comFloats 24 # Number of Floating Point instructions committed
system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
system.cpu.cpi 0.896328 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.896328 # CPI: Total CPI of All Threads
system.cpu.ipc 1.115663 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.115663 # IPC: Total IPC of All Threads
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system.cpu.stage0.runCycles 338763300 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 62.796568 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 228822575 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310638917 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 57.583149 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.runCycles 341595727 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 63.321615 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.runCycles 111387652 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.647934 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.runCycles 346809882 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.288163 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements
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system.cpu.icache.occ_percent::total 0.355998 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::total 25064833 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25064833 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25064833 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::total 25064833 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 1035 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 1035 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 1035 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 52854000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 52854000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 52854000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 52854000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 52854000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 25065868 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 25065868 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 25065868 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51066.666667 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 51066.666667 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 51066.666667 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 51066.666667 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 180 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 180 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 43286500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43286500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 43286500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43286500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 43286500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50627.485380 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50627.485380 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency
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system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.WriteReq_hits::total 37665413 # number of WriteReq hits
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system.cpu.dcache.overall_hits::total 151786041 # number of overall hits
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system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses
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system.cpu.dcache.overall_misses::total 2179322 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 5991589500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 22875440000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 28867029500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 28867029500 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15229.731275 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15229.731275 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12808.856895 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 12808.856895 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 13245.876240 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13245.876240 # average overall miss latency
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system.cpu.dcache.blocked::no_mshrs 5600 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 60.444444 # average number of cycles each access was blocked
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system.cpu.dcache.writebacks::total 436887 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531745 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1531745 # number of WriteReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645854500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 3731128500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 6376983000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13148.279101 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13148.279101 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14680.061614 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14680.061614 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1042 # number of replacements
system.cpu.l2cache.tagsinuse 22878.552216 # Cycle average of tags in use
system.cpu.l2cache.total_refs 531848 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.846686 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21684.756059 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.inst 0.021918 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::total 436887 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 232860 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 232860 # number of ReadExReq hits
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system.cpu.l2cache.overall_hits::cpu.data 429942 # number of overall hits
system.cpu.l2cache.overall_hits::total 429956 # number of overall hits
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system.cpu.l2cache.ReadExReq_misses::total 21328 # number of ReadExReq misses
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system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses
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system.cpu.l2cache.Writeback_accesses::total 436887 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020501 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.024577 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083906 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083906 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055892 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.057631 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50274.078478 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114589.454545 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 103697.543294 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53773.912228 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53773.912228 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 63202.707842 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 63202.707842 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1014 # number of writebacks
system.cpu.l2cache.writebacks::total 1014 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 841 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4125 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4966 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21328 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21328 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 841 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 25453 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26294 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31666859 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 419253922 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450920781 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 877062534 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 877062534 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31666859 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1296316456 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1327983315 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31666859 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1296316456 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1327983315 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083906 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37653.815696 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101637.314424 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90801.607128 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41122.586928 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41122.586928 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
