blob: cd0e43aa804f4ff0f62755403ae7957c26c6c71c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.762398 # Number of seconds simulated
sim_ticks 762397656000 # Number of ticks simulated
final_tick 762397656000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1514073 # Simulator instruction rate (inst/s)
host_op_rate 1514073 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1917939864 # Simulator tick rate (ticks/s)
host_mem_usage 219440 # Number of bytes of host memory used
host_seconds 397.51 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1620160 # Number of bytes read from this memory
system.physmem.bytes_read::total 1670272 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 56512 # Number of bytes written to this memory
system.physmem.bytes_written::total 56512 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 25315 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory
system.physmem.num_writes::total 883 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 65729 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2125085 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2190815 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 65729 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 65729 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 74124 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 74124 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 74124 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2125085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2264939 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114514042 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.write_hits 39451321 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
system.cpu.dtb.data_hits 153965363 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 153970296 # DTB accesses
system.cpu.itb.fetch_hits 601861898 # ITB hits
system.cpu.itb.fetch_misses 20 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 601861918 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 1524795312 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 601856964 # Number of instructions committed
system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls
system.cpu.num_int_insts 563959696 # number of integer instructions
system.cpu.num_fp_insts 1520 # number of float instructions
system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read
system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written
system.cpu.num_fp_register_reads 169 # number of times the floating registers were read
system.cpu.num_fp_register_writes 42 # number of times the floating registers were written
system.cpu.num_mem_refs 153970296 # number of memory refs
system.cpu.num_load_insts 114516673 # Number of load instructions
system.cpu.num_store_insts 39453623 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1524795312 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 673.382950 # Cycle average of tags in use
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 673.382950 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.328800 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.328800 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 601861103 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 601861103 # number of overall hits
system.cpu.icache.overall_hits::total 601861103 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 795 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 795 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses
system.cpu.icache.overall_misses::total 795 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 43221000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 43221000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 43221000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 43221000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 43221000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 43221000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 601861898 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54366.037736 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54366.037736 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54366.037736 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54366.037736 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 795 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.202421 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 563489000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.202421 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits
system.cpu.dcache.overall_hits::total 153509968 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
system.cpu.dcache.overall_misses::total 455395 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789140000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2789140000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4194225000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4194225000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6983365000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6983365000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6983365000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6983365000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13860.320426 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13860.320426 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16502.106916 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16502.106916 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15334.742367 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15334.742367 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
system.cpu.dcache.writebacks::total 436902 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 903 # number of replacements
system.cpu.l2cache.tagsinuse 22842.908958 # Cycle average of tags in use
system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21649.670438 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 668.334752 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 524.903769 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.660696 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.020396 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016019 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.697110 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 232970 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 232970 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 430080 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 430092 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 430080 # number of overall hits
system.cpu.l2cache.overall_hits::total 430092 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 783 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4122 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4905 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21193 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21193 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 25315 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26098 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 25315 # number of overall misses
system.cpu.l2cache.overall_misses::total 26098 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40716000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214344000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 255060000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1102036000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1102036000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 40716000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1316380000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1357096000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 40716000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1316380000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1357096000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 456190 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984906 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.024279 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083383 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083383 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984906 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055589 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.057209 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984906 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055589 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.057209 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 883 # number of writebacks
system.cpu.l2cache.writebacks::total 883 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 783 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4122 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4905 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21193 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21193 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 25315 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26098 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 25315 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26098 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 164880000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 196200000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 847720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 847720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1012600000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1043920000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1012600000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1043920000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020484 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024279 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083383 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083383 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057209 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057209 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|