path: root/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.163291                       # Number of seconds simulated
sim_ticks                                163291004000                       # Number of ticks simulated
final_tick                               163291004000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 225808                       # Simulator instruction rate (inst/s)
host_op_rate                                   238605                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               64682367                       # Simulator tick rate (ticks/s)
host_mem_usage                                 234804                       # Number of bytes of host memory used
host_seconds                                  2524.51                       # Real time elapsed on the host
sim_insts                                   570052735                       # Number of instructions simulated
sim_ops                                     602360941                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             47872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           1770240                       # Number of bytes read from this memory
system.physmem.bytes_read::total              1818112                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        47872                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           47872                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks       203264                       # Number of bytes written to this memory
system.physmem.bytes_written::total            203264                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                748                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              27660                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 28408                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            3176                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                 3176                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               293170                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             10841014                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                11134183                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          293170                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             293170                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1244796                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1244796                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1244796                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              293170                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            10841014                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               12378980                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   48                       # Number of system calls
system.cpu.numCycles                        326582009                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 85496783                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           80297868                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            2361759                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              47129611                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 46810915                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  1442822                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                 939                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           68930661                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      669745010                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85496783                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           48253737                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     130048027                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                13475244                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              116341672                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                    2                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           687                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                  67499108                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                807540                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          326356874                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.186850                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.203825                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                196309073     60.15%     60.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 20957347      6.42%     66.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  4946491      1.52%     68.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 14317000      4.39%     72.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  8978746      2.75%     75.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  9407391      2.88%     78.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  4385745      1.34%     79.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  5814869      1.78%     81.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 61240212     18.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            326356874                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.261793                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.050771                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 93064197                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              93574356                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 108736934                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              19947205                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               11034182                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              4784985                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                  1738                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              706036905                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                  6288                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               11034182                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                107346412                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                13092326                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          46822                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 114338400                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              80498732                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              697255622                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   101                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               59224108                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              19051405                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              625                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           723858007                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3241539667                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3241539539                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               128                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             627419213                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 96438794                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               6501                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           6457                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 169431016                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            172916819                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            80629893                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          21434071                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         27751379                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  682016489                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                4774                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 646845145                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1424192                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        79472523                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    197906343                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1840                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     326356874                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.982018                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.741007                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            67525997     20.69%     20.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            84702389     25.95%     46.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            74951613     22.97%     69.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            40526195     12.42%     82.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            28606192      8.77%     90.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            15221367      4.66%     95.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             5979021      1.83%     97.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             6497584      1.99%     99.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             2346516      0.72%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       326356874                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  204976      4.99%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                2983992     72.63%     77.62% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                919347     22.38%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             403923414     62.45%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                 6566      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.45% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            166112206     25.68%     88.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            76802956     11.87%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              646845145                       # Type of FU issued
system.cpu.iq.rate                           1.980651                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     4108315                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.006351                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1625579635                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         761505232                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    638567907                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              650953440                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         30447417                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     23963996                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       129674                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11684                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     10408650                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        12812                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         13814                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               11034182                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  314683                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 40041                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           682087415                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            655237                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             172916819                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             80629893                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               3420                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  12514                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  1466                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11684                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        1312850                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      1582780                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              2895630                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             642706502                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             163991051                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           4138643                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         66152                       # number of nop insts executed
system.cpu.iew.exec_refs                    240011876                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 74666851                       # Number of branches executed
system.cpu.iew.exec_stores                   76020825                       # Number of stores executed
system.cpu.iew.exec_rate                     1.967979                       # Inst execution rate
system.cpu.iew.wb_sent                      640060409                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     638567923                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 420584081                       # num instructions producing a value
system.cpu.iew.wb_consumers                 656222195                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.955306                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.640917                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      570052786                       # The number of committed instructions
system.cpu.commit.commitCommittedOps        602360992                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        79735934                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            2934                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           2422217                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    315322693                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.910300                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.242360                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     91618801     29.06%     29.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    103774162     32.91%     61.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     42992063     13.63%     75.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      8898067      2.82%     78.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     25658030      8.14%     86.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     13146506      4.17%     90.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      7589457      2.41%     93.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1157745      0.37%     93.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     20487862      6.50%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    315322693                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            570052786                       # Number of instructions committed
system.cpu.commit.committedOps              602360992                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      219174066                       # Number of memory references committed
system.cpu.commit.loads                     148952823                       # Number of loads committed
system.cpu.commit.membars                        1328                       # Number of memory barriers committed
system.cpu.commit.branches                   70828830                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 533523551                       # Number of committed integer instructions.
system.cpu.commit.function_calls               997573                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              20487862                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    976931145                       # The number of ROB reads
system.cpu.rob.rob_writes                  1375260810                       # The number of ROB writes
system.cpu.timesIdled                            9894                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          225135                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   570052735                       # Number of Instructions Simulated
system.cpu.committedOps                     602360941                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             570052735                       # Number of Instructions Simulated
system.cpu.cpi                               0.572898                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.572898                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.745512                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.745512                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3210543463                       # number of integer regfile reads
system.cpu.int_regfile_writes               664223214                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.misc_regfile_reads               905101471                       # number of misc regfile reads
system.cpu.misc_regfile_writes                   3116                       # number of misc regfile writes
system.cpu.icache.replacements                     67                       # number of replacements
system.cpu.icache.tagsinuse                689.277263                       # Cycle average of tags in use
system.cpu.icache.total_refs                 67498009                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    823                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               82014.591738                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     689.277263                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.336561                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.336561                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     67498009                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        67498009                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      67498009                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         67498009                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     67498009                       # number of overall hits
system.cpu.icache.overall_hits::total        67498009                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1099                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1099                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1099                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1099                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1099                       # number of overall misses
system.cpu.icache.overall_misses::total          1099                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     36702500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     36702500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     36702500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     36702500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     36702500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     36702500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     67499108                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     67499108                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     67499108                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     67499108                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     67499108                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     67499108                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000016                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000016                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000016                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000016                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000016                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000016                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33396.269336                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 33396.269336                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 33396.269336                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 33396.269336                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 33396.269336                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 33396.269336                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          276                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          276                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          276                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          276                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          276                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          276                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          823                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          823                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          823                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          823                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          823                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          823                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26927500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     26927500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26927500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     26927500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26927500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     26927500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000012                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000012                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000012                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000012                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000012                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000012                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32718.712029                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32718.712029                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32718.712029                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 32718.712029                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32718.712029                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 32718.712029                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 440493                       # number of replacements
system.cpu.dcache.tagsinuse               4094.665054                       # Cycle average of tags in use
system.cpu.dcache.total_refs                200200644                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 444589                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 450.304987                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               87327000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4094.665054                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999674                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999674                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    132070479                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       132070479                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     68126925                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       68126925                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         1683                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         1683                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         1557                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         1557                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     200197404                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        200197404                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    200197404                       # number of overall hits
system.cpu.dcache.overall_hits::total       200197404                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       228400                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        228400                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1290606                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1290606                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           22                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           22                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1519006                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1519006                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1519006                       # number of overall misses
system.cpu.dcache.overall_misses::total       1519006                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   1639819000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   1639819000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  12328996350                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  12328996350                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       168000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       168000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  13968815350                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  13968815350                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  13968815350                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  13968815350                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    132298879                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    132298879                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     69417531                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     69417531                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         1705                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         1705                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         1557                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         1557                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    201716410                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    201716410                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    201716410                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    201716410                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001726                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.001726                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.018592                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.018592                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.012903                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.012903                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.007530                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.007530                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.007530                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.007530                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  7179.592820                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total  7179.592820                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9552.873883                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  9552.873883                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  7636.363636                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  7636.363636                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data  9196.023814                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total  9196.023814                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data  9196.023814                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total  9196.023814                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      9916851                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2339                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  4239.782386                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       421148                       # number of writebacks
system.cpu.dcache.writebacks::total            421148                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        30933                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        30933                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1043483                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1043483                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           22                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           22                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1074416                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1074416                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1074416                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1074416                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       197467                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       197467                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       247123                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       247123                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       444590                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       444590                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       444590                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       444590                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    754200000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    754200000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1366160851                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   1366160851                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   2120360851                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   2120360851                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   2120360851                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   2120360851                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001493                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001493                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003560                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.003560                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002204                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002204                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002204                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002204                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  3819.372351                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  3819.372351                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  5528.262651                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  5528.262651                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  4769.249985                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total  4769.249985                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  4769.249985                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total  4769.249985                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                  4232                       # number of replacements
system.cpu.l2cache.tagsinuse             21916.989023                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  505361                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                 25263                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 20.003998                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20776.737847                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    177.343583                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    962.907593                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.634056                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.005412                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.029386                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.668853                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst           74                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       191964                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         192038                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       421148                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       421148                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       224955                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       224955                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst           74                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       416919                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          416993                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           74                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       416919                       # number of overall hits
system.cpu.l2cache.overall_hits::total         416993                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          749                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         5501                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         6250                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        22170                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        22170                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          749                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        27671                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         28420                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          749                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        27671                       # number of overall misses
system.cpu.l2cache.overall_misses::total        28420                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     25729000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    189531000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    215260000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    766936500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    766936500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     25729000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    956467500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    982196500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     25729000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    956467500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    982196500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          823                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       197465                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       198288                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       421148                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       421148                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       247125                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       247125                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          823                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       444590                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       445413                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          823                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       444590                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       445413                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.910085                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.027858                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.031520                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.089712                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.089712                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.910085                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.062239                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063806                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.910085                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.062239                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063806                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34351.134846                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34453.917470                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34441.600000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34593.437077                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34593.437077                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34351.134846                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34565.700553                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34560.045742                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34351.134846                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34565.700553                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34560.045742                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs      2032500                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs              322                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs  6312.111801                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks         3176                       # number of writebacks
system.cpu.l2cache.writebacks::total             3176                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           11                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           11                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           12                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           11                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           12                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          748                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         5490                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         6238                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        22170                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        22170                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          748                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        27660                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        28408                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          748                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        27660                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        28408                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     23297500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    171301000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    194598500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    698565000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    698565000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23297500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    869866000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    893163500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23297500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    869866000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    893163500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.908870                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.027802                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.031459                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.089712                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.089712                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.908870                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.062215                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063779                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.908870                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.062215                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063779                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31146.390374                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31202.367942                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.655659                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31509.472260                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31509.472260                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31146.390374                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448.517715                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31440.562518                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31146.390374                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448.517715                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31440.562518                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------