path: root/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.607412                       # Number of seconds simulated
sim_ticks                                607412415000                       # Number of ticks simulated
final_tick                               607412415000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  59004                       # Simulator instruction rate (inst/s)
host_op_rate                                   108719                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               40726098                       # Simulator tick rate (ticks/s)
host_mem_usage                                 295644                       # Number of bytes of host memory used
host_seconds                                 14914.57                       # Real time elapsed on the host
sim_insts                                   880025277                       # Number of instructions simulated
sim_ops                                    1621493927                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             57664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           1693248                       # Number of bytes read from this memory
system.physmem.bytes_read::total              1750912                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        57664                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           57664                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks       162176                       # Number of bytes written to this memory
system.physmem.bytes_written::total            162176                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                901                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              26457                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 27358                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            2534                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                 2534                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                94934                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2787641                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2882575                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           94934                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              94934                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks            266995                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                 266995                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks            266995                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               94934                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2787641                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3149570                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         27360                       # Total number of read requests seen
system.physmem.writeReqs                         2534                       # Total number of write requests seen
system.physmem.cpureqs                          29894                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                      1750912                       # Total number of bytes read from memory
system.physmem.bytesWritten                    162176                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                1750912                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                 162176                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                  1741                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                  1719                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                  1711                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                  1642                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                  1657                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                  1654                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                  1713                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                  1701                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                  1712                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                  1711                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                 1718                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                 1730                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                 1738                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                 1728                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                 1750                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                 1735                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                   160                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                   162                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                   160                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                   155                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                   155                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                   154                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                   158                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                   157                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                   156                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                   160                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                  158                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                  159                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                  159                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                  158                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                  164                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                  159                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    607412402000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                   27360                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                   2534                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                     26889                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       351                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        21                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                       88987000                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                 893982000                       # Sum of mem lat for all requests
system.physmem.totBusLat                    136800000                       # Total cycles spent in databus access
system.physmem.totBankLat                   668195000                       # Total cycles spent in bank access
system.physmem.avgQLat                        3252.45                       # Average queueing delay per request
system.physmem.avgBankLat                    24422.33                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  32674.78                       # Average memory access latency
system.physmem.avgRdBW                           2.88                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.27                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.88                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.27                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                        13.09                       # Average write queue length over time
system.physmem.readRowHits                      16427                       # Number of row buffer hits during reads
system.physmem.writeRowHits                      1022                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   60.04                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  40.33                       # Row buffer hit rate for writes
system.physmem.avgGap                     20318873.42                       # Average gap between requests
system.cpu.branchPred.lookups               158382296                       # Number of BP lookups
system.cpu.branchPred.condPredicted         158382296                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          26387252                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             83381183                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                83179505                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             99.758125                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls                   48                       # Number of system calls
system.cpu.numCycles                       1214824831                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          179163349                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1457867613                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   158382296                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           83179505                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     399005833                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                88132062                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              574704368                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   43                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           361                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                 186835049                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes              10712979                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1214462855                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.059159                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.252870                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                822674810     67.74%     67.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 26926688      2.22%     69.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 13135389      1.08%     71.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 20566511      1.69%     72.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 26637257      2.19%     74.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 18247973      1.50%     76.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 31504454      2.59%     79.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 39098170      3.22%     82.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                215671603     17.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1214462855                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.130375                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.200064                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                288324734                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             497934423                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 274040429                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              92574368                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               61588901                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2343698812                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles               61588901                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                336957337                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               124218348                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           2659                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 304046563                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             387649047                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2248109589                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   354                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents              242721119                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents             120169480                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands          2618670353                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5724257672                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       5724251768                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              5904                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1886895260                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                731775093                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 91                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             91                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 731348064                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            531825278                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           219280996                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         342077982                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores        144753457                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1993869707                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 294                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1783892793                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            265772                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       371981386                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    760150327                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            245                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1214462855                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.468874                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.421634                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           360357006     29.67%     29.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           364326915     30.00%     59.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           234272776     19.29%     78.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           141367539     11.64%     90.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            60718828      5.00%     95.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            39723200      3.27%     98.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            11050512      0.91%     99.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             2045307      0.17%     99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              600772      0.05%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1214462855                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  450048     15.52%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     15.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                2249912     77.59%     93.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                199796      6.89%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass          46812279      2.62%      2.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1065698440     59.74%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            478836274     26.84%     89.21% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           192545800     10.79%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1783892793                       # Type of FU issued
system.cpu.iq.rate                           1.468436                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2899756                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001626                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         4785413585                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2366027132                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1724688067                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 384                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes               1824                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           99                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1739980085                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     185                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        209981192                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    112783156                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        38868                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       181899                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     31094938                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         2165                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            66                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               61588901                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1215520                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                110006                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1993870001                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts          63340037                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             531825278                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            219280996                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 84                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  53594                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  2844                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         181899                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        2045614                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect     24471458                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             26517072                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1766151616                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             474571020                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          17741177                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    666290065                       # number of memory reference insts executed
system.cpu.iew.exec_branches                110357109                       # Number of branches executed
system.cpu.iew.exec_stores                  191719045                       # Number of stores executed
system.cpu.iew.exec_rate                     1.453832                       # Inst execution rate
system.cpu.iew.wb_sent                     1725806864                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1724688166                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1267103836                       # num instructions producing a value
system.cpu.iew.wb_consumers                1828916065                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.419701                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.692817                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       372377336                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              49                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          26387302                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1152873954                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.406480                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.829955                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    418181253     36.27%     36.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    415089887     36.00%     72.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     86977349      7.54%     79.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3    122167535     10.60%     90.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     24171647      2.10%     92.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     25387316      2.20%     94.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     16411129      1.42%     96.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     12045909      1.04%     97.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     32441929      2.81%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1152873954                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            880025277                       # Number of instructions committed
system.cpu.commit.committedOps             1621493927                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      607228180                       # Number of memory references committed
system.cpu.commit.loads                     419042122                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  107161574                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1621354439                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              32441929                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   3114303288                       # The number of ROB reads
system.cpu.rob.rob_writes                  4049366814                       # The number of ROB writes
system.cpu.timesIdled                           58967                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          361976                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   880025277                       # Number of Instructions Simulated
system.cpu.committedOps                    1621493927                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             880025277                       # Number of Instructions Simulated
system.cpu.cpi                               1.380443                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.380443                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.724405                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.724405                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3542727713                       # number of integer regfile reads
system.cpu.int_regfile_writes              1974483700                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        99                       # number of floating regfile reads
system.cpu.misc_regfile_reads               910779890                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.icache.replacements                     25                       # number of replacements
system.cpu.icache.tagsinuse                814.738585                       # Cycle average of tags in use
system.cpu.icache.total_refs                186833677                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    918                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               203522.523965                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     814.738585                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.397822                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.397822                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    186833682                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       186833682                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     186833682                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        186833682                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    186833682                       # number of overall hits
system.cpu.icache.overall_hits::total       186833682                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1367                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1367                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1367                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1367                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1367                       # number of overall misses
system.cpu.icache.overall_misses::total          1367                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     65166500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     65166500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     65166500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     65166500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     65166500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     65166500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    186835049                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    186835049                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    186835049                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    186835049                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    186835049                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    186835049                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000007                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000007                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000007                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000007                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000007                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000007                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47671.177762                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 47671.177762                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 47671.177762                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 47671.177762                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 47671.177762                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 47671.177762                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          146                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    29.200000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          444                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          444                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          444                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          444                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          444                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          444                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          923                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          923                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          923                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          923                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          923                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          923                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     47626500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     47626500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     47626500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     47626500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     47626500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     47626500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000005                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000005                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51599.674973                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51599.674973                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51599.674973                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51599.674973                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51599.674973                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51599.674973                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                  2556                       # number of replacements
system.cpu.l2cache.tagsinuse             22259.918849                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  531250                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                 24190                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 21.961554                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20782.874819                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    797.549554                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    679.494476                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.634243                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.024339                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.020737                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.679319                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       199226                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         199243                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       428982                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       428982                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            5                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       224442                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       224442                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst           17                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       423668                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          423685                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           17                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       423668                       # number of overall hits
system.cpu.l2cache.overall_hits::total         423685                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          901                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         4560                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         5461                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        21899                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        21899                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          901                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        26459                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         27360                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          901                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        26459                       # number of overall misses
system.cpu.l2cache.overall_misses::total        27360                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     46520500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    330240500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    376761000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1132989500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1132989500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     46520500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   1463230000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   1509750500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     46520500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   1463230000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   1509750500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          918                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       203786                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       204704                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       428982                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       428982                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data            5                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            5                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       246341                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       246341                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          918                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       450127                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       451045                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          918                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       450127                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       451045                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.981481                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.022376                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.026678                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.088897                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.088897                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.981481                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.058781                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.060659                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.981481                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.058781                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.060659                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51632.075472                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72421.162281                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68991.210401                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51737.042787                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51737.042787                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51632.075472                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55301.787671                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 55180.939327                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51632.075472                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55301.787671                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 55180.939327                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks         2534                       # number of writebacks
system.cpu.l2cache.writebacks::total             2534                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          901                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4560                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         5461                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21899                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        21899                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          901                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        26459                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        27360                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          901                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        26459                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        27360                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     35335231                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    273228266                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    308563497                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    860769620                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    860769620                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     35335231                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1133997886                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   1169333117                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     35335231                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1133997886                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   1169333117                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.981481                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.022376                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.026678                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.088897                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.088897                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.981481                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.058781                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.060659                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.981481                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.058781                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.060659                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39217.792453                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59918.479386                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56503.112434                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39306.343669                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39306.343669                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39217.792453                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42858.682717                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42738.783516                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39217.792453                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42858.682717                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42738.783516                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 446028                       # number of replacements
system.cpu.dcache.tagsinuse               4092.714418                       # Cycle average of tags in use
system.cpu.dcache.total_refs                452315129                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 450124                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                1004.867834                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              861652000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4092.714418                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999198                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999198                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    264375496                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       264375496                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    187939628                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      187939628                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     452315124                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        452315124                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    452315124                       # number of overall hits
system.cpu.dcache.overall_hits::total       452315124                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       211166                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        211166                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       246430                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       246430                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data       457596                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         457596                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       457596                       # number of overall misses
system.cpu.dcache.overall_misses::total        457596                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   3021463500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   3021463500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   4117356500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   4117356500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   7138820000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   7138820000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   7138820000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   7138820000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    264586662                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    264586662                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    188186058                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    188186058                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    452772720                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    452772720                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    452772720                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    452772720                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000798                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000798                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001310                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001310                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.001011                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.001011                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.001011                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.001011                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14308.475323                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14308.475323                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16708.016475                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16708.016475                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15600.704552                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15600.704552                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15600.704552                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15600.704552                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          398                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                38                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.473684                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       428982                       # number of writebacks
system.cpu.dcache.writebacks::total            428982                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data         7377                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total         7377                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data           87                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total           87                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         7464                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         7464                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         7464                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         7464                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       203789                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       203789                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       246343                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       246343                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       450132                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       450132                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       450132                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       450132                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2528052500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   2528052500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3623861000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   3623861000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6151913500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   6151913500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6151913500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   6151913500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000770                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000770                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001309                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.001309                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000994                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000994                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000994                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000994                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.245131                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.245131                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14710.631112                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14710.631112                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13666.909929                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13666.909929                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13666.909929                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13666.909929                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------