1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.061593 # Number of seconds simulated
sim_ticks 61592600500 # Number of ticks simulated
final_tick 61592600500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 271325 # Simulator instruction rate (inst/s)
host_op_rate 272676 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 184448880 # Simulator tick rate (ticks/s)
host_mem_usage 445184 # Number of bytes of host memory used
host_seconds 333.93 # Real time elapsed on the host
sim_insts 90602849 # Number of instructions simulated
sim_ops 91054080 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 49600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
system.physmem.bytes_read::total 996800 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 805292 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15378471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16183762 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 805292 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 805292 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 805292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15378471 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 16183762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15575 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 993 # Per bank write bursts
system.physmem.perBankRdBursts::1 890 # Per bank write bursts
system.physmem.perBankRdBursts::2 949 # Per bank write bursts
system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
system.physmem.perBankRdBursts::9 962 # Per bank write bursts
system.physmem.perBankRdBursts::10 938 # Per bank write bursts
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
system.physmem.perBankRdBursts::12 904 # Per bank write bursts
system.physmem.perBankRdBursts::13 867 # Per bank write bursts
system.physmem.perBankRdBursts::14 877 # Per bank write bursts
system.physmem.perBankRdBursts::15 905 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 61592506000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 15575 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 642.644287 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 437.986910 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 400.933627 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 248 16.01% 16.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 186 12.01% 28.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 90 5.81% 33.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 71 4.58% 38.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 77 4.97% 43.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 93 6.00% 49.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 43 2.78% 52.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 36 2.32% 54.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 705 45.51% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation
system.physmem.totQLat 77242000 # Total ticks spent queuing
system.physmem.totMemAccLat 369273250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
system.physmem.avgQLat 4959.36 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 23709.36 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.13 # Data bus utilization in percentage
system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 14018 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 3954575.02 # Average gap between requests
system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6373080 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3477375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 63718200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2539008855 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 34726497750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41361784860 # Total energy per rank (pJ)
system.physmem_0.averagePower 671.572046 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 57760380750 # Time in different power states
system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1772530500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 5329800 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2908125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 57478200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2571546735 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34697955750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41357928210 # Total energy per rank (pJ)
system.physmem_1.averagePower 671.509428 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 57713961000 # Time in different power states
system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1819631500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 20789446 # Number of BP lookups
system.cpu.branchPred.condPredicted 17091418 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8973614 # Number of BTB lookups
system.cpu.branchPred.BTBHits 8867024 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.812184 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 123185201 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602849 # Number of instructions committed
system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2068247 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.359617 # CPI: cycles per instruction
system.cpu.ipc 0.735501 # IPC: instructions per cycle
system.cpu.tickCycles 109827605 # Number of cycles that the object actually ticked
system.cpu.idleCycles 13357596 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 946107 # number of replacements
system.cpu.dcache.tags.tagsinuse 3616.143974 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26267423 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.644012 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.143974 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.882848 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.882848 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55463259 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55463259 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21598839 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21598839 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660810 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4660810 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26259649 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26259649 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26259649 # number of overall hits
system.cpu.dcache.overall_hits::total 26259649 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 74171 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 74171 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 989105 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 989105 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 989105 # number of overall misses
system.cpu.dcache.overall_misses::total 989105 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918412494 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11918412494 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2568231500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2568231500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14486643994 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14486643994 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14486643994 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14486643994 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22513773 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22513773 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27248754 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27248754 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27248754 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27248754 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015664 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015664 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.527043 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.527043 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34625.817368 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34625.817368 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14646.214501 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14646.214501 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks
system.cpu.dcache.writebacks::total 943286 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11499 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 11499 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27403 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27403 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 38902 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 38902 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 38902 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 38902 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 950203 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413322256 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413322256 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464464500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464464500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877786756 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11877786756 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877786756 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11877786756 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.365766 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.365766 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31313.387359 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31313.387359 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 5 # number of replacements
system.cpu.icache.tags.tagsinuse 690.370829 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27857028 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 34691.193026 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 690.370829 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.337095 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.337095 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 55716465 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55716465 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 27857028 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27857028 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27857028 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27857028 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27857028 # number of overall hits
system.cpu.icache.overall_hits::total 27857028 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
system.cpu.icache.overall_misses::total 803 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 61138997 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 61138997 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 61138997 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 61138997 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 61138997 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 61138997 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27857831 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27857831 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27857831 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27857831 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27857831 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27857831 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76138.227895 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76138.227895 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76138.227895 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76138.227895 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59598503 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 59598503 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59598503 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 59598503 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59598503 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 59598503 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74219.804483 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74219.804483 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 10238.643668 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1831333 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 117.710053 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 9347.860585 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.375683 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.407400 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.285274 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020611 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.312459 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 903198 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 935422 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 935397 # number of overall hits
system.cpu.l2cache.overall_hits::total 935422 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 778 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1040 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 778 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15584 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 778 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses
system.cpu.l2cache.overall_misses::total 15584 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58533000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 80800750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073909000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1073909000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 58533000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1096176750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1154709750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 58533000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1096176750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1154709750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46768 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968867 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001150 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968867 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016387 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968867 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016387 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75235.218509 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84991.412214 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77693.028846 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73838.627613 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73838.627613 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74095.851514 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74095.851514 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48659000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18669250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 67328250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 892098500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 892098500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48659000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910767750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 959426750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48659000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910767750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 959426750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310982 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62785.806452 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72926.757812 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65303.831232 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61337.905666 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61337.905666 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2845298 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183296 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 1894292 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1372497 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1428682244 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
system.membus.trans_dist::ReadReq 1031 # Transaction distribution
system.membus.trans_dist::ReadResp 1031 # Transaction distribution
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 15575 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15575 # Request fanout histogram
system.membus.reqLayer0.occupancy 21632500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
|