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|
---------- Begin Simulation Statistics ----------
final_tick 61269894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
host_inst_rate 246086 # Simulator instruction rate (inst/s)
host_mem_usage 426904 # Number of bytes of host memory used
host_op_rate 247853 # Simulator op (including micro ops) rate (op/s)
host_seconds 368.18 # Real time elapsed on the host
host_tick_rate 166415131 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 90602849 # Number of instructions simulated
sim_ops 91253402 # Number of ops (including micro ops) simulated
sim_seconds 0.061270 # Number of seconds simulated
sim_ticks 61269894500 # Number of ticks simulated
system.clk_domain.clock 1000 # Clock period in ticks
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.707356 # BTB Hit Percentage
system.cpu.branchPred.BTBHits 8859613 # Number of BTB hits
system.cpu.branchPred.BTBLookups 8975636 # Number of BTB lookups
system.cpu.branchPred.RASInCorrect 1020 # Number of incorrect RAS predictions.
system.cpu.branchPred.condIncorrect 765388 # Number of conditional branches incorrect
system.cpu.branchPred.condPredicted 17116903 # Number of conditional branches predicted
system.cpu.branchPred.lookups 20794461 # Number of BP lookups
system.cpu.branchPred.usedRAS 54785 # Number of times the RAS was used to get a target.
system.cpu.committedInsts 90602849 # Number of instructions committed
system.cpu.committedOps 91253402 # Number of ops (including micro ops) committed
system.cpu.cpi 1.352494 # CPI: cycles per instruction
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses::cpu.inst 22606743 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22606743 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13018.894340 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13018.894340 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11024.761855 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.761855 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits::cpu.inst 21691800 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21691800 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11911546244 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11911546244 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040472 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040472 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::cpu.inst 914943 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 914943 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11527 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 11527 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9959946256 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9959946256 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.039962 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039962 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903416 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903416 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31690.074425 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31690.074425 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28535.254491 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.254491 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits::cpu.inst 4661081 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4661081 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2341896500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2341896500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015607 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015607 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::cpu.inst 73900 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 73900 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334308500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334308500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009875 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009875 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46760 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46760 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses::cpu.inst 27341724 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27341724 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14414.262673 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14414.262673 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11886.487089 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11886.487089 # average overall mshr miss latency
system.cpu.dcache.demand_hits::cpu.inst 26352881 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26352881 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency::cpu.inst 14253442744 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14253442744 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate::cpu.inst 0.036166 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036166 # miss rate for demand accesses
system.cpu.dcache.demand_misses::cpu.inst 988843 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 988843 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits::cpu.inst 38667 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 38667 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11294254756 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11294254756 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034752 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034752 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses::cpu.inst 950176 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 950176 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses::cpu.inst 27341724 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27341724 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14414.262673 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14414.262673 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11886.487089 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11886.487089 # average overall mshr miss latency
system.cpu.dcache.overall_hits::cpu.inst 26352881 # number of overall hits
system.cpu.dcache.overall_hits::total 26352881 # number of overall hits
system.cpu.dcache.overall_miss_latency::cpu.inst 14253442744 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14253442744 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate::cpu.inst 0.036166 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036166 # miss rate for overall accesses
system.cpu.dcache.overall_misses::cpu.inst 988843 # number of overall misses
system.cpu.dcache.overall_misses::total 988843 # number of overall misses
system.cpu.dcache.overall_mshr_hits::cpu.inst 38667 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 38667 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11294254756 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11294254756 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034752 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034752 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses::cpu.inst 950176 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 950176 # number of overall MSHR misses
system.cpu.dcache.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2200 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id
system.cpu.dcache.tags.avg_refs 27.742918 # Average number of references to valid blocks.
system.cpu.dcache.tags.data_accesses 55649172 # Number of data accesses
system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.532737 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst 0.883431 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.883431 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.replacements 946080 # number of replacements
system.cpu.dcache.tags.sampled_refs 950176 # Sample count of references to valid blocks.
system.cpu.dcache.tags.tag_accesses 55649172 # Number of tag accesses
system.cpu.dcache.tags.tagsinuse 3618.532737 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26360655 # Total number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20496262250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks::writebacks 943298 # number of writebacks
system.cpu.dcache.writebacks::total 943298 # number of writebacks
system.cpu.discardedOps 2065378 # Number of ops (including micro ops) which were discarded before commit
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses::cpu.inst 27818907 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27818907 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68915.429630 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 68915.429630 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66500.619753 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66500.619753 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits::cpu.inst 27818097 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27818097 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55821498 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 55821498 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::cpu.inst 810 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 810 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53865502 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 53865502 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 810 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 810 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses::cpu.inst 27818907 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27818907 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68915.429630 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 68915.429630 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66500.619753 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 66500.619753 # average overall mshr miss latency
system.cpu.icache.demand_hits::cpu.inst 27818097 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27818097 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency::cpu.inst 55821498 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 55821498 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
system.cpu.icache.demand_misses::cpu.inst 810 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 810 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53865502 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 53865502 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses::cpu.inst 810 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 810 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses::cpu.inst 27818907 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27818907 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68915.429630 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 68915.429630 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66500.619753 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66500.619753 # average overall mshr miss latency
system.cpu.icache.overall_hits::cpu.inst 27818097 # number of overall hits
system.cpu.icache.overall_hits::total 27818097 # number of overall hits
system.cpu.icache.overall_miss_latency::cpu.inst 55821498 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 55821498 # number of overall miss cycles
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
system.cpu.icache.overall_misses::cpu.inst 810 # number of overall misses
system.cpu.icache.overall_misses::total 810 # number of overall misses
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53865502 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 53865502 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses::cpu.inst 810 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 810 # number of overall MSHR misses
system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 748 # Occupied blocks per task id
system.cpu.icache.tags.avg_refs 34343.329630 # Average number of references to valid blocks.
system.cpu.icache.tags.data_accesses 55638624 # Number of data accesses
system.cpu.icache.tags.occ_blocks::cpu.inst 696.774140 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.340222 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.340222 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id
system.cpu.icache.tags.replacements 5 # number of replacements
system.cpu.icache.tags.sampled_refs 810 # Sample count of references to valid blocks.
system.cpu.icache.tags.tag_accesses 55638624 # Number of tag accesses
system.cpu.icache.tags.tagsinuse 696.774140 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27818097 # Total number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.idleCycles 13105167 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.ipc 0.739375 # IPC: instructions per cycle
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46760 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46760 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65946.757667 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65946.757667 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53094.192683 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53094.192683 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits::cpu.inst 32218 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32218 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958997750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 958997750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310992 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.310992 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses::cpu.inst 14542 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14542 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772095750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772095750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310992 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310992 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14542 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14542 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses::cpu.inst 904226 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 904226 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69821.699905 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69821.699905 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57393.301435 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57393.301435 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits::cpu.inst 903173 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 903173 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 73522250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 73522250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001165 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001165 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses::cpu.inst 1053 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1053 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59976000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 59976000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001156 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001156 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1045 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1045 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses::writebacks 943298 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 943298 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits::writebacks 943298 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 943298 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses::cpu.inst 950986 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 950986 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66208.400128 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66208.400128 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53382.418041 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53382.418041 # average overall mshr miss latency
system.cpu.l2cache.demand_hits::cpu.inst 935391 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 935391 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency::cpu.inst 1032520000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1032520000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016399 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016399 # miss rate for demand accesses
system.cpu.l2cache.demand_misses::cpu.inst 15595 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15595 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832071750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 832071750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016390 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016390 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15587 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15587 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses::cpu.inst 950986 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66208.400128 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66208.400128 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53382.418041 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53382.418041 # average overall mshr miss latency
system.cpu.l2cache.overall_hits::cpu.inst 935391 # number of overall hits
system.cpu.l2cache.overall_hits::total 935391 # number of overall hits
system.cpu.l2cache.overall_miss_latency::cpu.inst 1032520000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1032520000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016399 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016399 # miss rate for overall accesses
system.cpu.l2cache.overall_misses::cpu.inst 15595 # number of overall misses
system.cpu.l2cache.overall_misses::total 15595 # number of overall misses
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832071750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 832071750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016390 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016390 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15587 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15587 # number of overall MSHR misses
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13889 # Occupied blocks per task id
system.cpu.l2cache.tags.avg_refs 117.618626 # Average number of references to valid blocks.
system.cpu.l2cache.tags.data_accesses 15216602 # Number of data accesses
system.cpu.l2cache.tags.occ_blocks::writebacks 9366.525575 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 902.408366 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.285844 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027539 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.313383 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15570 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475159 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.sampled_refs 15570 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.tag_accesses 15216602 # Number of tag accesses
system.cpu.l2cache.tags.tagsinuse 10268.933941 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1831322 # Total number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.numCycles 122539789 # number of cpu cycles simulated
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.tickCycles 109434622 # Number of cycles that the CPU actually ticked
system.cpu.toL2Bus.data_through_bus 121234176 # Total data (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1620 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843650 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2845270 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 1890440000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1382998 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1428632744 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.throughput 1978690791 # Throughput (bytes/s)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51840 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182336 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 121234176 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.trans_dist::ReadReq 904226 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 904226 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 943298 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46760 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46760 # Transaction distribution
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.membus.data_through_bus 997568 # Total data (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31174 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31174 # Packet count per connected master and slave (bytes)
system.membus.reqLayer0.occupancy 21774500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 149672750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.throughput 16281536 # Throughput (bytes/s)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 997568 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 997568 # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadReq 1045 # Transaction distribution
system.membus.trans_dist::ReadResp 1045 # Transaction distribution
system.membus.trans_dist::ReadExReq 14542 # Transaction distribution
system.membus.trans_dist::ReadExResp 14542 # Transaction distribution
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgGap 3930827.39 # Average gap between requests
system.physmem.avgMemAccLat 23360.33 # Average memory access latency per DRAM burst
system.physmem.avgQLat 4610.33 # Average queueing delay per DRAM burst
system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.busUtil 0.13 # Data bus utilization in percentage
system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.bw_inst_read::cpu.inst 816845 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 816845 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 16281536 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16281536 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 16281536 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 16281536 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytesPerActivate::samples 1547 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 643.557854 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 434.536592 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 403.240998 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 258 16.68% 16.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 197 12.73% 29.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 72 4.65% 34.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 57 3.68% 37.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 69 4.46% 42.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 102 6.59% 48.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 43 2.78% 51.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 57 3.68% 55.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 692 44.73% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1547 # Bytes accessed per row activation
system.physmem.bytesReadDRAM 997568 # Total number of bytes read from DRAM
system.physmem.bytesReadSys 997568 # Total read bytes from the system interface side
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.bytes_inst_read::cpu.inst 50048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 50048 # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu.inst 997568 # Number of bytes read from this memory
system.physmem.bytes_read::total 997568 # Number of bytes read from this memory
system.physmem.memoryStateTime::IDLE 55978709750 # Time in different power states
system.physmem.memoryStateTime::REF 2045680000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 3241107750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.num_reads::cpu.inst 15587 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15587 # Number of read requests responded to by this memory
system.physmem.pageHitRate 90.01 # Row buffer hit rate, read and write combined
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.perBankRdBursts::0 994 # Per bank write bursts
system.physmem.perBankRdBursts::1 891 # Per bank write bursts
system.physmem.perBankRdBursts::2 951 # Per bank write bursts
system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
system.physmem.perBankRdBursts::4 1052 # Per bank write bursts
system.physmem.perBankRdBursts::5 1115 # Per bank write bursts
system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
system.physmem.perBankRdBursts::9 962 # Per bank write bursts
system.physmem.perBankRdBursts::10 941 # Per bank write bursts
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
system.physmem.perBankRdBursts::12 904 # Per bank write bursts
system.physmem.perBankRdBursts::13 869 # Per bank write bursts
system.physmem.perBankRdBursts::14 877 # Per bank write bursts
system.physmem.perBankRdBursts::15 904 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.rdQLenPdf::0 15468 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.readBursts 15587 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 15587 # Read request sizes (log2)
system.physmem.readReqs 15587 # Number of read requests accepted
system.physmem.readRowHitRate 90.01 # Row buffer hit rate for reads
system.physmem.readRowHits 14030 # Number of row buffer hits during reads
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.totBusLat 77935000 # Total ticks spent in databus transfers
system.physmem.totGap 61269806500 # Total gap between requests
system.physmem.totMemAccLat 364117500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 71861250 # Total ticks spent queuing
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.voltage_domain.voltage 1 # Voltage in Volts
---------- End Simulation Statistics ----------
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