path: root/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.061144                       # Number of seconds simulated
sim_ticks                                 61144411500                       # Number of ticks simulated
final_tick                                61144411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 253751                       # Simulator instruction rate (inst/s)
host_op_rate                                   255015                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              171247115                       # Simulator tick rate (ticks/s)
host_mem_usage                                 451144                       # Number of bytes of host memory used
host_seconds                                   357.05                       # Real time elapsed on the host
sim_insts                                    90602849                       # Number of instructions simulated
sim_ops                                      91054080                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            996736                       # Number of bytes read from this memory
system.physmem.bytes_read::total               996736                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        49600                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           49600                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst              15574                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 15574                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst             16301343                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                16301343                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          811194                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             811194                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            16301343                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               16301343                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         15574                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                       15574                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   996736                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    996736                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 993                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 890                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 950                       # Per bank write bursts
system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
system.physmem.perBankRdBursts::4                1050                       # Per bank write bursts
system.physmem.perBankRdBursts::5                1113                       # Per bank write bursts
system.physmem.perBankRdBursts::6                1088                       # Per bank write bursts
system.physmem.perBankRdBursts::7                1088                       # Per bank write bursts
system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
system.physmem.perBankRdBursts::10                938                       # Per bank write bursts
system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
system.physmem.perBankRdBursts::12                903                       # Per bank write bursts
system.physmem.perBankRdBursts::13                867                       # Per bank write bursts
system.physmem.perBankRdBursts::14                877                       # Per bank write bursts
system.physmem.perBankRdBursts::15                904                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     61144323500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   15574                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     15451                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       114                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         1531                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      649.865447                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     447.084914                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     397.724653                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            242     15.81%     15.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          164     10.71%     26.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           94      6.14%     32.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           77      5.03%     37.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           65      4.25%     41.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          106      6.92%     48.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           51      3.33%     52.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           28      1.83%     54.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          704     45.98%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           1531                       # Bytes accessed per row activation
system.physmem.totQLat                       71444000                       # Total ticks spent queuing
system.physmem.totMemAccLat                 363456500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     77870000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        4587.39                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  23337.39                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          16.30                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       16.30                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.13                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                      14033                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.11                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      3926051.34                       # Average gap between requests
system.physmem.pageHitRate                      90.11                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE      55905599000                       # Time in different power states
system.physmem.memoryStateTime::REF        2041520000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT        3193563500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     16301343                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                1030                       # Transaction distribution
system.membus.trans_dist::ReadResp               1030                       # Transaction distribution
system.membus.trans_dist::ReadExReq             14544                       # Transaction distribution
system.membus.trans_dist::ReadExResp            14544                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31148                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  31148                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       996736                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total              996736                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                 996736                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            21821000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy          149563500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                20748985                       # Number of BP lookups
system.cpu.branchPred.condPredicted          17053333                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            764055                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              8969348                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 8846034                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             98.625162                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                   62305                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  442                       # Number of system calls
system.cpu.numCycles                        122288823                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    90602849                       # Number of instructions committed
system.cpu.committedOps                      91054080                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       2027782                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.349724                       # CPI: cycles per instruction
system.cpu.ipc                               0.740892                       # IPC: instructions per cycle
system.cpu.tickCycles                       109176310                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        13112513                       # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements                 5                       # number of replacements
system.cpu.icache.tags.tagsinuse           690.927528                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            27773576                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               803                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          34587.267746                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   690.927528                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.337367                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.337367                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          798                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          741                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.389648                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          55549561                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         55549561                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     27773576                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        27773576                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      27773576                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         27773576                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     27773576                       # number of overall hits
system.cpu.icache.overall_hits::total        27773576                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          803                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           803                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          803                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            803                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          803                       # number of overall misses
system.cpu.icache.overall_misses::total           803                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     55308998                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     55308998                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     55308998                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     55308998                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     55308998                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     55308998                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     27774379                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     27774379                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     27774379                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     27774379                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     27774379                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     27774379                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68877.955168                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 68877.955168                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68877.955168                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 68877.955168                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68877.955168                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 68877.955168                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          803                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          803                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          803                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          803                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          803                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          803                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     53368002                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     53368002                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     53368002                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     53368002                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     53368002                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     53368002                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000029                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000029                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000029                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66460.774595                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66460.774595                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66460.774595                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 66460.774595                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66460.774595                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66460.774595                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput              1982677223                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq         904183                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        904183                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       943269                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        46761                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        46761                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1606                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2843551                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           2845157                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51392                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121178240                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      121229632                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         121229632                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     1890375500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1371998                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1428578994                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        10264.635484                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1831263                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs            15557                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs           117.713119                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  9373.658869                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   890.976615                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.286061                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.027190                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.313252                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        15557                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          526                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1094                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13878                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.474762                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         15216022                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        15216022                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst       903145                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         903145                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       943269                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       943269                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst        32217                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total        32217                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       935362                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          935362                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       935362                       # number of overall hits
system.cpu.l2cache.overall_hits::total         935362                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         1038                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         1038                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst        14544                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        14544                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        15582                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         15582                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        15582                       # number of overall misses
system.cpu.l2cache.overall_misses::total        15582                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     71727250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     71727250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    959621000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    959621000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1031348250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   1031348250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1031348250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   1031348250                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst       904183                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       904183                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       943269                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       943269                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst        46761                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        46761                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       950944                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       950944                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       950944                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       950944                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.001148                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.001148                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.311028                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.311028                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016386                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.016386                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016386                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.016386                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69101.396917                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69101.396917                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65980.541804                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65980.541804                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.438583                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66188.438583                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.438583                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66188.438583                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            8                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1030                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         1030                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        14544                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        14544                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        15574                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        15574                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        15574                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        15574                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     58365000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58365000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    772683000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    772683000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    831048000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    831048000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    831048000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    831048000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.001139                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001139                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.311028                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311028                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016377                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.016377                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016377                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.016377                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56665.048544                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56665.048544                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53127.268977                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53127.268977                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.243097                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53361.243097                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.243097                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53361.243097                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            946045                       # number of replacements
system.cpu.dcache.tags.tagsinuse          3618.157159                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            26265609                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            950141                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             27.643907                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle       20427116250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst  3618.157159                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst     0.883339                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.883339                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          261                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         2250                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         1585                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          55458945                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         55458945                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst     21596750                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        21596750                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst      4661085                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4661085                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst         3887                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst         3887                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst      26257835                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         26257835                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst     26257835                       # number of overall hits
system.cpu.dcache.overall_hits::total        26257835                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst       914897                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        914897                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst        73896                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        73896                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.inst       988793                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         988793                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst       988793                       # number of overall misses
system.cpu.dcache.overall_misses::total        988793                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst  11909486494                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  11909486494                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst   2342585500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   2342585500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst  14252071994                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  14252071994                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst  14252071994                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  14252071994                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst     22511647                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22511647                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst      4734981                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst         3887                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst         3887                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst     27246628                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     27246628                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst     27246628                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     27246628                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.040641                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.040641                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.015606                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.015606                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst     0.036290                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.036290                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst     0.036290                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.036290                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31701.113727                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31701.113727                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.605268                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14413.605268                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.605268                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14413.605268                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       943269                       # number of writebacks
system.cpu.dcache.writebacks::total            943269                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        11517                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        11517                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        27135                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        27135                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst        38652                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        38652                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst        38652                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        38652                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       903380                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       903380                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        46761                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        46761                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst       950141                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       950141                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst       950141                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       950141                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   9958325256                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   9958325256                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   1334905750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   1334905750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  11293231006                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  11293231006                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  11293231006                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  11293231006                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.040129                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040129                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009876                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009876                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.034872                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.034872                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.034872                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.034872                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.416651                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.416651                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.847475                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.847475                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.847475                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.847475                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------