path: root/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.058174                       # Number of seconds simulated
sim_ticks                                 58174017500                       # Number of ticks simulated
final_tick                                58174017500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 129950                       # Simulator instruction rate (inst/s)
host_op_rate                                   130597                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               83449704                       # Simulator tick rate (ticks/s)
host_mem_usage                                 446256                       # Number of bytes of host memory used
host_seconds                                   697.11                       # Real time elapsed on the host
sim_insts                                    90589799                       # Number of instructions simulated
sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             44480                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data             49984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher       930560                       # Number of bytes read from this memory
system.physmem.bytes_read::total              1025024                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        44480                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           44480                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks        26560                       # Number of bytes written to this memory
system.physmem.bytes_written::total             26560                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                695                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                781                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher        14540                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 16016                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks             415                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                  415                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               764603                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               859215                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     15996145                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                17619962                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          764603                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             764603                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks            456561                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                 456561                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks            456561                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              764603                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              859215                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     15996145                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               18076524                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         16016                       # Number of read requests accepted
system.physmem.writeReqs                          415                       # Number of write requests accepted
system.physmem.readBursts                       16016                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                        415                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  1011776                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     13248                       # Total number of bytes read from write queue
system.physmem.bytesWritten                     25088                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   1025024                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                  26560                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      207                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       5                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                1014                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 876                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 957                       # Per bank write bursts
system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
system.physmem.perBankRdBursts::4                1065                       # Per bank write bursts
system.physmem.perBankRdBursts::5                1144                       # Per bank write bursts
system.physmem.perBankRdBursts::6                1126                       # Per bank write bursts
system.physmem.perBankRdBursts::7                1093                       # Per bank write bursts
system.physmem.perBankRdBursts::8                1040                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
system.physmem.perBankRdBursts::10                938                       # Per bank write bursts
system.physmem.perBankRdBursts::11                903                       # Per bank write bursts
system.physmem.perBankRdBursts::12                912                       # Per bank write bursts
system.physmem.perBankRdBursts::13                888                       # Per bank write bursts
system.physmem.perBankRdBursts::14                938                       # Per bank write bursts
system.physmem.perBankRdBursts::15                925                       # Per bank write bursts
system.physmem.perBankWrBursts::0                  43                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   7                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   6                       # Per bank write bursts
system.physmem.perBankWrBursts::4                  10                       # Per bank write bursts
system.physmem.perBankWrBursts::5                  44                       # Per bank write bursts
system.physmem.perBankWrBursts::6                  74                       # Per bank write bursts
system.physmem.perBankWrBursts::7                  25                       # Per bank write bursts
system.physmem.perBankWrBursts::8                  45                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                 10                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  5                       # Per bank write bursts
system.physmem.perBankWrBursts::12                 11                       # Per bank write bursts
system.physmem.perBankWrBursts::13                 32                       # Per bank write bursts
system.physmem.perBankWrBursts::14                 48                       # Per bank write bursts
system.physmem.perBankWrBursts::15                 32                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     58173860500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   16016                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                    415                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     10954                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2453                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       522                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       347                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       301                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       287                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       308                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       284                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       291                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        58                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         1930                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      536.107772                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     304.077638                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     432.159932                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            590     30.57%     30.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          221     11.45%     42.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           97      5.03%     47.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           69      3.58%     50.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           71      3.68%     54.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           49      2.54%     56.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           51      2.64%     59.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           42      2.18%     61.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          740     38.34%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           1930                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples            22                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean       717.636364                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       31.597036                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     3209.686449                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511              21     95.45%     95.45% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359            1      4.55%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total              22                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples            22                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.818182                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.808292                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.588490                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16                  2      9.09%      9.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                 20     90.91%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total              22                       # Writes before turning the bus around for reads
system.physmem.totQLat                      169690298                       # Total ticks spent queuing
system.physmem.totMemAccLat                 466109048                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     79045000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10733.78                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29483.78                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          17.39                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.43                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       17.62                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.46                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.14                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.31                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        17.30                       # Average write queue length when enqueuing
system.physmem.readRowHits                      14150                       # Number of row buffer hits during reads
system.physmem.writeRowHits                       110                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.51                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  26.83                       # Row buffer hit rate for writes
system.physmem.avgGap                      3540494.22                       # Average gap between requests
system.physmem.pageHitRate                      87.92                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                    7832160                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    4273500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  64506000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                  1289520                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             3799451760                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             2476215945                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            32730681000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              39084249885                       # Total energy per rank (pJ)
system.physmem_0.averagePower              671.881619                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    54439969881                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1942460000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      1788917619                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                    6667920                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    3638250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  58507800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                  1146960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             3799451760                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             2448182205                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            32755263750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              39072858645                       # Total energy per rank (pJ)
system.physmem_1.averagePower              671.685955                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    54482617084                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1942460000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      1747288416                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                28257086                       # Number of BP lookups
system.cpu.branchPred.condPredicted          23279263                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            837830                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             11842064                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                11784394                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             99.513007                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                   75760                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 88                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  442                       # Number of system calls
system.cpu.numCycles                        116348036                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles             748817                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      134985012                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    28257086                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           11860154                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     114705506                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1679063                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 1007                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles          831                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  32301197                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   575                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          116295692                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.165959                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.319053                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 58725363     50.50%     50.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 13942075     11.99%     62.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  9230802      7.94%     70.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 34397452     29.58%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            116295692                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.242867                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.160183                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                  8839821                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              64036145                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  33034290                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               9558144                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 827292                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              4101248                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 12341                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              114428571                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               1996975                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 827292                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 15280810                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                49891272                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         109349                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  35424705                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              14762264                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              110897410                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               1415598                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              11131669                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1144033                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1526935                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                 476507                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           129954934                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             483266147                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        119472382                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               420                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 22642015                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               4363                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           4358                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  21506426                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             26812625                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             5349337                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads            517439                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           253975                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  109689181                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                8247                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 101387653                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1074699                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        18656398                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     41685630                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             29                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     116295692                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.871809                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.989320                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            54655211     47.00%     47.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            31361654     26.97%     73.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            22008607     18.92%     92.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7072409      6.08%     98.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             1197497      1.03%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 314      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       116295692                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 9793566     48.69%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     50      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                13      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                9616917     47.81%     96.50% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                703878      3.50%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              71983899     71.00%     71.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                10709      0.01%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               2      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              53      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc            124      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             24343332     24.01%     95.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             5049532      4.98%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              101387653                       # Type of FU issued
system.cpu.iq.rate                           0.871417                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    20114424                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.198391                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          340259668                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         128354519                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     99625011                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 453                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                612                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          114                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              121501841                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     236                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           290489                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4336714                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         1516                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation         1340                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       604493                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         7566                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        130818                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 827292                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 8117300                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                684188                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           109710095                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              26812625                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              5349337                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               4359                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 178987                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                342189                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents           1340                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         436578                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       412874                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               849452                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             100126762                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              23806670                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1260891                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         12667                       # number of nop insts executed
system.cpu.iew.exec_refs                     28724538                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 20624131                       # Number of branches executed
system.cpu.iew.exec_stores                    4917868                       # Number of stores executed
system.cpu.iew.exec_rate                     0.860580                       # Inst execution rate
system.cpu.iew.wb_sent                       99709725                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      99625125                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  59703453                       # num instructions producing a value
system.cpu.iew.wb_consumers                  95545682                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.856268                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.624868                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        17384546                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            825591                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    113603530                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.801504                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.738080                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     77180399     67.94%     67.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     18615023     16.39%     84.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      7150693      6.29%     90.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      3466326      3.05%     93.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1641860      1.45%     95.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       544762      0.48%     95.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       704352      0.62%     96.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       180030      0.16%     96.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      4120085      3.63%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    113603530                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             90602408                       # Number of instructions committed
system.cpu.commit.committedOps               91053639                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27220755                       # Number of memory references committed
system.cpu.commit.loads                      22475911                       # Number of loads committed
system.cpu.commit.membars                        3888                       # Number of memory barriers committed
system.cpu.commit.branches                   18732305                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  72326352                       # Number of committed integer instructions.
system.cpu.commit.function_calls                56148                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         63822387     70.09%     70.09% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           10474      0.01%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            6      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc           15      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            2      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        22475911     24.68%     94.79% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        4744844      5.21%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          91053639                       # Class of committed instruction
system.cpu.commit.bw_lim_events               4120085                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    217915896                       # The number of ROB reads
system.cpu.rob.rob_writes                   219569120                       # The number of ROB writes
system.cpu.timesIdled                             587                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           52344                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    90589799                       # Number of Instructions Simulated
system.cpu.committedOps                      91041030                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.284339                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.284339                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.778610                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.778610                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                108111439                       # number of integer regfile reads
system.cpu.int_regfile_writes                58700930                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        59                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       95                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 369063438                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 58693153                       # number of cc regfile writes
system.cpu.misc_regfile_reads                28414947                       # number of misc regfile reads
system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           5470195                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.789215                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            18252015                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           5470707                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              3.336317                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          35049500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.789215                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999588                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999588                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          343                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          169                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          61908703                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         61908703                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     13889937                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13889937                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4353797                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4353797                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data          522                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total           522                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         3872                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         3872                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      18243734                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18243734                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     18244256                       # number of overall hits
system.cpu.dcache.overall_hits::total        18244256                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      9585777                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       9585777                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       381184                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       381184                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            7                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            7                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           15                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           15                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      9966961                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9966961                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9966968                       # number of overall misses
system.cpu.dcache.overall_misses::total       9966968                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  88717689000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  88717689000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   3954782792                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   3954782792                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       296500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       296500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  92672471792                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  92672471792                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  92672471792                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  92672471792                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23475714                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23475714                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data          529                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total          529                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     28210695                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     28210695                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     28211224                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     28211224                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408327                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.408327                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080504                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.080504                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.013233                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.013233                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003859                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003859                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.353304                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.353304                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.353298                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.353298                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9255.138003                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total  9255.138003                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10374.996831                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10374.996831                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data  9297.966731                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total  9297.966731                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data  9297.960201                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total  9297.960201                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       330068                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        99317                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            121445                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           12837                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.717839                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     7.736777                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      5436552                       # number of writebacks
system.cpu.dcache.writebacks::total           5436552                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4337556                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      4337556                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158702                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       158702                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           15                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           15                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      4496258                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      4496258                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      4496258                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      4496258                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248221                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5248221                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222482                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       222482                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      5470703                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      5470703                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      5470707                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      5470707                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43246268500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  43246268500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2278267197                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2278267197                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       214500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       214500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45524535697                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  45524535697                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45524750197                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  45524750197                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223560                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223560                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046987                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046987                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007561                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007561                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193923                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.193923                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193920                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.193920                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8240.176719                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8240.176719                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10240.231556                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10240.231556                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53625                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53625                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8321.514748                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total  8321.514748                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8321.547873                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total  8321.547873                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements               451                       # number of replacements
system.cpu.icache.tags.tagsinuse           428.509106                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            32300030                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               910                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          35494.538462                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   428.509106                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.836932                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.836932                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          459                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           22                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          331                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.896484                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          64603278                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         64603278                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     32300030                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        32300030                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      32300030                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         32300030                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     32300030                       # number of overall hits
system.cpu.icache.overall_hits::total        32300030                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1154                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1154                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1154                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1154                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1154                       # number of overall misses
system.cpu.icache.overall_misses::total          1154                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     61388483                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     61388483                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     61388483                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     61388483                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     61388483                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     61388483                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     32301184                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     32301184                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     32301184                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     32301184                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     32301184                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     32301184                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000036                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000036                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000036                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000036                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53196.259099                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 53196.259099                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53196.259099                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 53196.259099                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53196.259099                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 53196.259099                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        19635                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          107                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               227                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    86.497797                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    21.400000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          244                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          244                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          244                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          244                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          244                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          244                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          910                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          910                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          910                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          910                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          910                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50524487                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     50524487                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50524487                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     50524487                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50524487                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     50524487                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000028                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000028                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55521.414286                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55521.414286                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55521.414286                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 55521.414286                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55521.414286                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 55521.414286                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued      4525641                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified      5296015                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit       665258                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage     14074393                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements              580                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        12072.245633                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           10689052                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs            16020                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs           667.231710                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 11065.307975                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   570.003280                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   229.604220                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   207.330158                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.675373                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.034790                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.014014                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.012654                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.736831                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          262                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        15178                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           23                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3            8                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4          220                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          972                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1056                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13076                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.015991                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.926392                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        175272106                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       175272106                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      5436552                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      5436552                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       226009                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       226009                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          213                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total          213                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5243702                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      5243702                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst          213                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      5469711                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         5469924                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst          213                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      5469711                       # number of overall hits
system.cpu.l2cache.overall_hits::total        5469924                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data          509                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          509                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          697                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          697                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data          487                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total          487                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          697                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          996                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          1693                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          697                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          996                       # number of overall misses
system.cpu.l2cache.overall_misses::total         1693                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     35228000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     35228000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     48202000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     48202000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     30204500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total     30204500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     48202000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     65432500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    113634500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     48202000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     65432500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    113634500                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      5436552                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      5436552                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       226518                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       226518                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          910                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          910                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      5244189                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      5244189                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          910                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      5470707                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      5471617                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          910                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      5470707                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      5471617                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002247                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.002247                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.765934                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.765934                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000093                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000093                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.765934                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.000182                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.000309                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.765934                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.000182                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.000309                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69210.216110                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69210.216110                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 69156.384505                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 69156.384505                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 62021.560575                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 62021.560575                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69156.384505                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65695.281124                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 67120.200827                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69156.384505                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65695.281124                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 67120.200827                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks          415                       # number of writebacks
system.cpu.l2cache.writebacks::total              415                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          169                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total          169                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           46                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           46                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          215                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          217                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          215                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          217                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           11                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total           11                       # number of CleanEvict MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        20231                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total        20231                       # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          340                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          340                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          695                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          695                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          441                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total          441                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          695                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          781                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         1476                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          695                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          781                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        20231                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        21707                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    860658985                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    860658985                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     26049500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     26049500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43944500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43944500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     25180500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     25180500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43944500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     51230000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     95174500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43944500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     51230000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    860658985                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    955833485                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001501                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001501                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.763736                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000084                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000143                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.000270                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.763736                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000143                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.003967                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 42541.593841                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 42541.593841                       # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76616.176471                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76616.176471                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63229.496403                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63229.496403                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 57098.639456                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 57098.639456                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63229.496403                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65595.390525                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64481.368564                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63229.496403                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65595.390525                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 42541.593841                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44033.421707                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp       5245099                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      5436967                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        31344                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq        22118                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       226518                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       226518                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          910                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244189                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2259                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16408706                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          16410965                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58240                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    698064576                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          698122816                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       22698                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     10964961                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.002070                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.045451                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1           10942263     99.79%     99.79% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2              22698      0.21%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       10964961                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    10907683500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization         18.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1366996                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    8206064991                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization         14.1                       # Layer utilization (%)
system.membus.trans_dist::ReadResp              15676                       # Transaction distribution
system.membus.trans_dist::Writeback               415                       # Transaction distribution
system.membus.trans_dist::CleanEvict              117                       # Transaction distribution
system.membus.trans_dist::ReadExReq               340                       # Transaction distribution
system.membus.trans_dist::ReadExResp              340                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         15676                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        32564                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  32564                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1051584                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 1051584                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples             16548                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                   16548    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total               16548                       # Request fanout histogram
system.membus.reqLayer0.occupancy            27912645                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           83778508                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------