path: root/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.058681                       # Number of seconds simulated
sim_ticks                                 58681066500                       # Number of ticks simulated
final_tick                                58681066500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 243006                       # Simulator instruction rate (inst/s)
host_op_rate                                   244216                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              157411271                       # Simulator tick rate (ticks/s)
host_mem_usage                                 492224                       # Number of bytes of host memory used
host_seconds                                   372.79                       # Real time elapsed on the host
sim_insts                                    90589799                       # Number of instructions simulated
sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             44800                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            219520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher       922368                       # Number of bytes read from this memory
system.physmem.bytes_read::total              1186688                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        44800                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           44800                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks         6784                       # Number of bytes written to this memory
system.physmem.bytes_written::total              6784                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                700                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               3430                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher        14412                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 18542                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks             106                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                  106                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               763449                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3740900                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     15718324                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                20222673                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          763449                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             763449                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks            115608                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                 115608                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks            115608                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              763449                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3740900                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     15718324                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               20338281                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         18543                       # Number of read requests accepted
system.physmem.writeReqs                          106                       # Number of write requests accepted
system.physmem.readBursts                       18543                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                        106                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  1180544                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6208                       # Total number of bytes read from write queue
system.physmem.bytesWritten                      4608                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   1186752                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                   6784                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       97                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       6                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                3245                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 921                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 954                       # Per bank write bursts
system.physmem.perBankRdBursts::3                1031                       # Per bank write bursts
system.physmem.perBankRdBursts::4                1065                       # Per bank write bursts
system.physmem.perBankRdBursts::5                1115                       # Per bank write bursts
system.physmem.perBankRdBursts::6                1093                       # Per bank write bursts
system.physmem.perBankRdBursts::7                1100                       # Per bank write bursts
system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
system.physmem.perBankRdBursts::10                933                       # Per bank write bursts
system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
system.physmem.perBankRdBursts::12                904                       # Per bank write bursts
system.physmem.perBankRdBursts::13                895                       # Per bank write bursts
system.physmem.perBankRdBursts::14               1401                       # Per bank write bursts
system.physmem.perBankRdBursts::15                904                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   2                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                  12                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   8                       # Per bank write bursts
system.physmem.perBankWrBursts::6                  10                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   7                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   1                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  1                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  5                       # Per bank write bursts
system.physmem.perBankWrBursts::13                 12                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  8                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  6                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     58681058000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   18543                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                    106                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     12536                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      3413                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       499                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       407                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       316                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       301                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       299                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       297                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       278                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       100                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         2972                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      398.104980                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     217.970166                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     405.874685                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            839     28.23%     28.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          987     33.21%     61.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           89      2.99%     64.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           64      2.15%     66.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           64      2.15%     68.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           65      2.19%     70.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           54      1.82%     72.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           55      1.85%     74.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          755     25.40%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           2972                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples             4                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      4544.500000                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean     1447.547305                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     7502.381200                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511               2     50.00%     50.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-2047            1     25.00%     75.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-15871            1     25.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total               4                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples             4                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean               18                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.000000                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                  4    100.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total               4                       # Writes before turning the bus around for reads
system.physmem.totQLat                      829373528                       # Total ticks spent queuing
system.physmem.totMemAccLat                1175236028                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     92230000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       44962.24                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  63712.24                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          20.12                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.08                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       20.22                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.12                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.16                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.16                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        19.34                       # Average write queue length when enqueuing
system.physmem.readRowHits                      15527                       # Number of row buffer hits during reads
system.physmem.writeRowHits                        11                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   84.18                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  11.00                       # Row buffer hit rate for writes
system.physmem.avgGap                      3146606.15                       # Average gap between requests
system.physmem.pageHitRate                      83.78                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                   15943620                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    8459055                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  75134220                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                   203580                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           1849451760.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy              458311920                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy               99516480                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy        3997068570                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        3182851200                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy        10077393330                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy              19767987555                       # Total energy per rank (pJ)
system.physmem_0.averagePower              336.871642                       # Core power per rank (mW)
system.physmem_0.totalIdleTime            57408712347                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      196273000                       # Time in different power states
system.physmem_0.memoryStateTime::REF       786774000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF    40354533250                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN   8288648060                       # Time in different power states
system.physmem_0.memoryStateTime::ACT       289307153                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN   8765531037                       # Time in different power states
system.physmem_1.actEnergy                    5333580                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    2819685                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  56563080                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                   172260                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           259378080.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy              131548590                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy               14205120                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy         785395590                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy         262919520                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy        13470232590                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy              14988765045                       # Total energy per rank (pJ)
system.physmem_1.averagePower              255.427603                       # Core power per rank (mW)
system.physmem_1.totalIdleTime            58353780091                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE       23548250                       # Time in different power states
system.physmem_1.memoryStateTime::REF       110212000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF    55948105250                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN    684663397                       # Time in different power states
system.physmem_1.memoryStateTime::ACT       192205159                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN   1722332444                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                28234239                       # Number of BP lookups
system.cpu.branchPred.condPredicted          23266690                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            835421                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             11829840                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                11748052                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             99.308630                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                   74543                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 96                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups           27224                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits              25476                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             1748                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted          245                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  442                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON     58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        117362134                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles             746504                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      134908625                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    28234239                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           11848071                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     115710996                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1674249                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  874                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles          948                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  32275841                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   569                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          117296446                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.155292                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.317650                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 59759710     50.95%     50.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 13934020     11.88%     62.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  9230571      7.87%     70.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 34372145     29.30%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            117296446                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.240574                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.149507                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                  8834504                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              65062525                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  33013030                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               9560979                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 825408                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              4097904                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 11817                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              114396314                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               1984657                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 825408                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 15270391                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                50319403                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         113009                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  35408802                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              15359433                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              110873352                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               1412133                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              11133960                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1550028                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                2088318                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                 507009                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           129946854                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             483157007                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        119448195                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               430                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 22633935                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               4409                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           4401                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  21513701                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             26805540                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             5347415                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads            519015                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           253842                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  109668195                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                8283                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 101366364                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1074602                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        18635448                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     41675725                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             65                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     117296446                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.864190                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.988217                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            55661536     47.45%     47.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            31364227     26.74%     74.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            22008293     18.76%     92.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7064324      6.02%     98.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             1197751      1.02%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 315      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       117296446                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 9780929     48.66%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     50      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                13      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.66% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                9614642     47.84%     96.50% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                702971      3.50%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead                 3      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite               24      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              71970702     71.00%     71.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                10697      0.01%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               2      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              57      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc            124      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             24337480     24.01%     95.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             5047270      4.98%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead               8      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite             22      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              101366364                       # Type of FU issued
system.cpu.iq.rate                           0.863706                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    20098632                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.198277                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          341201935                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         128312613                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     99607782                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 473                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                622                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          118                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              121464746                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     250                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           288157                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4329629                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         1502                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation         1344                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       602571                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         7583                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        130792                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 825408                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 8297291                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                773487                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           109689301                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              26805540                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              5347415                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               4395                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 182523                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                427569                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents           1344                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         435014                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       412394                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               847408                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             100110032                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              23803163                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1256332                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         12823                       # number of nop insts executed
system.cpu.iew.exec_refs                     28718949                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 20621210                       # Number of branches executed
system.cpu.iew.exec_stores                    4915786                       # Number of stores executed
system.cpu.iew.exec_rate                     0.853001                       # Inst execution rate
system.cpu.iew.wb_sent                       99693474                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      99607900                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  59692176                       # num instructions producing a value
system.cpu.iew.wb_consumers                  95528763                       # num instructions consuming a value
system.cpu.iew.wb_rate                       0.848723                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.624861                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        17363908                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            823705                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    114608461                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.794476                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.731976                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     78183874     68.22%     68.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     18612814     16.24%     84.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      7153278      6.24%     90.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      3469165      3.03%     93.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1644308      1.43%     95.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       541542      0.47%     95.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       703493      0.61%     96.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       179022      0.16%     96.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      4120965      3.60%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    114608461                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             90602408                       # Number of instructions committed
system.cpu.commit.committedOps               91053639                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27220755                       # Number of memory references committed
system.cpu.commit.loads                      22475911                       # Number of loads committed
system.cpu.commit.membars                        3888                       # Number of memory barriers committed
system.cpu.commit.branches                   18732305                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  72326352                       # Number of committed integer instructions.
system.cpu.commit.function_calls                56148                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         63822387     70.09%     70.09% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           10474      0.01%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            6      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc           15      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            2      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        22475905     24.68%     94.79% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        4744822      5.21%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead            6      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite           22      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          91053639                       # Class of committed instruction
system.cpu.commit.bw_lim_events               4120965                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    218899309                       # The number of ROB reads
system.cpu.rob.rob_writes                   219523661                       # The number of ROB writes
system.cpu.timesIdled                             582                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           65688                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    90589799                       # Number of Instructions Simulated
system.cpu.committedOps                      91041030                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.295534                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.295534                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.771883                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.771883                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                108098001                       # number of integer regfile reads
system.cpu.int_regfile_writes                58691976                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       98                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 369004563                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 58686890                       # number of cc regfile writes
system.cpu.misc_regfile_reads                28409682                       # number of misc regfile reads
system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           5470632                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.769242                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            18249828                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           5471144                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              3.335651                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          38122500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.769242                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999549                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999549                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          334                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          61906996                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         61906996                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     13887361                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13887361                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4354163                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4354163                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data          522                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total           522                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         3873                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         3873                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      18241524                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18241524                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     18242046                       # number of overall hits
system.cpu.dcache.overall_hits::total        18242046                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      9587281                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       9587281                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       380818                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       380818                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            7                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            7                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           14                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           14                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      9968099                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9968099                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9968106                       # number of overall misses
system.cpu.dcache.overall_misses::total       9968106                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  89375617500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  89375617500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   4089956224                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   4089956224                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       302000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       302000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  93465573724                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  93465573724                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  93465573724                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  93465573724                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23474642                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23474642                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data          529                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total          529                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     28209623                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     28209623                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     28210152                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     28210152                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408410                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.408410                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080427                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.080427                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.013233                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.013233                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003602                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003602                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.353358                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.353358                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.353352                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.353352                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9322.311248                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total  9322.311248                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10739.923596                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10739.923596                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data  9376.469247                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total  9376.469247                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data  9376.462662                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total  9376.462662                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       331655                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       128757                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            121530                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           12840                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.728997                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    10.027804                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      5470632                       # number of writebacks
system.cpu.dcache.writebacks::total           5470632                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4338725                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      4338725                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158229                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       158229                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           14                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           14                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      4496954                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      4496954                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      4496954                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      4496954                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248556                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5248556                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222589                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       222589                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      5471145                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      5471145                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      5471149                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      5471149                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43819499500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  43819499500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2297613115                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2297613115                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       235500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       235500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  46117112615                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  46117112615                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  46117348115                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  46117348115                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223584                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223584                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047009                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047009                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007561                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007561                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193946                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.193946                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193943                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.193943                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8348.867670                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8348.867670                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10322.222190                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10322.222190                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        58875                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        58875                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8429.151963                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total  8429.151963                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8429.188844                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total  8429.188844                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements               448                       # number of replacements
system.cpu.icache.tags.tagsinuse           427.601453                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            32274679                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               906                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          35623.266004                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   427.601453                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.835159                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.835159                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          458                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           19                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          335                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.894531                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          64552564                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         64552564                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     32274679                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        32274679                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      32274679                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         32274679                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     32274679                       # number of overall hits
system.cpu.icache.overall_hits::total        32274679                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1150                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1150                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1150                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1150                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1150                       # number of overall misses
system.cpu.icache.overall_misses::total          1150                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     79102980                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     79102980                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     79102980                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     79102980                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     79102980                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     79102980                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     32275829                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     32275829                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     32275829                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     32275829                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     32275829                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     32275829                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000036                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000036                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000036                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000036                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68785.200000                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 68785.200000                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68785.200000                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 68785.200000                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68785.200000                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 68785.200000                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        21255                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          760                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               230                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               6                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    92.413043                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets   126.666667                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks          448                       # number of writebacks
system.cpu.icache.writebacks::total               448                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          243                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          243                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          243                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          243                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          243                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          243                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          907                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          907                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          907                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          907                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          907                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          907                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     60408984                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     60408984                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     60408984                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     60408984                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     60408984                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     60408984                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000028                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000028                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66603.069460                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66603.069460                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66603.069460                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 66603.069460                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66603.069460                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66603.069460                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued      4986166                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified      5293297                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit       266998                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage     14074663                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements              148                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        11219.998633                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            5292017                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs            14707                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs           359.829809                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 11153.900503                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    66.098130                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.680780                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.004034                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.684814                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022           64                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        14495                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4           55                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          466                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3398                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9680                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          119                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          832                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.003906                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.884705                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        180526200                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       180526200                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks      5457195                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      5457195                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        11011                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        11011                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       225669                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       225669                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          205                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total          205                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5241856                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      5241856                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst          205                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      5467525                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         5467730                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst          205                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      5467525                       # number of overall hits
system.cpu.l2cache.overall_hits::total        5467730                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data          501                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          501                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          702                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          702                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data         3118                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total         3118                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          702                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         3619                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          4321                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          702                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         3619                       # number of overall misses
system.cpu.l2cache.overall_misses::total         4321                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       106500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       106500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     63936500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     63936500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     58121500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     58121500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    619277500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total    619277500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     58121500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    683214000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    741335500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     58121500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    683214000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    741335500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      5457195                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      5457195                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        11011                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        11011                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data            5                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            5                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       226170                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       226170                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          907                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          907                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      5244974                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      5244974                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          907                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      5471144                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      5472051                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          907                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      5471144                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      5472051                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002215                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.002215                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.773980                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.773980                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000594                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000594                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.773980                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.000661                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.000790                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.773980                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.000661                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.000790                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        21300                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        21300                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127617.764471                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127617.764471                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82794.159544                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82794.159544                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198613.694676                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198613.694676                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82794.159544                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188785.299807                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 171565.725526                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82794.159544                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188785.299807                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 171565.725526                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.unused_prefetches                3                       # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks          106                       # number of writebacks
system.cpu.l2cache.writebacks::total              106                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          158                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total          158                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           30                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           30                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          188                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          189                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          188                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          189                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       316628                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       316628                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          343                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          343                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          701                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          701                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         3088                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total         3088                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          701                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         3431                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         4132                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          701                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         3431                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       316628                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       320760                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher   1087453464                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total   1087453464                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        76500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        76500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     45609000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     45609000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     53854500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     53854500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    591148000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    591148000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     53854500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    636757000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    690611500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     53854500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    636757000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher   1087453464                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   1778064964                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001517                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001517                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.772878                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.772878                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000589                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000589                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.772878                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000627                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.000755                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.772878                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000627                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.058618                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3434.482939                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  3434.482939                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        15300                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        15300                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 132970.845481                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 132970.845481                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76825.249643                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76825.249643                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 191433.937824                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 191433.937824                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76825.249643                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185589.332556                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167137.342691                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76825.249643                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185589.332556                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3434.482939                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total  5543.287704                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests     10943136                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      5471098                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2874                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops       302216                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops       302215                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp       5245880                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      5457301                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        13885                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict           42                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       318509                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp            6                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq            5                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp            5                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       226170                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       226170                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          907                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244974                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2261                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16412936                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          16415197                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        86656                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    700274048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          700360704                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      318663                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                  7168                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      5790713                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.052689                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.223412                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            5485610     94.73%     94.73% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             305102      5.27%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        5790713                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    10942648026                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization         18.6                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy         9032                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1361495                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    8206721993                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization         14.0                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests         18697                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests         3032                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED  58681066500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp              18200                       # Transaction distribution
system.membus.trans_dist::WritebackDirty          106                       # Transaction distribution
system.membus.trans_dist::CleanEvict               42                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
system.membus.trans_dist::ReadExReq               342                       # Transaction distribution
system.membus.trans_dist::ReadExResp              342                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         18201                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        37239                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  37239                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1193472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 1193472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples             18549                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                   18549    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total               18549                       # Request fanout histogram
system.membus.reqLayer0.occupancy            29669004                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy           97336094                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------