blob: b6a9feb5d59522976361b37b155e97a6977962ba (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.026894 # Number of seconds simulated
sim_ticks 26894328500 # Number of ticks simulated
final_tick 26894328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 165934 # Simulator instruction rate (inst/s)
host_op_rate 167125 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49262466 # Simulator tick rate (ticks/s)
host_mem_usage 394132 # Number of bytes of host memory used
host_seconds 545.94 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated
sim_ops 91240351 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 45184 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory
system.physmem.bytes_read::total 992640 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 45184 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 45184 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 706 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1680057 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 35228840 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 36908897 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1680057 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1680057 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1680057 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 35228840 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 36908897 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15510 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 15510 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 992640 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 992640 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 987 # Per bank write bursts
system.physmem.perBankRdBursts::1 885 # Per bank write bursts
system.physmem.perBankRdBursts::2 942 # Per bank write bursts
system.physmem.perBankRdBursts::3 1029 # Per bank write bursts
system.physmem.perBankRdBursts::4 1048 # Per bank write bursts
system.physmem.perBankRdBursts::5 1105 # Per bank write bursts
system.physmem.perBankRdBursts::6 1078 # Per bank write bursts
system.physmem.perBankRdBursts::7 1080 # Per bank write bursts
system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
system.physmem.perBankRdBursts::9 957 # Per bank write bursts
system.physmem.perBankRdBursts::10 936 # Per bank write bursts
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
system.physmem.perBankRdBursts::12 905 # Per bank write bursts
system.physmem.perBankRdBursts::13 863 # Per bank write bursts
system.physmem.perBankRdBursts::14 876 # Per bank write bursts
system.physmem.perBankRdBursts::15 896 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 26894128500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 15510 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 10369 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4857 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1366 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 726.489019 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 530.637647 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 387.552146 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 153 11.20% 11.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 146 10.69% 21.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 54 3.95% 25.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 65 4.76% 30.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 57 4.17% 34.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 41 3.00% 37.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 35 2.56% 40.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 33 2.42% 42.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 782 57.25% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1366 # Bytes accessed per row activation
system.physmem.totQLat 88775250 # Total ticks spent queuing
system.physmem.totMemAccLat 379587750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77550000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5723.74 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24473.74 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.29 # Data bus utilization in percentage
system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 14143 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 1733986.36 # Average gap between requests
system.physmem.pageHitRate 91.19 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 24303280500 # Time in different power states
system.physmem.memoryStateTime::REF 898040000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 1692660750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 36908897 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 972 # Transaction distribution
system.membus.trans_dist::ReadResp 972 # Transaction distribution
system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31022 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31022 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992640 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 992640 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 992640 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 18401000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 145166999 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 27364118 # Number of BP lookups
system.cpu.branchPred.condPredicted 22575249 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 843312 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 11626081 # Number of BTB lookups
system.cpu.branchPred.BTBHits 11546341 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 99.314128 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 70079 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 187 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 53788658 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 14474692 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 130915195 # Number of instructions fetch has processed
system.cpu.fetch.Branches 27364118 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11616420 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 24576695 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 5106515 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 9886759 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 14156505 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 349331 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 53187301 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.478661 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.235073 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 28648969 53.86% 53.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3469200 6.52% 60.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2052434 3.86% 64.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1567853 2.95% 67.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1679873 3.16% 70.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 3021837 5.68% 76.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1566641 2.95% 78.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1116795 2.10% 81.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 10063699 18.92% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 53187301 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.508734 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.433881 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 16310855 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 8657573 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 23455900 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 522552 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4240421 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4543490 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 8671 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 129206748 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 42514 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4240421 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 17921369 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2850180 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 191379 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 22351654 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5632298 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 126131712 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1889841 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 3251328 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 563418 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 3246 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 146876533 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 549573070 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 512042051 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 826 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 39462347 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 4633 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 4631 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 9072079 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 30275485 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5599467 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2184620 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1363504 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 120806561 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 8485 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 105954089 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 91175 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 29372689 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 73925597 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 267 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 53187301 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.992094 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.919550 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 15526622 29.19% 29.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 10753574 20.22% 49.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8641028 16.25% 65.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6157106 11.58% 77.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 5949684 11.19% 88.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2742880 5.16% 93.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2429206 4.57% 98.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 538839 1.01% 99.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 448362 0.84% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 53187301 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 44574 8.99% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 27 0.01% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.99% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 174239 35.13% 44.13% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 277108 55.87% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 75094311 70.87% 70.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 10550 0.01% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 140 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 196 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 25720178 24.27% 95.16% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5128709 4.84% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 105954089 # Type of FU issued
system.cpu.iq.rate 1.969822 # Inst issue rate
system.cpu.iq.fu_busy_cnt 495948 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.004681 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 265681854 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 150192687 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 103425723 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 748 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1061 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 319 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 106449666 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 371 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 469381 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 7701519 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 7870 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 6982 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 854623 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 30068 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 4240421 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 731718 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 478226 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 120827778 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 309730 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 30275485 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 5599467 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 4597 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 72415 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 359917 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 6982 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 447833 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 447193 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 895026 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 104954211 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25387781 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 999878 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 12732 # number of nop insts executed
system.cpu.iew.exec_refs 30458601 # number of memory reference insts executed
system.cpu.iew.exec_branches 21526378 # Number of branches executed
system.cpu.iew.exec_stores 5070820 # Number of stores executed
system.cpu.iew.exec_rate 1.951233 # Inst execution rate
system.cpu.iew.wb_sent 103717343 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 103426042 # cumulative count of insts written-back
system.cpu.iew.wb_producers 62672484 # num instructions producing a value
system.cpu.iew.wb_consumers 105780863 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.922823 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.592475 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 29588025 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 834722 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 48946880 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.864326 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.553843 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 19590544 40.02% 40.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 13003525 26.57% 66.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4154420 8.49% 75.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3492472 7.14% 82.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1473630 3.01% 85.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 727145 1.49% 86.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 923215 1.89% 88.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 261788 0.53% 89.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5320141 10.87% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 48946880 # Number of insts commited each cycle
system.cpu.commit.committedInsts 90602407 # Number of instructions committed
system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 27318810 # Number of memory references committed
system.cpu.commit.loads 22573966 # Number of loads committed
system.cpu.commit.membars 3888 # Number of memory barriers committed
system.cpu.commit.branches 18732304 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 63923653 70.05% 70.05% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.06% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 22573966 24.74% 94.80% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 4744844 5.20% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 91252960 # Class of committed instruction
system.cpu.commit.bw_lim_events 5320141 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 164461990 # The number of ROB reads
system.cpu.rob.rob_writes 245943119 # The number of ROB writes
system.cpu.timesIdled 58216 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 601357 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.593761 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.593761 # CPI: Total CPI of All Threads
system.cpu.ipc 1.684180 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.684180 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 499033245 # number of integer regfile reads
system.cpu.int_regfile_writes 121427335 # number of integer regfile writes
system.cpu.fp_regfile_reads 166 # number of floating regfile reads
system.cpu.fp_regfile_writes 402 # number of floating regfile writes
system.cpu.misc_regfile_reads 29301616 # number of misc regfile reads
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
system.cpu.toL2Bus.throughput 4500548582 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 907410 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 907410 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 942895 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 40933 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 40933 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1463 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838119 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2839582 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120992384 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 121039168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 121039168 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 1888514500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1215999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1424171240 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
system.cpu.icache.tags.replacements 3 # number of replacements
system.cpu.icache.tags.tagsinuse 631.006365 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 14155509 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 731 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 19364.581395 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 631.006365 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.308109 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.308109 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 728 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.355469 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 28313740 # Number of tag accesses
system.cpu.icache.tags.data_accesses 28313740 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 14155509 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14155509 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14155509 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 14155509 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 14155509 # number of overall hits
system.cpu.icache.overall_hits::total 14155509 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 995 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 995 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 995 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 995 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 995 # number of overall misses
system.cpu.icache.overall_misses::total 995 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 67178998 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 67178998 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 67178998 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 67178998 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 67178998 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 67178998 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 14156504 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 14156504 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 14156504 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 14156504 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 14156504 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 14156504 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67516.580905 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 67516.580905 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 67516.580905 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 67516.580905 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 593 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 59.300000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 263 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 263 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 263 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 263 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 263 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 732 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 732 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 732 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 732 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 732 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 732 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50814250 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 50814250 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50814250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 50814250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50814250 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 50814250 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69418.374317 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69418.374317 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69418.374317 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 69418.374317 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69418.374317 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 69418.374317 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 10751.524012 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1834202 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15494 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 118.381438 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 9904.575959 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 617.996997 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 228.951056 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.302264 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018860 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006987 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.328110 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15494 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1306 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13614 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.472839 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15186331 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15186331 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 906402 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 906426 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 942895 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 942895 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26395 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26395 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 932797 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 932821 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 932797 # number of overall hits
system.cpu.l2cache.overall_hits::total 932821 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 707 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 276 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 983 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 707 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 14814 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15521 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 707 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14814 # number of overall misses
system.cpu.l2cache.overall_misses::total 15521 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49834500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21050250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 70884750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 978125750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 978125750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 49834500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 999176000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1049010500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 49834500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 999176000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1049010500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 731 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 906678 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 907409 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 942895 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 942895 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 40933 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 40933 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 731 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 947611 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 948342 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 731 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 947611 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 948342 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967168 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000304 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001083 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.355166 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.355166 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967168 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015633 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016366 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967168 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015633 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016366 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70487.270156 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76269.021739 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72110.630722 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67280.626634 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67280.626634 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70487.270156 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67448.089645 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 67586.527930 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70487.270156 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67448.089645 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 67586.527930 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 706 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 266 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 972 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 706 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15510 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 706 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15510 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40933250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17118000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58051250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 795610750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 795610750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40933250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 812728750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 853662000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40933250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 812728750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 853662000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000293 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001071 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.355166 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.355166 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016355 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016355 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57979.107649 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64353.383459 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59723.508230 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54726.286284 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54726.286284 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 943515 # number of replacements
system.cpu.dcache.tags.tagsinuse 3673.207831 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 28229578 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 947611 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 29.790260 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 7976079250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3673.207831 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.896779 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.896779 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 452 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 3133 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 60126081 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 60126081 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23676805 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23676805 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4544974 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4544974 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 28221779 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 28221779 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 28221779 # number of overall hits
system.cpu.dcache.overall_hits::total 28221779 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1169644 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1169644 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 190007 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 190007 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1359651 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1359651 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1359651 # number of overall misses
system.cpu.dcache.overall_misses::total 1359651 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13867675477 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 13867675477 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8610605390 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8610605390 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 264500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 264500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 22478280867 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 22478280867 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 22478280867 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 22478280867 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 24846449 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24846449 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 29581430 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 29581430 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 29581430 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 29581430 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047075 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.047075 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040128 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.040128 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002042 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002042 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.045963 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.045963 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.045963 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.045963 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11856.321647 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11856.321647 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45317.306152 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 45317.306152 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33062.500000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33062.500000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16532.390199 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16532.390199 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 136970 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 24472 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.597009 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 942895 # number of writebacks
system.cpu.dcache.writebacks::total 942895 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262958 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 262958 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 149081 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 149081 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 412039 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 412039 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 412039 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 412039 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906686 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 906686 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40926 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 40926 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 947612 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 947612 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 947612 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 947612 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10019308761 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10019308761 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1304642257 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1304642257 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323951018 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11323951018 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323951018 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11323951018 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036492 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036492 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008643 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008643 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.032034 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.032034 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.472557 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.472557 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31878.078898 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31878.078898 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|