path: root/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.058199                       # Number of seconds simulated
sim_ticks                                 58199030500                       # Number of ticks simulated
final_tick                                58199030500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 218368                       # Simulator instruction rate (inst/s)
host_op_rate                                   219455                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              140289424                       # Simulator tick rate (ticks/s)
host_mem_usage                                 534192                       # Number of bytes of host memory used
host_seconds                                   414.85                       # Real time elapsed on the host
sim_insts                                    90589799                       # Number of instructions simulated
sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             44352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data             87616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher       925056                       # Number of bytes read from this memory
system.physmem.bytes_read::total              1057024                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        44352                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           44352                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks        11200                       # Number of bytes written to this memory
system.physmem.bytes_written::total             11200                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                693                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1369                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher        14454                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 16516                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks             175                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                  175                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               762075                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1505455                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     15894698                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                18162227                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          762075                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             762075                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks            192443                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                 192443                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks            192443                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              762075                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1505455                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     15894698                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               18354670                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         16517                       # Number of read requests accepted
system.physmem.writeReqs                          175                       # Number of write requests accepted
system.physmem.readBursts                       16517                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                        175                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  1048320                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8768                       # Total number of bytes read from write queue
system.physmem.bytesWritten                      9216                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   1057088                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                  11200                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      137                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       4                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                1166                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 920                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 953                       # Per bank write bursts
system.physmem.perBankRdBursts::3                1031                       # Per bank write bursts
system.physmem.perBankRdBursts::4                1061                       # Per bank write bursts
system.physmem.perBankRdBursts::5                1122                       # Per bank write bursts
system.physmem.perBankRdBursts::6                1094                       # Per bank write bursts
system.physmem.perBankRdBursts::7                1089                       # Per bank write bursts
system.physmem.perBankRdBursts::8                1025                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
system.physmem.perBankRdBursts::10                933                       # Per bank write bursts
system.physmem.perBankRdBursts::11                900                       # Per bank write bursts
system.physmem.perBankRdBursts::12                903                       # Per bank write bursts
system.physmem.perBankRdBursts::13                900                       # Per bank write bursts
system.physmem.perBankRdBursts::14               1411                       # Per bank write bursts
system.physmem.perBankRdBursts::15                910                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   2                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   6                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   1                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   3                       # Per bank write bursts
system.physmem.perBankWrBursts::5                  16                       # Per bank write bursts
system.physmem.perBankWrBursts::6                  40                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   7                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   2                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  2                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  2                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  2                       # Per bank write bursts
system.physmem.perBankWrBursts::13                 17                       # Per bank write bursts
system.physmem.perBankWrBursts::14                 37                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  7                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     58199022000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   16517                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                    175                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     11454                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2521                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       462                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       397                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       296                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       296                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       316                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       292                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       292                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        54                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         1812                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      582.746137                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     353.648277                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     424.722034                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            448     24.72%     24.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          213     11.75%     36.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           96      5.30%     41.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           72      3.97%     45.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           56      3.09%     48.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           67      3.70%     52.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           61      3.37%     55.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           48      2.65%     58.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          751     41.45%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           1812                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples             8                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      2016.250000                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       98.342741                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     5441.040729                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511               7     87.50%     87.50% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-15871            1     12.50%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total               8                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples             8                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean               18                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.000000                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                  8    100.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total               8                       # Writes before turning the bus around for reads
system.physmem.totQLat                      175730624                       # Total ticks spent queuing
system.physmem.totMemAccLat                 482855624                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     81900000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10728.37                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29478.37                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          18.01                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.16                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       18.16                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.19                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.14                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        14.75                       # Average write queue length when enqueuing
system.physmem.readRowHits                      14651                       # Number of row buffer hits during reads
system.physmem.writeRowHits                        51                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.44                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  29.82                       # Row buffer hit rate for writes
system.physmem.avgGap                      3486641.62                       # Average gap between requests
system.physmem.pageHitRate                      88.83                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                    7658280                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    4178625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  65512200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                   486000                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             3800977440                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             2714701095                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            32535498750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              39129012390                       # Total energy per rank (pJ)
system.physmem_0.averagePower              672.381118                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    54114607553                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1943240000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      2137743447                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                    6017760                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    3283500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  61916400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                   447120                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             3800977440                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             2480426820                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            32741002500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              39094071540                       # Total energy per rank (pJ)
system.physmem_1.averagePower              671.780705                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    54458056984                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1943240000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      1793992016                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                28233538                       # Number of BP lookups
system.cpu.branchPred.condPredicted          23266052                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            835390                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             11829354                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                11747655                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             99.309354                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                   74541                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 92                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups           27216                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits              25478                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             1738                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted          245                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  442                       # Number of system calls
system.cpu.numCycles                        116398062                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles             746143                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      134906479                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    28233538                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           11847674                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     114760827                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1674187                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  911                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles          805                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  32275055                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   562                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          116345779                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.164712                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.318875                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 58810972     50.55%     50.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 13933527     11.98%     62.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  9228064      7.93%     70.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 34373216     29.54%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            116345779                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.242560                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.159010                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                  8834252                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              64111694                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  33013656                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               9560800                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 825377                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              4097950                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 11817                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              114395383                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               1985420                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 825377                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 15270485                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                49952350                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         109536                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  35410349                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              14777682                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              110872417                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               1412237                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              11132933                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1144918                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1526969                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                 486977                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           129945519                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             483152587                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        119447216                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               432                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 22632600                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               4409                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           4401                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  21510749                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             26805153                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             5347343                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads            519410                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           254099                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  109667150                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                8283                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 101366848                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1074801                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        18634403                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     41667039                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             65                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     116345779                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.871255                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.989200                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            54714850     47.03%     47.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            31358235     26.95%     73.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            22007860     18.92%     92.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7066756      6.07%     98.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             1197765      1.03%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 313      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       116345779                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 9784213     48.67%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     50      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                13      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                9614548     47.83%     96.50% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                702998      3.50%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              71970791     71.00%     71.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                10698      0.01%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               2      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              54      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc            124      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.01% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             24337715     24.01%     95.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             5047462      4.98%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              101366848                       # Type of FU issued
system.cpu.iq.rate                           0.870864                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    20101822                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.198308                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          340255638                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         128310520                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     99608490                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 460                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                624                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          115                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              121468430                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     240                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           288068                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4329242                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         1500                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation         1342                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       602499                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         7579                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        130663                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 825377                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 8119454                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                685980                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           109688255                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              26805153                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              5347343                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               4395                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 180270                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                342292                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents           1342                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         435059                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       412404                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               847463                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             100109842                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              23803071                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1257006                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         12822                       # number of nop insts executed
system.cpu.iew.exec_refs                     28718921                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 20621209                       # Number of branches executed
system.cpu.iew.exec_stores                    4915850                       # Number of stores executed
system.cpu.iew.exec_rate                     0.860065                       # Inst execution rate
system.cpu.iew.wb_sent                       99693752                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      99608605                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  59691637                       # num instructions producing a value
system.cpu.iew.wb_consumers                  95527463                       # num instructions consuming a value
system.cpu.iew.wb_rate                       0.855758                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.624864                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        17362842                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            823674                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    113658017                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.801119                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.737711                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     77235221     67.95%     67.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     18611593     16.38%     84.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      7151823      6.29%     90.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      3469408      3.05%     93.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1644636      1.45%     95.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       541902      0.48%     95.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       703188      0.62%     96.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       178974      0.16%     96.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      4121272      3.63%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    113658017                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             90602408                       # Number of instructions committed
system.cpu.commit.committedOps               91053639                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27220755                       # Number of memory references committed
system.cpu.commit.loads                      22475911                       # Number of loads committed
system.cpu.commit.membars                        3888                       # Number of memory barriers committed
system.cpu.commit.branches                   18732305                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  72326352                       # Number of committed integer instructions.
system.cpu.commit.function_calls                56148                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         63822387     70.09%     70.09% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           10474      0.01%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            6      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc           15      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            2      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.10% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        22475911     24.68%     94.79% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        4744844      5.21%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          91053639                       # Class of committed instruction
system.cpu.commit.bw_lim_events               4121272                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    217947492                       # The number of ROB reads
system.cpu.rob.rob_writes                   219521309                       # The number of ROB writes
system.cpu.timesIdled                             570                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           52283                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    90589799                       # Number of Instructions Simulated
system.cpu.committedOps                      91041030                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.284891                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.284891                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.778276                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.778276                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                108097873                       # number of integer regfile reads
system.cpu.int_regfile_writes                58692304                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        59                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       96                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 369004699                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 58686555                       # number of cc regfile writes
system.cpu.misc_regfile_reads                28410103                       # number of misc regfile reads
system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           5470634                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.784091                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            18249365                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           5471146                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              3.335565                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          35796500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.784091                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999578                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999578                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          344                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          168                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          61906904                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         61906904                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     13887331                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13887331                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4353747                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4353747                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data          522                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total           522                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         3872                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         3872                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      18241078                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18241078                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     18241600                       # number of overall hits
system.cpu.dcache.overall_hits::total        18241600                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      9587264                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       9587264                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       381234                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       381234                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            7                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            7                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           15                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           15                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      9968498                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9968498                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9968505                       # number of overall misses
system.cpu.dcache.overall_misses::total       9968505                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  88773272500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  88773272500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   4000795875                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   4000795875                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       291000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       291000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  92774068375                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  92774068375                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  92774068375                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  92774068375                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23474595                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23474595                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data          529                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total          529                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     28209576                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     28209576                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     28210105                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     28210105                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408410                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.408410                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080514                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.080514                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.013233                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.013233                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003859                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003859                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.353373                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.353373                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.353366                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.353366                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9259.500156                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total  9259.500156                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        19400                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        19400                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data  9306.724882                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total  9306.724882                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data  9306.718347                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total  9306.718347                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       329915                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       108865                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            121409                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           12838                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.717385                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     8.479903                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      5470634                       # number of writebacks
system.cpu.dcache.writebacks::total           5470634                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4338603                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      4338603                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158750                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       158750                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           15                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           15                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      4497353                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      4497353                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      4497353                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      4497353                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248661                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5248661                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222484                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       222484                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      5471145                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      5471145                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      5471149                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      5471149                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43288788000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  43288788000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2285573254                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2285573254                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       214500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       214500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45574361254                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  45574361254                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45574575754                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  45574575754                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223589                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223589                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046987                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046987                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007561                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007561                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193946                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.193946                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193943                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.193943                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8247.586956                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8247.586956                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53625                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53625                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8329.949445                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total  8329.949445                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8329.982560                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total  8329.982560                       # average overall mshr miss latency
system.cpu.icache.tags.replacements               447                       # number of replacements
system.cpu.icache.tags.tagsinuse           427.448157                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            32273898                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               904                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          35701.214602                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   427.448157                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.834860                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.834860                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          457                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          335                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.892578                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          64550990                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         64550990                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     32273898                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        32273898                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      32273898                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         32273898                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     32273898                       # number of overall hits
system.cpu.icache.overall_hits::total        32273898                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1145                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1145                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1145                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1145                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1145                       # number of overall misses
system.cpu.icache.overall_misses::total          1145                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     60302481                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     60302481                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     60302481                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     60302481                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     60302481                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     60302481                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     32275043                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     32275043                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     32275043                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     32275043                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     32275043                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     32275043                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000035                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000035                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000035                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000035                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000035                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000035                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 52665.922271                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 52665.922271                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        18953                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          107                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               219                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    86.543379                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    21.400000                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks          447                       # number of writebacks
system.cpu.icache.writebacks::total               447                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          240                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          240                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          240                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          240                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          240                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          240                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          905                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          905                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          905                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          905                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          905                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          905                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     49734485                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     49734485                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     49734485                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     49734485                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     49734485                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     49734485                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000028                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000028                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.num_hwpf_issued      4981065                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified      5296247                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit       274020                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage     14074841                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements              248                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        11235.818499                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            5318374                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs            14915                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs           356.578880                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   174.301588                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.675141                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.010639                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.685780                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          181                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        14486                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3            2                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4          168                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          469                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3489                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9544                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          100                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          884                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.011047                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.884155                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        180510207                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       180510207                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks      5451171                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      5451171                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        17033                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        17033                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       226019                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       226019                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          210                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total          210                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5243562                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      5243562                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst          210                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      5469581                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         5469791                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst          210                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      5469581                       # number of overall hits
system.cpu.l2cache.overall_hits::total        5469791                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data            3                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            3                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data          500                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          500                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          695                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          695                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1065                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total         1065                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          695                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         1565                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          2260                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          695                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         1565                       # number of overall misses
system.cpu.l2cache.overall_misses::total         2260                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        59500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        59500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     41259500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     41259500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     47414000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     47414000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     71274500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total     71274500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     47414000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    112534000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    159948000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     47414000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    112534000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    159948000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      5451171                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      5451171                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        17033                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        17033                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data            3                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            3                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       226519                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       226519                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          905                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          905                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      5244627                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      5244627                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          905                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      5471146                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      5472051                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          905                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      5471146                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      5472051                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002207                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.002207                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.767956                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.767956                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000203                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000203                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.767956                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.000286                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.000413                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.767956                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.000286                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.000413                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19833.333333                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19833.333333                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        82519                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        82519                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68221.582734                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68221.582734                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66924.413146                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66924.413146                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68221.582734                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71906.709265                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70773.451327                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68221.582734                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70773.451327                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.unused_prefetches                7                       # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks          175                       # number of writebacks
system.cpu.l2cache.writebacks::total              175                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          158                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total          158                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           37                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           37                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          195                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          196                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          195                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          196                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       316084                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       316084                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            3                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            3                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          342                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          342                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          694                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          694                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1028                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1028                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          694                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         1370                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         2064                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          694                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         1370                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       316084                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       318148                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    852614747                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    852614747                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        41500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        41500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     32745000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     32745000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43196500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43196500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     63614500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     63614500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43196500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     96359500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    139556000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43196500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     96359500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    852614747                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    992170747                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001510                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001510                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.766851                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.766851                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000196                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000196                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.766851                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000250                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.000377                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.766851                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000250                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.058141                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2697.430895                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  2697.430895                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2697.430895                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total  3118.582380                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests     10943135                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      5471097                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2877                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops       303361                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops       302576                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops          785                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp       5245531                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      5451346                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        19910                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict         1794                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       317966                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp            4                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq            3                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp            3                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       226519                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       226519                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          905                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244627                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2256                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16412936                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          16415192                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        86464                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    700274176                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          700360640                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      319939                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      5791989                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.053010                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.224658                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            5485738     94.71%     94.71% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             305466      5.27%     99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                785      0.01%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        5791989                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    10942648515                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization         18.8                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy         6019                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1357497                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    8206724991                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization         14.1                       # Layer utilization (%)
system.membus.trans_dist::ReadResp              16175                       # Transaction distribution
system.membus.trans_dist::WritebackDirty          175                       # Transaction distribution
system.membus.trans_dist::CleanEvict               63                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                4                       # Transaction distribution
system.membus.trans_dist::ReadExReq               341                       # Transaction distribution
system.membus.trans_dist::ReadExResp              341                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         16176                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        33275                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  33275                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1068224                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 1068224                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples             16759                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                   16759    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total               16759                       # Request fanout histogram
system.membus.reqLayer0.occupancy            27529285                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           86434816                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------