path: root/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.026911                       # Number of seconds simulated
sim_ticks                                 26911413000                       # Number of ticks simulated
final_tick                                26911413000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 116759                       # Simulator instruction rate (inst/s)
host_op_rate                                   117598                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               34685583                       # Simulator tick rate (ticks/s)
host_mem_usage                                 427272                       # Number of bytes of host memory used
host_seconds                                   775.87                       # Real time elapsed on the host
sim_insts                                    90589798                       # Number of instructions simulated
sim_ops                                      91240351                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             45440                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            947712                       # Number of bytes read from this memory
system.physmem.bytes_read::total               993152                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        45440                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           45440                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                710                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              14808                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 15518                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              1688503                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             35215988                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                36904491                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1688503                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1688503                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1688503                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            35215988                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               36904491                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         15518                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                       15518                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   993152                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    993152                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              1                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 987                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 886                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 942                       # Per bank write bursts
system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
system.physmem.perBankRdBursts::4                1050                       # Per bank write bursts
system.physmem.perBankRdBursts::5                1105                       # Per bank write bursts
system.physmem.perBankRdBursts::6                1078                       # Per bank write bursts
system.physmem.perBankRdBursts::7                1080                       # Per bank write bursts
system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 959                       # Per bank write bursts
system.physmem.perBankRdBursts::10                938                       # Per bank write bursts
system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
system.physmem.perBankRdBursts::12                904                       # Per bank write bursts
system.physmem.perBankRdBursts::13                865                       # Per bank write bursts
system.physmem.perBankRdBursts::14                877                       # Per bank write bursts
system.physmem.perBankRdBursts::15                896                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     26911220500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   15518                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     11172                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4157                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       169                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          619                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean     1598.759289                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     481.680955                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev    2200.761860                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65            153     24.72%     24.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129           75     12.12%     36.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193           40      6.46%     43.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257           20      3.23%     46.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321           12      1.94%     48.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385            6      0.97%     49.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449           27      4.36%     53.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513           12      1.94%     55.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577            5      0.81%     56.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641           10      1.62%     58.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705            3      0.48%     58.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769            4      0.65%     59.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833            5      0.81%     60.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897            8      1.29%     61.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961            3      0.48%     61.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025            3      0.48%     62.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089            6      0.97%     63.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153            2      0.32%     63.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217            2      0.32%     63.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281            3      0.48%     64.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345            2      0.32%     64.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409            4      0.65%     65.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473            6      0.97%     66.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537           19      3.07%     69.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601            6      0.97%     70.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665            6      0.97%     71.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793            3      0.48%     71.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857            3      0.48%     72.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985            1      0.16%     72.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049            6      0.97%     73.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113            2      0.32%     73.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177            6      0.97%     74.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305            2      0.32%     75.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369            1      0.16%     75.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497            3      0.48%     75.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561            1      0.16%     75.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625            2      0.32%     76.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689            1      0.16%     76.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753            5      0.81%     77.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817            4      0.65%     77.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945            2      0.32%     78.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009            3      0.48%     78.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073            4      0.65%     79.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137            2      0.32%     79.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201            2      0.32%     79.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265            2      0.32%     80.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393            3      0.48%     80.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457            1      0.16%     80.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521            2      0.32%     81.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585            1      0.16%     81.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649            3      0.48%     81.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713            3      0.48%     82.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777            2      0.32%     82.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905            1      0.16%     82.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969            1      0.16%     83.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033            1      0.16%     83.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097            3      0.48%     83.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161            2      0.32%     84.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225            1      0.16%     84.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417            3      0.48%     84.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481            4      0.65%     85.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545            4      0.65%     85.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609            1      0.16%     86.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673            3      0.48%     86.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737            2      0.32%     86.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801            2      0.32%     87.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865            1      0.16%     87.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929            2      0.32%     87.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993            1      0.16%     87.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057            2      0.32%     88.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121            5      0.81%     89.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185            3      0.48%     89.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249            4      0.65%     90.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377            2      0.32%     90.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441            6      0.97%     91.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505            3      0.48%     91.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569            1      0.16%     92.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697            1      0.16%     92.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825            1      0.16%     92.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889            1      0.16%     92.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017            3      0.48%     93.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081            1      0.16%     93.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145            2      0.32%     93.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209            1      0.16%     93.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273            2      0.32%     94.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337            3      0.48%     94.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401            1      0.16%     94.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529            2      0.32%     94.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593            1      0.16%     95.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657            3      0.48%     95.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721            1      0.16%     95.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785            1      0.16%     95.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913            1      0.16%     96.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977            1      0.16%     96.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041            1      0.16%     96.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105            2      0.32%     96.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169            1      0.16%     96.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425            1      0.16%     97.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617            1      0.16%     97.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681            1      0.16%     97.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745            1      0.16%     97.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873            1      0.16%     97.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129            2      0.32%     98.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193           12      1.94%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            619                       # Bytes accessed per row activation
system.physmem.totQLat                      103760250                       # Total ticks spent queuing
system.physmem.totMemAccLat                 357130250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     77590000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                   175780000                       # Total ticks spent accessing banks
system.physmem.avgQLat                        6686.44                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    11327.49                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  23013.94                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          36.90                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       36.90                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.29                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.29                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                      14899                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   96.01                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      1734193.87                       # Average gap between requests
system.physmem.pageHitRate                      96.01                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               1.04                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     36904491                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                 980                       # Transaction distribution
system.membus.trans_dist::ReadResp                980                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               1                       # Transaction distribution
system.membus.trans_dist::ReadExReq             14538                       # Transaction distribution
system.membus.trans_dist::ReadExResp            14538                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31038                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  31038                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       993152                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total              993152                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                 993152                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            19253000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy          145189999                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
system.cpu.branchPred.lookups                26686306                       # Number of BP lookups
system.cpu.branchPred.condPredicted          22003847                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            843168                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             11366672                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                11283030                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             99.264147                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                   70474                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                170                       # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  442                       # Number of system calls
system.cpu.numCycles                         53822827                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           14174375                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      127897951                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    26686306                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           11353504                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      24037647                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4766390                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               11312706                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  108                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles             8                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           52                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  13845393                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                329438                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           53431463                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.410222                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.214882                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 29432152     55.08%     55.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  3389873      6.34%     61.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  2028658      3.80%     65.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1553769      2.91%     68.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1668148      3.12%     71.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2920061      5.47%     76.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1509677      2.83%     79.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1090745      2.04%     81.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  9838380     18.41%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             53431463                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.495818                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.376277                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 16937925                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               9159010                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  22405754                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1030805                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3897969                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              4444268                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                  8691                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              126081524                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 42632                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3897969                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 18719458                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 3589629                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         186437                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  21552986                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5484984                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              123156725                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                     9                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 425837                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4596994                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents             1284                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           143603336                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             536446832                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        500029218                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               672                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             107414186                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 36189150                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               4635                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           4633                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12540789                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             29477429                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             5520545                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           2151265                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1294097                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  118170448                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                8500                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 105167442                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued             79307                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        26742090                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     65583646                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            282                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      53431463                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.968268                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.908949                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            15374280     28.77%     28.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            11649569     21.80%     50.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             8250468     15.44%     66.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             6827782     12.78%     78.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             4953380      9.27%     88.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2948609      5.52%     93.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             2456731      4.60%     98.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              528512      0.99%     99.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              442132      0.83%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        53431463                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   45750      6.92%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     27      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 340320     51.44%     58.36% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                275443     41.64%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              74429619     70.77%     70.77% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                10979      0.01%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt             129      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc            165      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.78% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             25613153     24.35%     95.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             5113394      4.86%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              105167442                       # Type of FU issued
system.cpu.iq.rate                           1.953956                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                      661540                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.006290                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          264506537                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         144925816                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    102691564                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 657                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                923                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          287                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              105828655                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     327                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           441760                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      6903463                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6716                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation         6442                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       775701                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         31606                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3897969                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  957023                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                126637                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           118191644                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            310003                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              29477429                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              5520545                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               4612                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  65722                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  6738                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents           6442                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         447212                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       446019                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               893231                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             104191675                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              25292948                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            975767                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         12696                       # number of nop insts executed
system.cpu.iew.exec_refs                     30349771                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 21326762                       # Number of branches executed
system.cpu.iew.exec_stores                    5056823                       # Number of stores executed
system.cpu.iew.exec_rate                     1.935827                       # Inst execution rate
system.cpu.iew.wb_sent                      102970942                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     102691851                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  62249009                       # num instructions producing a value
system.cpu.iew.wb_consumers                 104309545                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.907961                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.596772                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        26941617                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            834570                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     49533494                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.842248                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.540561                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     20042935     40.46%     40.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13146551     26.54%     67.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4167484      8.41%     75.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      3431298      6.93%     82.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1535317      3.10%     85.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       726626      1.47%     86.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       954928      1.93%     88.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       253259      0.51%     89.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5275096     10.65%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     49533494                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             90602407                       # Number of instructions committed
system.cpu.commit.committedOps               91252960                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27318810                       # Number of memory references committed
system.cpu.commit.loads                      22573966                       # Number of loads committed
system.cpu.commit.membars                        3888                       # Number of memory barriers committed
system.cpu.commit.branches                   18732304                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  72525674                       # Number of committed integer instructions.
system.cpu.commit.function_calls                56148                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               5275096                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    162447241                       # The number of ROB reads
system.cpu.rob.rob_writes                   240306728                       # The number of ROB writes
system.cpu.timesIdled                           46009                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          391364                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    90589798                       # Number of Instructions Simulated
system.cpu.committedOps                      91240351                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              90589798                       # Number of Instructions Simulated
system.cpu.cpi                               0.594138                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.594138                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.683111                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.683111                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                495604527                       # number of integer regfile reads
system.cpu.int_regfile_writes               120552200                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       148                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      360                       # number of floating regfile writes
system.cpu.misc_regfile_reads                29090078                       # number of misc regfile reads
system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
system.cpu.toL2Bus.throughput              4497665284                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq         904635                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        904635                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       942892                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        43700                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        43700                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1472                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2838092                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           2839564                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        47040                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120991360                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      121038400                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         121038400                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus          128                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     1888506500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          7.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1222499                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1424110491                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          5.3                       # Layer utilization (%)
system.cpu.icache.tags.replacements                 3                       # number of replacements
system.cpu.icache.tags.tagsinuse           632.612747                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            13844401                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               735                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          18835.919728                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   632.612747                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.308893                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.308893                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     13844401                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        13844401                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      13844401                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         13844401                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     13844401                       # number of overall hits
system.cpu.icache.overall_hits::total        13844401                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          991                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           991                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          991                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            991                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          991                       # number of overall misses
system.cpu.icache.overall_misses::total           991                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     67770748                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     67770748                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     67770748                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     67770748                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     67770748                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     67770748                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     13845392                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     13845392                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     13845392                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     13845392                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     13845392                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     13845392                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000072                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000072                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000072                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000072                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000072                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000072                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68386.224016                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 68386.224016                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68386.224016                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 68386.224016                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68386.224016                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 68386.224016                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          651                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    59.181818                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          254                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          254                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          254                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          254                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          254                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          254                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          737                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          737                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          737                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          737                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          737                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          737                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     51712250                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     51712250                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     51712250                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     51712250                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     51712250                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     51712250                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000053                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70165.875170                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70165.875170                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70165.875170                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 70165.875170                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70165.875170                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 70165.875170                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        10730.950237                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1831391                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs            15501                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs           118.146636                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  9880.493814                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   618.630242                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   231.826182                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.301529                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.018879                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.007075                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.327483                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst           24                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       903618                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         903642                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       942892                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       942892                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data        29162                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total        29162                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst           24                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       932780                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          932804                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           24                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       932780                       # number of overall hits
system.cpu.l2cache.overall_hits::total         932804                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          711                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          280                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          991                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        14538                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        14538                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          711                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        14818                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         15529                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          711                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        14818                       # number of overall misses
system.cpu.l2cache.overall_misses::total        15529                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     50729000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     21404500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     72133500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    962429750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    962429750                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     50729000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    983834250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   1034563250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     50729000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    983834250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   1034563250                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          735                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       903898                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       904633                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       942892                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       942892                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data            2                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            2                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        43700                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        43700                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          735                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       947598                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       948333                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          735                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       947598                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       948333                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.967347                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000310                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.001095                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.500000                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.332677                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.332677                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.967347                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.015637                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.016375                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.967347                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.015637                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.016375                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71348.804501                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76444.642857                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72788.597376                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66200.973311                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66200.973311                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71348.804501                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66394.537050                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66621.369695                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71348.804501                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66394.537050                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66621.369695                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           10                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           11                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           10                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           11                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           11                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          710                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          270                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          980                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14538                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        14538                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          710                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        14808                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        15518                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          710                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        14808                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        15518                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     41786750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     17438000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     59224750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        10001                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        10001                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    780053750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    780053750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     41786750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    797491750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    839278500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     41786750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    797491750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    839278500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.965986                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000299                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001083                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.332677                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.332677                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965986                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015627                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.016363                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965986                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015627                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.016363                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58854.577465                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64585.185185                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60433.418367                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53656.194112                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53656.194112                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58854.577465                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53855.466640                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54084.192551                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58854.577465                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53855.466640                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54084.192551                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            943502                       # number of replacements
system.cpu.dcache.tags.tagsinuse          3671.733270                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            28144425                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            947598                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.700807                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        8006035000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  3671.733270                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.896419                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.896419                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     23603772                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23603772                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4532846                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4532846                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         3913                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         3913                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      28136618                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         28136618                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     28136618                       # number of overall hits
system.cpu.dcache.overall_hits::total        28136618                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1173981                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1173981                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       202135                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       202135                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            7                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            7                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1376116                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1376116                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1376116                       # number of overall misses
system.cpu.dcache.overall_misses::total       1376116                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  13894448479                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  13894448479                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   8458649331                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   8458649331                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       251500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       251500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  22353097810                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  22353097810                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  22353097810                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  22353097810                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     24777753                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     24777753                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3920                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         3920                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     29512734                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     29512734                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     29512734                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     29512734                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047380                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.047380                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.042690                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.042690                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001786                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001786                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.046628                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.046628                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.046628                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.046628                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.326533                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.326533                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41846.534895                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 41846.534895                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16243.614499                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16243.614499                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16243.614499                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16243.614499                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       154190                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             23957                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     6.436115                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       942892                       # number of writebacks
system.cpu.dcache.writebacks::total            942892                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       270066                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       270066                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158450                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       158450                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            7                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            7                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       428516                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       428516                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       428516                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       428516                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903915                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       903915                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        43685                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        43685                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       947600                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       947600                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       947600                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       947600                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9994483010                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   9994483010                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1318924416                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   1318924416                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11313407426                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  11313407426                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11313407426                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  11313407426                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036481                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036481                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009226                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009226                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032108                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.032108                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032108                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.032108                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.883678                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.883678                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30191.700034                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30191.700034                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.011636                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.011636                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.011636                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.011636                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------