path: root/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.070047                       # Number of seconds simulated
sim_ticks                                 70046988500                       # Number of ticks simulated
final_tick                                70046988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 120922                       # Simulator instruction rate (inst/s)
host_op_rate                                   212925                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               53613076                       # Simulator tick rate (ticks/s)
host_mem_usage                                 355612                       # Number of bytes of host memory used
host_seconds                                  1306.53                       # Real time elapsed on the host
sim_insts                                   157988582                       # Number of instructions simulated
sim_ops                                     278192519                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read                     3895936                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                  65216                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                   892288                       # Number of bytes written to this memory
system.physmem.num_reads                        60874                       # Number of read requests responded to by this memory
system.physmem.num_writes                       13942                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                       55618894                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                    931032                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write                      12738421                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total                      68357314                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                  444                       # Number of system calls
system.cpu.numCycles                        140093978                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 37937752                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           37937752                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            1331995                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              33815417                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 33320649                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           29024363                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      203514307                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    37937752                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           33320649                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      63466806                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                10233892                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               37945043                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   18                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            68                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                  28213885                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                212642                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          139306492                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.579216                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.290579                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 78286088     56.20%     56.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  3759512      2.70%     58.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  2809249      2.02%     60.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  4511465      3.24%     64.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  7046412      5.06%     69.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  5071327      3.64%     72.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  7671850      5.51%     78.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  4389018      3.15%     81.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 25761571     18.49%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            139306492                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.270802                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.452698                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 41961886                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              28163540                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  52299140                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               8011732                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                8870194                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              354926885                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                8870194                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 48488899                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 4721769                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           9082                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  53110553                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              24105995                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              349921643                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    18                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 105361                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              20166032                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands           314159745                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             860584858                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        860581891                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              2967                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             248344192                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 65815553                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                479                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            473                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  57293063                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            112603571                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            37556545                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          47800126                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          8208845                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  343290045                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                2336                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 316029105                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued             76885                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        64917017                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     92716043                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1890                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     139306492                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.268588                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.744230                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            32068137     23.02%     23.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            17712067     12.71%     35.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            24423194     17.53%     53.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            32289069     23.18%     76.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            18335734     13.16%     89.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             9491103      6.81%     96.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             3154604      2.26%     98.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1783304      1.28%     99.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8               49280      0.04%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       139306492                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   25569      1.30%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1859415     94.86%     96.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                 75095      3.83%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass             16711      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             180131547     57.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 149      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            101432595     32.10%     89.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            34448103     10.90%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              316029105                       # Type of FU issued
system.cpu.iq.rate                           2.255836                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1960079                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.006202                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          773400844                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         408240794                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    312293905                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 822                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes               1922                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          316                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              317972066                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     407                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         52311971                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     21824183                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       143830                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        34021                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      6116794                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         3244                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          3822                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                8870194                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  981730                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 88786                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           343292381                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts             39929                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             112603571                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             37556545                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                466                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   1316                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 42406                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          34021                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        1234482                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       211725                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1446207                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             313835720                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             100810143                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2193385                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    134854161                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 31726163                       # Number of branches executed
system.cpu.iew.exec_stores                   34044018                       # Number of stores executed
system.cpu.iew.exec_rate                     2.240180                       # Inst execution rate
system.cpu.iew.wb_sent                      313006075                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     312294221                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 231754622                       # num instructions producing a value
system.cpu.iew.wb_consumers                 317218208                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.229177                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.730584                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      157988582                       # The number of committed instructions
system.cpu.commit.commitCommittedOps        278192519                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        65103374                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1332005                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    130436298                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.132785                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.651894                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     49351461     37.84%     37.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     24978168     19.15%     56.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     17073618     13.09%     70.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     12436945      9.53%     79.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      3526211      2.70%     82.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      3453253      2.65%     84.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      2711146      2.08%     87.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1125673      0.86%     87.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     15779823     12.10%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    130436298                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            157988582                       # Number of instructions committed
system.cpu.commit.committedOps              278192519                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      122219139                       # Number of memory references committed
system.cpu.commit.loads                      90779388                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   29309710                       # Number of branches committed
system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              15779823                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    457952368                       # The number of ROB reads
system.cpu.rob.rob_writes                   695479183                       # The number of ROB writes
system.cpu.timesIdled                           23894                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          787486                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   157988582                       # Number of Instructions Simulated
system.cpu.committedOps                     278192519                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             157988582                       # Number of Instructions Simulated
system.cpu.cpi                               0.886735                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.886735                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.127733                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.127733                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                554395898                       # number of integer regfile reads
system.cpu.int_regfile_writes               279799467                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       352                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      262                       # number of floating regfile writes
system.cpu.misc_regfile_reads               200946158                       # number of misc regfile reads
system.cpu.icache.replacements                     64                       # number of replacements
system.cpu.icache.tagsinuse                822.534021                       # Cycle average of tags in use
system.cpu.icache.total_refs                 28212585                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   1024                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               27551.352539                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     822.534021                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.401628                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.401628                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     28212585                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        28212585                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      28212585                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         28212585                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     28212585                       # number of overall hits
system.cpu.icache.overall_hits::total        28212585                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1300                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1300                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1300                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1300                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1300                       # number of overall misses
system.cpu.icache.overall_misses::total          1300                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     46952500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     46952500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     46952500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     46952500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     46952500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     46952500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     28213885                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     28213885                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     28213885                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     28213885                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     28213885                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     28213885                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000046                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000046                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000046                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36117.307692                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36117.307692                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36117.307692                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          275                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          275                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          275                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          275                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          275                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          275                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1025                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         1025                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         1025                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         1025                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         1025                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         1025                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     36071500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     36071500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     36071500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     36071500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     36071500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     36071500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000036                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000036                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000036                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35191.707317                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35191.707317                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35191.707317                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                2072906                       # number of replacements
system.cpu.dcache.tagsinuse               4073.029614                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 77489413                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                2077002                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  37.308300                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle            23588256000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4073.029614                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.994392                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.994392                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     46135653                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        46135653                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     31353751                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       31353751                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      77489404                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         77489404                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     77489404                       # number of overall hits
system.cpu.dcache.overall_hits::total        77489404                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2289012                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2289012                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        86000                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        86000                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2375012                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2375012                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2375012                       # number of overall misses
system.cpu.dcache.overall_misses::total       2375012                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  13766771000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  13766771000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   1501245288                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   1501245288                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  15268016288                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  15268016288                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  15268016288                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  15268016288                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     48424665                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     48424665                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     31439751                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     31439751                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     79864416                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     79864416                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     79864416                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     79864416                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047270                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002735                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.029738                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.029738                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  6014.285203                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17456.340558                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data  6428.605956                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data  6428.605956                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1880780                       # number of writebacks
system.cpu.dcache.writebacks::total           1880780                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       294089                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       294089                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3918                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         3918                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       298007                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       298007                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       298007                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       298007                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994923                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1994923                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82082                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        82082                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2077005                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2077005                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2077005                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2077005                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5565133500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   5565133500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1157645788                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   1157645788                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6722779288                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   6722779288                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6722779288                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   6722779288                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.041196                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002611                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026007                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026007                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2789.648272                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14103.528033                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  3236.766059                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  3236.766059                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 33246                       # number of replacements
system.cpu.l2cache.tagsinuse             18964.988080                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3764517                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                 61253                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 61.458492                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 12927.949414                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    243.086422                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   5793.952244                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.394530                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.007418                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.176817                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.578766                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst            5                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1964440                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1964445                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1880780                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1880780                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data        52709                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total        52709                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst            5                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2017149                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2017154                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            5                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2017149                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2017154                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         1019                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        30342                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        31361                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        29513                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        29513                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         1019                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        59855                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         60874                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         1019                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        59855                       # number of overall misses
system.cpu.l2cache.overall_misses::total        60874                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     34913500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1036289000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1071202500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1006190000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1006190000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     34913500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   2042479000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   2077392500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     34913500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   2042479000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   2077392500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         1024                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1994782                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1995806                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1880780                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1880780                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        82222                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        82222                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         1024                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2077004                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2078028                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         1024                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2077004                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2078028                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.995117                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.015211                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.358943                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.995117                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.028818                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.995117                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.028818                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34262.512267                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34153.615451                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34093.111510                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34262.512267                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34123.782474                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34262.512267                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34123.782474                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        13942                       # number of writebacks
system.cpu.l2cache.writebacks::total            13942                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1019                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        30342                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        31361                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        29513                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        29513                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         1019                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        59855                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        60874                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         1019                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        59855                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        60874                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     31643000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    941211000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    972854000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        31000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        31000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    914925500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    914925500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     31643000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1856136500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   1887779500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     31643000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1856136500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   1887779500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.995117                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.015211                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358943                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.995117                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.028818                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.995117                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.028818                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.993131                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.071188                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.762376                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.993131                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.550497                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.993131                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.550497                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------