path: root/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.065554                       # Number of seconds simulated
sim_ticks                                 65553895500                       # Number of ticks simulated
final_tick                                65553895500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 122580                       # Simulator instruction rate (inst/s)
host_op_rate                                   215844                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               50862026                       # Simulator tick rate (ticks/s)
host_mem_usage                                 417260                       # Number of bytes of host memory used
host_seconds                                  1288.86                       # Real time elapsed on the host
sim_insts                                   157988547                       # Number of instructions simulated
sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             69632                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           1890944                       # Number of bytes read from this memory
system.physmem.bytes_read::total              1960576                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        69632                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           69632                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks        17920                       # Number of bytes written to this memory
system.physmem.bytes_written::total             17920                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               1088                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              29546                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 30634                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks             280                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                  280                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              1062210                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             28845639                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                29907849                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1062210                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1062210                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks            273363                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                 273363                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks            273363                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1062210                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            28845639                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               30181212                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         30634                       # Number of read requests accepted
system.physmem.writeReqs                          280                       # Number of write requests accepted
system.physmem.readBursts                       30634                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                        280                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  1951616                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8960                       # Total number of bytes read from write queue
system.physmem.bytesWritten                     16000                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   1960576                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                  17920                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      140                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                1938                       # Per bank write bursts
system.physmem.perBankRdBursts::1                2083                       # Per bank write bursts
system.physmem.perBankRdBursts::2                2040                       # Per bank write bursts
system.physmem.perBankRdBursts::3                1941                       # Per bank write bursts
system.physmem.perBankRdBursts::4                2041                       # Per bank write bursts
system.physmem.perBankRdBursts::5                1918                       # Per bank write bursts
system.physmem.perBankRdBursts::6                1976                       # Per bank write bursts
system.physmem.perBankRdBursts::7                1870                       # Per bank write bursts
system.physmem.perBankRdBursts::8                1951                       # Per bank write bursts
system.physmem.perBankRdBursts::9                1940                       # Per bank write bursts
system.physmem.perBankRdBursts::10               1805                       # Per bank write bursts
system.physmem.perBankRdBursts::11               1794                       # Per bank write bursts
system.physmem.perBankRdBursts::12               1792                       # Per bank write bursts
system.physmem.perBankRdBursts::13               1799                       # Per bank write bursts
system.physmem.perBankRdBursts::14               1827                       # Per bank write bursts
system.physmem.perBankRdBursts::15               1779                       # Per bank write bursts
system.physmem.perBankWrBursts::0                  10                       # Per bank write bursts
system.physmem.perBankWrBursts::1                 107                       # Per bank write bursts
system.physmem.perBankWrBursts::2                  31                       # Per bank write bursts
system.physmem.perBankWrBursts::3                  25                       # Per bank write bursts
system.physmem.perBankWrBursts::4                  39                       # Per bank write bursts
system.physmem.perBankWrBursts::5                  13                       # Per bank write bursts
system.physmem.perBankWrBursts::6                  16                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   1                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   5                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  3                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     65553697500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   30634                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                    280                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     29978                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       404                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         2859                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      687.860091                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     477.665686                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     399.129385                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            441     15.42%     15.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          263      9.20%     24.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383          134      4.69%     29.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          136      4.76%     34.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          118      4.13%     38.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          116      4.06%     42.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           85      2.97%     45.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           96      3.36%     48.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         1470     51.42%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           2859                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples            14                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      2173.928571                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       21.222071                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     8074.812153                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023             13     92.86%     92.86% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::29696-30719            1      7.14%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total              14                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples            14                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.857143                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.849200                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.534522                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16                  1      7.14%      7.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                 13     92.86%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total              14                       # Writes before turning the bus around for reads
system.physmem.totQLat                      136299000                       # Total ticks spent queuing
system.physmem.totMemAccLat                 708061500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    152470000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        4469.70                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  23219.70                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          29.77                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.24                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       29.91                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.27                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.23                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.62                       # Average write queue length when enqueuing
system.physmem.readRowHits                      27721                       # Number of row buffer hits during reads
system.physmem.writeRowHits                       161                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.91                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  57.50                       # Row buffer hit rate for writes
system.physmem.avgGap                      2120518.13                       # Average gap between requests
system.physmem.pageHitRate                      90.60                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                   11740680                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    6406125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 123169800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                  1568160                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             4281566640                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             3052855305                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            36653676000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              44130982710                       # Total energy per rank (pJ)
system.physmem_0.averagePower              673.213820                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    60959756000                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2188940000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      2404016500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                    9873360                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    5387250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 114558600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                    51840                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             4281566640                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             3230070300                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            36498224250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              44139732240                       # Total energy per rank (pJ)
system.physmem_1.averagePower              673.347293                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    60700713000                       # Time in different power states
system.physmem_1.memoryStateTime::REF      2188940000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      2663059500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                40360668                       # Number of BP lookups
system.cpu.branchPred.condPredicted          40360668                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1392637                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             26664097                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 5988252                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              86625                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups        26664097                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits           21157452                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses          5506645                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       511906                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls                  444                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON     65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        131107792                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           30523578                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      219647427                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    40360668                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           27145704                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      98945290                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2900833                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                        518                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                 6239                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        114030                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           50                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          156                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  29742559                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                352958                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                      20                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          131040277                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.949675                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.407509                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 65532629     50.01%     50.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  4015050      3.06%     53.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  3611452      2.76%     55.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  6110552      4.66%     60.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  7743592      5.91%     66.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  5553299      4.24%     70.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  3377797      2.58%     73.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  2818268      2.15%     75.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 32277638     24.63%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            131040277                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.307843                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.675319                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 15257836                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              64260169                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  40205069                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               9866787                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1450416                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              361840570                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                1450416                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 20789312                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                11161609                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          17754                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  44252475                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              53368711                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              352352816                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 16475                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 802883                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               46797603                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                4838735                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           354809982                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             933969547                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        575070468                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             25233                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 75597235                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                487                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            488                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  64661942                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            112312024                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            38476139                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          51587404                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          9144280                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  343861767                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                4715                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 317818488                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            169830                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        65674018                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    101673382                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           4270                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     131040277                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.425350                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.164581                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            35194225     26.86%     26.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            20112862     15.35%     42.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            17093441     13.04%     55.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            17641161     13.46%     68.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            15328111     11.70%     80.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            12869587      9.82%     90.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             6689257      5.10%     95.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             4093724      3.12%     98.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             2017909      1.54%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       131040277                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  366862      8.95%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.95% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                3538662     86.29%     95.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                195200      4.76%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass             33340      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             181791277     57.20%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                11724      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                   408      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 305      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            101272470     31.86%     89.08% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            34708964     10.92%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              317818488                       # Type of FU issued
system.cpu.iq.rate                           2.424101                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     4100724                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.012903                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          770927721                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         409562927                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    313648272                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               20086                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              38326                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         4607                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              321877132                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                    8740                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         57541030                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     21532639                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        67356                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        63407                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      7036387                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         3908                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        141249                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1450416                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 8045146                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               3020269                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           343866482                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            122594                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             112312024                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             38476139                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               1910                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   3213                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               3025719                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          63407                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         529775                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      1033204                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1562979                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             315414153                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             100518036                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2404335                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    134824639                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 32104448                       # Number of branches executed
system.cpu.iew.exec_stores                   34306603                       # Number of stores executed
system.cpu.iew.exec_rate                     2.405762                       # Inst execution rate
system.cpu.iew.wb_sent                      314286106                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     313652879                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 237682188                       # num instructions producing a value
system.cpu.iew.wb_consumers                 343423954                       # num instructions consuming a value
system.cpu.iew.wb_rate                       2.392328                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.692096                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        65797430                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1399141                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    121633848                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.287130                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     3.051606                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     56556051     46.50%     46.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     16464352     13.54%     60.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     11233282      9.24%     69.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      8748892      7.19%     76.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2045691      1.68%     78.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1756798      1.44%     79.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       927336      0.76%     80.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       727466      0.60%     80.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     23173980     19.05%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    121633848                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      122219137                       # Number of memory references committed
system.cpu.commit.loads                      90779385                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   29309705                       # Number of branches committed
system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 278169481                       # Number of committed integer instructions.
system.cpu.commit.function_calls              4237596                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass        16695      0.01%      0.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        155945353     56.06%     56.06% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           10938      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv              329      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd             12      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        90779385     32.63%     88.70% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       31439752     11.30%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
system.cpu.commit.bw_lim_events              23173980                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    442449762                       # The number of ROB reads
system.cpu.rob.rob_writes                   697455131                       # The number of ROB writes
system.cpu.timesIdled                             919                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           67515                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.829856                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.829856                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.205028                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.205028                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                502814986                       # number of integer regfile reads
system.cpu.int_regfile_writes               247784196                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      4396                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      732                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 109093589                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 65488596                       # number of cc regfile writes
system.cpu.misc_regfile_reads               201890594                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           2073601                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4068.108072                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            71473739                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2077697                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             34.400463                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle       21041764500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4068.108072                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993190                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993190                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          507                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         3433                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          156                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         150601371                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        150601371                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     40127755                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        40127755                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     31345984                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       31345984                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      71473739                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         71473739                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     71473739                       # number of overall hits
system.cpu.dcache.overall_hits::total        71473739                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2694330                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2694330                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        93768                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        93768                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2788098                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2788098                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2788098                       # number of overall misses
system.cpu.dcache.overall_misses::total       2788098                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  32345718500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  32345718500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   2982305493                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   2982305493                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  35328023993                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  35328023993                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  35328023993                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  35328023993                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     42822085                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     42822085                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     74261837                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     74261837                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     74261837                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     74261837                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.062919                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.062919                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002982                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.002982                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037544                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037544                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037544                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037544                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12005.106464                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 12005.106464                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31805.152003                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31805.152003                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12671.012279                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12671.012279                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12671.012279                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12671.012279                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       218790                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          393                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             43059                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.081168                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    98.250000                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      2067196                       # number of writebacks
system.cpu.dcache.writebacks::total           2067196                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       698496                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       698496                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11905                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        11905                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       710401                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       710401                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       710401                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       710401                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1995834                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1995834                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        81863                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        81863                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2077697                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2077697                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2077697                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2077697                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24223051500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  24223051500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2825101993                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2825101993                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27048153493                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  27048153493                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27048153493                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  27048153493                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046608                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046608                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002604                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027978                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.027978                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027978                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.027978                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.806718                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.806718                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34510.120482                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34510.120482                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13018.333998                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13018.333998                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13018.333998                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13018.333998                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                91                       # number of replacements
system.cpu.icache.tags.tagsinuse           875.979350                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            29741086                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              1117                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          26625.860340                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   875.979350                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.427724                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.427724                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1026                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           29                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           35                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          914                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.500977                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          59486235                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         59486235                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     29741086                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        29741086                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      29741086                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         29741086                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     29741086                       # number of overall hits
system.cpu.icache.overall_hits::total        29741086                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1473                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1473                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1473                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1473                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1473                       # number of overall misses
system.cpu.icache.overall_misses::total          1473                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    110309999                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    110309999                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    110309999                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    110309999                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    110309999                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    110309999                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     29742559                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     29742559                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     29742559                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     29742559                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     29742559                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     29742559                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000050                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000050                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000050                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000050                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000050                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000050                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74887.983028                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 74887.983028                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74887.983028                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 74887.983028                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74887.983028                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 74887.983028                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1013                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                13                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    77.923077                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks           91                       # number of writebacks
system.cpu.icache.writebacks::total                91                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          356                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          356                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          356                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          356                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          356                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          356                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1117                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         1117                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         1117                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         1117                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         1117                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         1117                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     86959999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     86959999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     86959999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     86959999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     86959999                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     86959999                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000038                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000038                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000038                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77851.386750                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77851.386750                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77851.386750                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 77851.386750                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77851.386750                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 77851.386750                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements              663                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        21665.639104                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4121840                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs            30651                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs           134.476526                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks     2.943755                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   711.855926                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 20950.839423                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.000090                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.021724                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.639369                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.661183                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        29988                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          166                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3           56                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29650                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.915161                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         33250579                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        33250579                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks      2067196                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      2067196                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks           91                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total           91                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data        52900                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total        52900                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           29                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total           29                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1995251                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1995251                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst           29                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2048151                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2048180                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           29                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2048151                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2048180                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data        28989                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        28989                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1088                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         1088                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data          557                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total          557                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         1088                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        29546                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         30634                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         1088                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        29546                       # number of overall misses
system.cpu.l2cache.overall_misses::total        30634                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2146396500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   2146396500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     84962000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     84962000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     42143000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total     42143000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     84962000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   2188539500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   2273501500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     84962000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   2188539500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   2273501500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      2067196                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      2067196                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks           91                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total           91                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        81889                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        81889                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1117                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         1117                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1995808                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1995808                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         1117                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2077697                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2078814                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         1117                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2077697                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2078814                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.354004                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.354004                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.974038                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.974038                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000279                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000279                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.974038                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.014221                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.014736                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.974038                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.014221                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.014736                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74041.757218                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74041.757218                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78090.073529                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78090.073529                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75660.682226                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75660.682226                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78090.073529                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74072.277127                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74214.973559                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78090.073529                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74072.277127                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74214.973559                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks          280                       # number of writebacks
system.cpu.l2cache.writebacks::total              280                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28989                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        28989                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1088                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1088                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          557                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total          557                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         1088                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        29546                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        30634                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         1088                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        29546                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        30634                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1856506500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1856506500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     74082000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     74082000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     36573000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     36573000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     74082000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1893079500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   1967161500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     74082000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1893079500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   1967161500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.354004                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.354004                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.974038                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.974038                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000279                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000279                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.974038                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014221                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.014736                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.974038                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014221                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.014736                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64041.757218                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64041.757218                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68090.073529                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68090.073529                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65660.682226                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65660.682226                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68090.073529                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64072.277127                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64214.973559                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68090.073529                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64072.277127                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64214.973559                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      4152506                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2073696                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests           15                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          331                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          331                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp       1996925                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      2067476                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean           91                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict         6788                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        81889                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        81889                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq         1117                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1995808                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2325                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6228995                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           6231320                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77312                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265273152                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          265350464                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                         663                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                 17920                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      2079477                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.000168                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.012972                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2079127     99.98%     99.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                350      0.02%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2079477                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4143540000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          6.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1675999                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3116545500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          4.8                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests         30966                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests          332                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED  65553895500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp               1645                       # Transaction distribution
system.membus.trans_dist::WritebackDirty          280                       # Transaction distribution
system.membus.trans_dist::CleanEvict               52                       # Transaction distribution
system.membus.trans_dist::ReadExReq             28989                       # Transaction distribution
system.membus.trans_dist::ReadExResp            28989                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          1645                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61600                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61600                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  61600                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1978496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1978496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 1978496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples             30634                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                   30634    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total               30634                       # Request fanout histogram
system.membus.reqLayer0.occupancy            43502500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy          161439750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------