blob: 740e607ea2ffbcc02729c36d3ce0f1ff329cf768 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.068408 # Number of seconds simulated
sim_ticks 68408131000 # Number of ticks simulated
final_tick 68408131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 92617 # Simulator instruction rate (inst/s)
host_op_rate 163083 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 40102422 # Simulator tick rate (ticks/s)
host_mem_usage 370556 # Number of bytes of host memory used
host_seconds 1705.84 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192462 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1892736 # Number of bytes read from this memory
system.physmem.bytes_read::total 1961088 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 20352 # Number of bytes written to this memory
system.physmem.bytes_written::total 20352 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 29574 # Number of read requests responded to by this memory
system.physmem.num_reads::total 30642 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 318 # Number of write requests responded to by this memory
system.physmem.num_writes::total 318 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 999179 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 27668290 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 28667469 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 999179 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 999179 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 297508 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 297508 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 297508 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 999179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 27668290 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 28964978 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 136816263 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 36128371 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 36128371 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1086051 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 25676514 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 25568930 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 28040484 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 196465722 # Number of instructions fetch has processed
system.cpu.fetch.Branches 36128371 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 25568930 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 59455138 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 8440333 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 41957570 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 207 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 27323760 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 153045 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 136778320 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.524833 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.343005 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 80075177 58.54% 58.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2168654 1.59% 60.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2999031 2.19% 62.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4111689 3.01% 65.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 8029506 5.87% 71.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 5053851 3.69% 74.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 2898853 2.12% 77.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1472297 1.08% 78.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 29969262 21.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 136778320 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.264065 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.435982 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 40775641 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 32574420 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 46270758 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9832617 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 7324884 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 341365831 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 7324884 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 46092133 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 6411510 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 9224 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 50365166 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 26575403 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 337580749 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 5005 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 24325640 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 73870 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 414916926 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1010481124 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1010477953 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3171 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 341010848 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 73906078 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 481 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 57495301 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 108229908 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 37227556 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 46399442 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 8017088 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 331952532 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2380 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 311468511 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 188619 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 53509766 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 93151802 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1934 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 136778320 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.277177 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.722818 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 29621399 21.66% 21.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 18208303 13.31% 34.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 26183268 19.14% 54.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 31189173 22.80% 76.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 17472478 12.77% 89.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 8789771 6.43% 96.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 3781191 2.76% 98.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1461656 1.07% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 71081 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 136778320 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 22736 1.09% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1942986 92.77% 93.86% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 128630 6.14% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 29247 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 177262228 56.91% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 143 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.92% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 99693377 32.01% 88.93% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 34483516 11.07% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 311468511 # Type of FU issued
system.cpu.iq.rate 2.276546 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2094352 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006724 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 761997211 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 385495678 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 308386892 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 1102 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1693 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 371 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 313533109 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 507 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 52559129 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 17450524 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 94828 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 33225 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 5787805 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3313 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 7324884 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 821379 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 106718 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 331954912 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 49233 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 108229908 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 37227556 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1080 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 29147 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 33225 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 614391 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 577456 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1191847 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 309549319 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 99164391 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1919192 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 133267604 # number of memory reference insts executed
system.cpu.iew.exec_branches 31551799 # Number of branches executed
system.cpu.iew.exec_stores 34103213 # Number of stores executed
system.cpu.iew.exec_rate 2.262518 # Inst execution rate
system.cpu.iew.wb_sent 308913193 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 308387263 # cumulative count of insts written-back
system.cpu.iew.wb_producers 227149501 # num instructions producing a value
system.cpu.iew.wb_consumers 466434365 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.254025 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.486991 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 157988547 # The number of committed instructions
system.cpu.commit.commitCommittedOps 278192462 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 53766564 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1086077 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 129453436 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.148977 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.662392 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 48953386 37.82% 37.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 24330343 18.79% 56.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 17047293 13.17% 69.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12542277 9.69% 79.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3298814 2.55% 82.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 3552746 2.74% 84.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 2756547 2.13% 86.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1133806 0.88% 87.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 15838224 12.23% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 129453436 # Number of insts commited each cycle
system.cpu.commit.committedInsts 157988547 # Number of instructions committed
system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 122219135 # Number of memory references committed
system.cpu.commit.loads 90779384 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 29309705 # Number of branches committed
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.int_insts 278186170 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 15838224 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 445574238 # The number of ROB reads
system.cpu.rob.rob_writes 671251501 # The number of ROB writes
system.cpu.timesIdled 1985 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 37943 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
system.cpu.cpi 0.865988 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.865988 # CPI: Total CPI of All Threads
system.cpu.ipc 1.154750 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.154750 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 705392602 # number of integer regfile reads
system.cpu.int_regfile_writes 373276329 # number of integer regfile writes
system.cpu.fp_regfile_reads 441 # number of floating regfile reads
system.cpu.fp_regfile_writes 230 # number of floating regfile writes
system.cpu.misc_regfile_reads 197984249 # number of misc regfile reads
system.cpu.icache.replacements 87 # number of replacements
system.cpu.icache.tagsinuse 844.199846 # Cycle average of tags in use
system.cpu.icache.total_refs 27322358 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 25392.526022 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 844.199846 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.412207 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.412207 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 27322358 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27322358 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27322358 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27322358 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27322358 # number of overall hits
system.cpu.icache.overall_hits::total 27322358 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1402 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1402 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1402 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1402 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1402 # number of overall misses
system.cpu.icache.overall_misses::total 1402 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 51713500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 51713500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 51713500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 51713500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 51713500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 51713500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27323760 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27323760 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27323760 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27323760 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27323760 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27323760 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36885.520685 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 36885.520685 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 36885.520685 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 36885.520685 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 325 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 325 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 325 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 325 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 325 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39505500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 39505500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39505500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 39505500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39505500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 39505500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36681.058496 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36681.058496 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36681.058496 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36681.058496 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36681.058496 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36681.058496 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2072121 # number of replacements
system.cpu.dcache.tagsinuse 4072.371520 # Cycle average of tags in use
system.cpu.dcache.total_refs 75597840 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2076217 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 36.411339 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 22802887000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4072.371520 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.994231 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.994231 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 44240568 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 44240568 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31357263 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31357263 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 75597831 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 75597831 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 75597831 # number of overall hits
system.cpu.dcache.overall_hits::total 75597831 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2315103 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2315103 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 82488 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 82488 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2397591 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2397591 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2397591 # number of overall misses
system.cpu.dcache.overall_misses::total 2397591 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 16770812000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 16770812000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571570000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1571570000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 18342382000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18342382000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18342382000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18342382000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 46555671 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 46555671 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 77995422 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 77995422 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 77995422 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 77995422 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049728 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.049728 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002624 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002624 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.030740 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.030740 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.030740 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.030740 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7244.088924 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 7244.088924 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19052.104549 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 19052.104549 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 7650.338194 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 7650.338194 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2065063 # number of writebacks
system.cpu.dcache.writebacks::total 2065063 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 320901 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 320901 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 469 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 469 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 321370 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 321370 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 321370 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 321370 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994202 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1994202 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82019 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 82019 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2076221 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2076221 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2076221 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2076221 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6183631000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6183631000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1313937000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1313937000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7497568000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7497568000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7497568000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7497568000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042835 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042835 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.026620 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026620 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3100.804733 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3100.804733 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16019.910021 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16019.910021 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1458 # number of replacements
system.cpu.l2cache.tagsinuse 20067.979072 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4027415 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 30622 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 131.520312 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 19572.608886 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 263.032470 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 232.337716 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.597309 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.008027 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.007090 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.612426 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1993505 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1993513 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2065063 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2065063 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 53141 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 53141 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2046646 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2046654 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2046646 # number of overall hits
system.cpu.l2cache.overall_hits::total 2046654 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 1068 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 582 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1650 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 28992 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 28992 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 29574 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 30642 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 29574 # number of overall misses
system.cpu.l2cache.overall_misses::total 30642 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37986000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20700500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 58686500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 989313000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 989313000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 37986000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1010013500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1047999500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 37986000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1010013500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1047999500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1994087 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1995163 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2065063 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2065063 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 82133 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 82133 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2076220 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2077296 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2076220 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2077296 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992565 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000292 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000827 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352988 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.352988 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992565 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014244 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.014751 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014244 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.014751 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35567.415730 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35567.869416 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35567.575758 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.654801 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.654801 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34201.406566 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34201.406566 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 318 # number of writebacks
system.cpu.l2cache.writebacks::total 318 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 582 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1650 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28992 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 28992 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 29574 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 30642 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 29574 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 30642 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34610000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18859500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53469500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899045000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899045000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34610000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 917904500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 952514500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34610000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 917904500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 952514500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000827 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352988 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352988 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014751 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014751 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32406.367041 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32404.639175 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32405.757576 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.106236 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.106236 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|