blob: cca34d6d035e9b9eba5340fe80914010dede1a83 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.368209 # Number of seconds simulated
sim_ticks 368209254000 # Number of ticks simulated
final_tick 368209254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 606195 # Simulator instruction rate (inst/s)
host_op_rate 1067413 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1412802854 # Simulator tick rate (ticks/s)
host_mem_usage 363612 # Number of bytes of host memory used
host_seconds 260.62 # Real time elapsed on the host
sim_insts 157988583 # Number of instructions simulated
sim_ops 278192520 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory
system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 14528 # Number of bytes written to this memory
system.physmem.bytes_written::total 14528 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 29370 # Number of read requests responded to by this memory
system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory
system.physmem.num_writes::total 227 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 140442 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5104923 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 5245365 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 140442 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 140442 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 39456 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 39456 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 39456 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 140442 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5104923 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5284821 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 736418508 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988583 # Number of instructions committed
system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186228 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 834011910 # number of times the integer registers were read
system.cpu.num_int_register_writes 341010914 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_mem_refs 122219139 # number of memory refs
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 736418508 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 665.897663 # Cycle average of tags in use
system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 665.897663 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits
system.cpu.icache.overall_hits::total 217695401 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
system.cpu.icache.overall_misses::total 808 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 45336000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 45336000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 45336000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 45336000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 45336000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 45336000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56108.910891 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56108.910891 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56108.910891 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56108.910891 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42912000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 42912000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42912000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 42912000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42912000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 42912000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53108.910891 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53108.910891 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
system.cpu.dcache.tagsinuse 4076.463091 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126234114000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.463091 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995230 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995230 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 120152372 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 120152372 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 120152372 # number of overall hits
system.cpu.dcache.overall_hits::total 120152372 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 27487330000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 27487330000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2708348000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2708348000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 30195678000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 30195678000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 30195678000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 30195678000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 122219201 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 122219201 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14018.998123 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14018.998123 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25524.206241 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25524.206241 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14609.664370 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14609.664370 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14609.664370 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14609.664370 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2061794 # number of writebacks
system.cpu.dcache.writebacks::total 2061794 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21605170000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21605170000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2390019500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2390019500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23995189500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23995189500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23995189500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23995189500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11018.998123 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11018.998123 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22524.192104 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22524.192104 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11609.663644 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11609.663644 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1081 # number of replacements
system.cpu.l2cache.tagsinuse 19722.096664 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 19370.042647 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 209.723692 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 142.330324 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.591127 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.006400 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.601871 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2061794 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 77082 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 77082 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data 2037459 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2037459 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 2037459 # number of overall hits
system.cpu.l2cache.overall_hits::total 2037459 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 343 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1151 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 29027 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 29027 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 29370 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 30178 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 808 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 29370 # number of overall misses
system.cpu.l2cache.overall_misses::total 30178 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17836000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 59852000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509433500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1509433500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1527269500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1569285500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1527269500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1569285500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2061794 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2061794 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000175 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000587 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273558 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.273558 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014210 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.014595 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014210 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.014595 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.016295 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.016295 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000.977533 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.977533 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 227 # number of writebacks
system.cpu.l2cache.writebacks::total 227 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 343 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1151 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29027 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 29027 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 29370 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 30178 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 29370 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 30178 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 46040000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1161080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1161080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1174800000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1207120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1174800000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1207120000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000175 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273558 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273558 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
