1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.366358 # Number of seconds simulated
sim_ticks 366358475500 # Number of ticks simulated
final_tick 366358475500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 156500 # Simulator instruction rate (inst/s)
host_op_rate 169511 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 113180486 # Simulator tick rate (ticks/s)
host_mem_usage 245616 # Number of bytes of host memory used
host_seconds 3236.94 # Real time elapsed on the host
sim_insts 506582155 # Number of instructions simulated
sim_ops 548695378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9004224 # Number of bytes read from this memory
system.physmem.bytes_read::total 9225920 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6180352 # Number of bytes written to this memory
system.physmem.bytes_written::total 6180352 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 140691 # Number of read requests responded to by this memory
system.physmem.num_reads::total 144155 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 96568 # Number of write requests responded to by this memory
system.physmem.num_writes::total 96568 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 605134 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 24577633 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 25182767 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 605134 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 605134 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 16869685 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 16869685 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 16869685 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 605134 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 24577633 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42052451 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 144155 # Number of read requests accepted
system.physmem.writeReqs 96568 # Number of write requests accepted
system.physmem.readBursts 144155 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 96568 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 9218240 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue
system.physmem.bytesWritten 6178944 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 9225920 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6180352 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 9365 # Per bank write bursts
system.physmem.perBankRdBursts::1 8967 # Per bank write bursts
system.physmem.perBankRdBursts::2 8978 # Per bank write bursts
system.physmem.perBankRdBursts::3 8700 # Per bank write bursts
system.physmem.perBankRdBursts::4 9448 # Per bank write bursts
system.physmem.perBankRdBursts::5 9342 # Per bank write bursts
system.physmem.perBankRdBursts::6 8938 # Per bank write bursts
system.physmem.perBankRdBursts::7 8105 # Per bank write bursts
system.physmem.perBankRdBursts::8 8575 # Per bank write bursts
system.physmem.perBankRdBursts::9 8679 # Per bank write bursts
system.physmem.perBankRdBursts::10 8775 # Per bank write bursts
system.physmem.perBankRdBursts::11 9474 # Per bank write bursts
system.physmem.perBankRdBursts::12 9378 # Per bank write bursts
system.physmem.perBankRdBursts::13 9522 # Per bank write bursts
system.physmem.perBankRdBursts::14 8708 # Per bank write bursts
system.physmem.perBankRdBursts::15 9081 # Per bank write bursts
system.physmem.perBankWrBursts::0 6205 # Per bank write bursts
system.physmem.perBankWrBursts::1 6092 # Per bank write bursts
system.physmem.perBankWrBursts::2 6005 # Per bank write bursts
system.physmem.perBankWrBursts::3 5814 # Per bank write bursts
system.physmem.perBankWrBursts::4 6161 # Per bank write bursts
system.physmem.perBankWrBursts::5 6174 # Per bank write bursts
system.physmem.perBankWrBursts::6 6015 # Per bank write bursts
system.physmem.perBankWrBursts::7 5497 # Per bank write bursts
system.physmem.perBankWrBursts::8 5724 # Per bank write bursts
system.physmem.perBankWrBursts::9 5822 # Per bank write bursts
system.physmem.perBankWrBursts::10 5961 # Per bank write bursts
system.physmem.perBankWrBursts::11 6444 # Per bank write bursts
system.physmem.perBankWrBursts::12 6310 # Per bank write bursts
system.physmem.perBankWrBursts::13 6277 # Per bank write bursts
system.physmem.perBankWrBursts::14 5996 # Per bank write bursts
system.physmem.perBankWrBursts::15 6049 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 366358446500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 144155 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 96568 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 143662 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2912 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3099 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5531 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5665 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5679 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5677 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5679 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5680 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5705 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5660 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5653 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5593 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5579 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 65262 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 235.919953 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 156.506308 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 241.385533 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 24794 37.99% 37.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18171 27.84% 65.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 7030 10.77% 76.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7953 12.19% 88.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2052 3.14% 91.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1171 1.79% 93.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 739 1.13% 94.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 589 0.90% 95.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 2763 4.23% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 65262 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 25.848887 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 382.035418 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.326992 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.223724 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 2.446858 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17 2657 47.68% 47.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19 2761 49.55% 97.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21 56 1.01% 98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23 29 0.52% 98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25 20 0.36% 99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31 7 0.13% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33 5 0.09% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35 2 0.04% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37 5 0.09% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39 2 0.04% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41 2 0.04% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43 2 0.04% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47 1 0.02% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53 2 0.04% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-57 1 0.02% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-61 1 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads
system.physmem.totQLat 1537104750 # Total ticks spent queuing
system.physmem.totMemAccLat 4237761000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 720175000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10671.74 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29421.74 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 25.16 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 16.87 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.33 # Data bus utilization in percentage
system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
system.physmem.avgWrQLen 20.57 # Average write queue length when enqueuing
system.physmem.readRowHits 110916 # Number of row buffer hits during reads
system.physmem.writeRowHits 64397 # Number of row buffer hits during writes
system.physmem.readRowHitRate 77.01 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 66.69 # Row buffer hit rate for writes
system.physmem.avgGap 1521908.78 # Average gap between requests
system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 248466960 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 135572250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 560157000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 23928256560 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 47486087820 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 178156194000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 250825301550 # Total energy per rank (pJ)
system.physmem_0.averagePower 684.658255 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 296072654000 # Time in different power states
system.physmem_0.memoryStateTime::REF 12233260000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 58046909500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 244634040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 133480875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 562879200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 314740080 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 23928256560 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 47146698135 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 178453904250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 250784593140 # Total energy per rank (pJ)
system.physmem_1.averagePower 684.547137 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 296568978750 # Time in different power states
system.physmem_1.memoryStateTime::REF 12233260000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 57550826250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 132589371 # Number of BP lookups
system.cpu.branchPred.condPredicted 98514041 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 6557944 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 68842060 # Number of BTB lookups
system.cpu.branchPred.BTBHits 64854431 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 94.207569 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 10017867 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17926 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 732716951 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506582155 # Number of instructions committed
system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed
system.cpu.discardedOps 13466923 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.446393 # CPI: cycles per instruction
system.cpu.ipc 0.691375 # IPC: instructions per cycle
system.cpu.tickCycles 695825303 # Number of cycles that the object actually ticked
system.cpu.idleCycles 36891648 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1139854 # number of replacements
system.cpu.dcache.tags.tagsinuse 4070.954710 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 171283379 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1143950 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 149.729778 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954710 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 346821558 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 346821558 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 114764882 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114764882 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53538642 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 53538642 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 2773 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 2773 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168303524 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168303524 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168306297 # number of overall hits
system.cpu.dcache.overall_hits::total 168306297 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 854741 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 854741 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 700664 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 700664 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 20 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 20 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 1555405 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1555405 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1555425 # number of overall misses
system.cpu.dcache.overall_misses::total 1555425 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14025846982 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 14025846982 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22027401500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 22027401500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 36053248482 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 36053248482 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 36053248482 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 36053248482 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 115619623 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 115619623 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 169858929 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 169858929 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 169861722 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 169861722 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007161 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.007161 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16409.470216 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16409.470216 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31437.895339 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31437.895339 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23179.331738 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23179.331738 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23179.033693 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23179.033693 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1068578 # number of writebacks
system.cpu.dcache.writebacks::total 1068578 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66974 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 66974 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344497 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 344497 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 411471 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 411471 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 411471 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 411471 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787767 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 787767 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356167 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 356167 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 16 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 16 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1143934 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1143934 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1143950 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1143950 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930687015 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930687015 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10965407750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10965407750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1449000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1449000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22896094765 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 22896094765 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22897543765 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 22897543765 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005729 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005729 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15144.943892 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15144.943892 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30787.264822 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30787.264822 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 90562.500000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 90562.500000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20015.223575 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20015.223575 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20016.210293 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20016.210293 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 17681 # number of replacements
system.cpu.icache.tags.tagsinuse 1190.210021 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 200953825 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 19553 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 10277.390937 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1190.210021 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.581157 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.581157 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1410 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 401966309 # Number of tag accesses
system.cpu.icache.tags.data_accesses 401966309 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 200953825 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 200953825 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 200953825 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 200953825 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 200953825 # number of overall hits
system.cpu.icache.overall_hits::total 200953825 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 19553 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 19553 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 19553 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 19553 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 19553 # number of overall misses
system.cpu.icache.overall_misses::total 19553 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 493452495 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 493452495 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 493452495 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 493452495 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 493452495 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 493452495 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 200973378 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 200973378 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 200973378 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 200973378 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 200973378 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 200973378 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25236.664195 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 25236.664195 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25236.664195 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 25236.664195 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25236.664195 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25236.664195 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19553 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 19553 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 19553 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 19553 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 19553 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 19553 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 462727005 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 462727005 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 462727005 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 462727005 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 462727005 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 462727005 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23665.269012 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23665.269012 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23665.269012 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 23665.269012 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23665.269012 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23665.269012 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 111401 # number of replacements
system.cpu.l2cache.tags.tagsinuse 27648.660571 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1684556 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 142587 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 11.814233 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 163811788500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23520.663233 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.227273 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 3737.770065 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.717794 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011909 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.114068 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.843770 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31186 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4927 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25871 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 18355652 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 18355652 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 16087 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 747708 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 763795 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1068578 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1068578 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 255536 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 255536 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 16087 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1003244 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1019331 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 16087 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1003244 # number of overall hits
system.cpu.l2cache.overall_hits::total 1019331 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3466 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 39825 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 43291 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 100881 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 100881 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3466 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 140706 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 144172 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3466 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 140706 # number of overall misses
system.cpu.l2cache.overall_misses::total 144172 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 274192500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3286653000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3560845500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7928578250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7928578250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 274192500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11215231250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 11489423750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 274192500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11215231250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 11489423750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 19553 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 787533 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 807086 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1068578 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1068578 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356417 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 356417 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 19553 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1143950 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1163503 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 19553 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1143950 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1163503 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177262 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050569 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.053639 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283042 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.283042 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177262 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.123000 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.123912 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177262 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.123000 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.123912 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79109.203693 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82527.382298 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 82253.713243 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78593.374867 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78593.374867 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79109.203693 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79706.844413 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79692.476695 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79109.203693 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79706.844413 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79692.476695 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 96568 # number of writebacks
system.cpu.l2cache.writebacks::total 96568 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3464 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39810 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 43274 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100881 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 100881 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3464 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 140691 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 144155 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3464 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 140691 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 144155 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 230478500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2786732250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3017210750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6666945750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6666945750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230478500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9453678000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 9684156500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230478500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9453678000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 9684156500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050550 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283042 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283042 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123897 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123897 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66535.363741 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70000.810098 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69723.407820 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66087.229012 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66087.229012 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66535.363741 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.617993 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67178.776317 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66535.363741 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.617993 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67178.776317 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 807086 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 807086 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1068578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39106 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356478 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3395584 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1251392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141601792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 142853184 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2232081 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 2232081 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2232081 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2184618500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 30027495 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1744688735 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.trans_dist::ReadReq 43274 # Transaction distribution
system.membus.trans_dist::ReadResp 43274 # Transaction distribution
system.membus.trans_dist::Writeback 96568 # Transaction distribution
system.membus.trans_dist::ReadExReq 100881 # Transaction distribution
system.membus.trans_dist::ReadExResp 100881 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384878 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 384878 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15406272 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 15406272 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 240723 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 240723 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 240723 # Request fanout histogram
system.membus.reqLayer0.occupancy 679184500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 765222500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
|