path: root/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.363609                       # Number of seconds simulated
sim_ticks                                363608804500                       # Number of ticks simulated
final_tick                               363608804500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 100066                       # Simulator instruction rate (inst/s)
host_op_rate                                   108385                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               71824585                       # Simulator tick rate (ticks/s)
host_mem_usage                                 304984                       # Number of bytes of host memory used
host_seconds                                  5062.46                       # Real time elapsed on the host
sim_insts                                   506579366                       # Number of instructions simulated
sim_ops                                     548692589                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            179584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9028480                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9208064                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       179584                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          179584                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6218624                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6218624                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2806                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             141070                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                143876                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97166                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97166                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               493893                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             24830202                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                25324095                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          493893                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             493893                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          17102512                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               17102512                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          17102512                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              493893                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            24830202                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               42426607                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        143876                       # Number of read requests accepted
system.physmem.writeReqs                        97166                       # Number of write requests accepted
system.physmem.readBursts                      143876                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97166                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9201472                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6592                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6217344                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9208064                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6218624                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      103                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9345                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8917                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8955                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8654                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9386                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9354                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8955                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8104                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8603                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8629                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8742                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9454                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9335                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9509                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8712                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9119                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6212                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6095                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6031                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5882                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6240                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6242                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6046                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5509                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5790                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5862                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5980                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6494                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6352                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6321                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5998                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6092                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    363608778500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  143876                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97166                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    143433                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       320                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2923                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5694                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5686                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5721                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5699                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5724                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5731                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5738                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5711                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5643                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5621                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65427                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      235.654638                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     156.256012                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     241.782834                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24843     37.97%     37.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18425     28.16%     66.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6952     10.63%     76.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7899     12.07%     88.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2020      3.09%     91.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1104      1.69%     93.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          778      1.19%     94.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          662      1.01%     95.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         2744      4.19%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65427                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5612                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.618496                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      380.574654                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5610     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5612                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5612                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.310406                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.214262                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.369355                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            2682     47.79%     47.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            2777     49.48%     97.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              56      1.00%     98.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              33      0.59%     98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              17      0.30%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              10      0.18%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29               7      0.12%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31               5      0.09%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               7      0.12%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35               4      0.07%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               3      0.05%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41               2      0.04%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43               4      0.07%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49               1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51               1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53               1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-73               1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::98-99               1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5612                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1539890250                       # Total ticks spent queuing
system.physmem.totMemAccLat                4235634000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    718865000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10710.57                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29460.57                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          25.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          17.10                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       25.32                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       17.10                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        19.45                       # Average write queue length when enqueuing
system.physmem.readRowHits                     110770                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64716                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.05                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.60                       # Row buffer hit rate for writes
system.physmem.avgGap                      1508487.23                       # Average gap between requests
system.physmem.pageHitRate                      72.83                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  249041520                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  135885750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 558807600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                312407280                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            23748734880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            47272879035                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           176694091500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             248971847565                       # Total energy per rank (pJ)
system.physmem_0.averagePower              684.736255                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   293641319750                       # Time in different power states
system.physmem_0.memoryStateTime::REF     12141480000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     57820495250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  245269080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  133827375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 562192800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                316684080                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            23748734880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            46853247600                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           177062189250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             248922145065                       # Total energy per rank (pJ)
system.physmem_1.averagePower              684.599560                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   294255473500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     12141480000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     57206580500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               131890227                       # Number of BP lookups
system.cpu.branchPred.condPredicted          98029520                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           6134595                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             68518889                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                64416393                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             94.012606                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 9980436                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              18277                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        727217609                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   506579366                       # Number of instructions committed
system.cpu.committedOps                     548692589                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      13188504                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.435545                       # CPI: cycles per instruction
system.cpu.ipc                               0.696599                       # IPC: instructions per cycle
system.cpu.tickCycles                       690736700                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        36480909                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           1141376                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4070.790078                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           171162589                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1145472                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            149.425380                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4896334500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4070.790078                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993845                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993845                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          551                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3500                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         346584178                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        346584178                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    114644865                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114644865                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     53537898                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53537898                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2744                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2744                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     168182763                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168182763                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    168185507                       # number of overall hits
system.cpu.dcache.overall_hits::total       168185507                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       855598                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        855598                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       701151                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       701151                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           15                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           15                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1556749                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1556749                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1556764                       # number of overall misses
system.cpu.dcache.overall_misses::total       1556764                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  14056066500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14056066500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  21917357000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  21917357000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  35973423500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  35973423500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  35973423500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  35973423500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    115500463                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    115500463                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2759                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2759                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    169739512                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    169739512                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    169742271                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    169742271                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007408                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007408                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012927                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012927                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005437                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.005437                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009171                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009171                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009171                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009171                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.353619                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.353619                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31259.111090                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31259.111090                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.043429                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23108.043429                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23107.820774                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23107.820774                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1069283                       # number of writebacks
system.cpu.dcache.writebacks::total           1069283                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66543                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        66543                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344746                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       344746                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       411289                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       411289                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       411289                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       411289                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       789055                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       789055                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356405                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356405                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1145460                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1145460                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1145472                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1145472                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12372636000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12372636000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11132196500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11132196500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       944000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       944000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23504832500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23504832500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23505776500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  23505776500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006832                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006832                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006571                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006571                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004349                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004349                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006748                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006748                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006748                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006748                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15680.321397                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15680.321397                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31234.681051                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31234.681051                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78666.666667                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78666.666667                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20519.994151                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20519.994151                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20520.603297                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20520.603297                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             17687                       # number of replacements
system.cpu.icache.tags.tagsinuse          1188.299437                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           199347924                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             19559                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          10192.132727                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1188.299437                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.580224                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.580224                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          305                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1404                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         398754525                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        398754525                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    199347924                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       199347924                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     199347924                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        199347924                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    199347924                       # number of overall hits
system.cpu.icache.overall_hits::total       199347924                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        19559                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         19559                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        19559                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          19559                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        19559                       # number of overall misses
system.cpu.icache.overall_misses::total         19559                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    449446000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    449446000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    449446000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    449446000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    449446000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    449446000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    199367483                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    199367483                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    199367483                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    199367483                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    199367483                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    199367483                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000098                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000098                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000098                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000098                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000098                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000098                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22978.986656                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22978.986656                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22978.986656                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22978.986656                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22978.986656                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22978.986656                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks        17687                       # number of writebacks
system.cpu.icache.writebacks::total             17687                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19559                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        19559                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        19559                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        19559                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        19559                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        19559                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    429887000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    429887000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    429887000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    429887000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    429887000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    429887000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000098                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000098                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000098                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21978.986656                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21978.986656                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21978.986656                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21978.986656                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21978.986656                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21978.986656                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           112304                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27637.803257                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1771245                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           143514                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.341967                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     163256914000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23514.215736                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   307.353699                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  3816.233823                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.717597                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009380                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.116462                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.843439                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31210                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          321                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4944                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25846                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.952454                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         19053033                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        19053033                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks      1069283                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      1069283                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        17449                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        17449                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       255738                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       255738                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        16752                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        16752                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       748650                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       748650                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        16752                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1004388                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1021140                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        16752                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1004388                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1021140                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       100917                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       100917                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2807                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         2807                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        40167                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        40167                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2807                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141084                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        143891                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2807                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141084                       # number of overall misses
system.cpu.l2cache.overall_misses::total       143891                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7914773500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7914773500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    223970500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    223970500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3305851000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   3305851000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    223970500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11220624500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11444595000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    223970500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11220624500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11444595000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      1069283                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      1069283                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        17449                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        17449                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       356655                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356655                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        19559                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        19559                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       788817                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       788817                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        19559                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1145472                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1165031                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        19559                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1145472                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1165031                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282954                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.282954                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.143514                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.143514                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.050921                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.050921                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.143514                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.123167                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.123508                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.143514                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.123167                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.123508                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78428.545240                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78428.545240                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79789.989312                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79789.989312                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82302.661389                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82302.661389                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79789.989312                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79531.516685                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79536.558923                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79789.989312                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79531.516685                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79536.558923                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97166                       # number of writebacks
system.cpu.l2cache.writebacks::total            97166                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           14                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           14                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100917                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       100917                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2806                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2806                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        40153                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        40153                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2806                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141070                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       143876                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2806                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141070                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       143876                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6905603500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6905603500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    195670500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    195670500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2903188500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2903188500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    195670500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9808792000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  10004462500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    195670500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9808792000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  10004462500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282954                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282954                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.143463                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.143463                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050903                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050903                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.143463                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123154                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.123495                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.143463                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123154                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.123495                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68428.545240                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68428.545240                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69732.893799                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69732.893799                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.152940                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.152940                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69732.893799                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.381584                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69535.311657                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69732.893799                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.381584                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69535.311657                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      2324094                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159133                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4986                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2609                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2606                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp        808376                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      1166449                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        17687                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        87231                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       356655                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       356655                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        19559                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       788817                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56805                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3432320                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3489125                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2383744                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141744320                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          144128064                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      112304                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      1277335                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.006003                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.077277                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            1269670     99.40%     99.40% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               7662      0.60%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  3      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1277335                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2249017000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      29357961                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1718215984                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.membus.trans_dist::ReadResp              42959                       # Transaction distribution
system.membus.trans_dist::WritebackDirty        97166                       # Transaction distribution
system.membus.trans_dist::CleanEvict            12529                       # Transaction distribution
system.membus.trans_dist::ReadExReq            100917                       # Transaction distribution
system.membus.trans_dist::ReadExResp           100917                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         42959                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397447                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 397447                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15426688                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15426688                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            253571                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  253571    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              253571                       # Request fanout histogram
system.membus.reqLayer0.occupancy           685058500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy          763682500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------