blob: 63d0e7cc10865bd5897c08e6a49748bce604af10 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.361826 # Number of seconds simulated
sim_ticks 361826015500 # Number of ticks simulated
final_tick 361826015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 231274 # Simulator instruction rate (inst/s)
host_op_rate 250500 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 165186980 # Simulator tick rate (ticks/s)
host_mem_usage 321304 # Number of bytes of host memory used
host_seconds 2190.40 # Real time elapsed on the host
sim_insts 506582155 # Number of instructions simulated
sim_ops 548695378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 9220736 # Number of bytes read from this memory
system.physmem.bytes_read::total 9220736 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6177024 # Number of bytes written to this memory
system.physmem.bytes_written::total 6177024 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 144074 # Number of read requests responded to by this memory
system.physmem.num_reads::total 144074 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 96516 # Number of write requests responded to by this memory
system.physmem.num_writes::total 96516 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 25483894 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 25483894 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 612007 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 612007 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 17071807 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 17071807 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 17071807 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 25483894 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42555702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 144074 # Number of read requests accepted
system.physmem.writeReqs 96516 # Number of write requests accepted
system.physmem.readBursts 144074 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 96516 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 9213952 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue
system.physmem.bytesWritten 6175488 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 9220736 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6177024 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 9331 # Per bank write bursts
system.physmem.perBankRdBursts::1 8974 # Per bank write bursts
system.physmem.perBankRdBursts::2 8995 # Per bank write bursts
system.physmem.perBankRdBursts::3 8704 # Per bank write bursts
system.physmem.perBankRdBursts::4 9445 # Per bank write bursts
system.physmem.perBankRdBursts::5 9338 # Per bank write bursts
system.physmem.perBankRdBursts::6 8941 # Per bank write bursts
system.physmem.perBankRdBursts::7 8096 # Per bank write bursts
system.physmem.perBankRdBursts::8 8562 # Per bank write bursts
system.physmem.perBankRdBursts::9 8674 # Per bank write bursts
system.physmem.perBankRdBursts::10 8773 # Per bank write bursts
system.physmem.perBankRdBursts::11 9481 # Per bank write bursts
system.physmem.perBankRdBursts::12 9368 # Per bank write bursts
system.physmem.perBankRdBursts::13 9509 # Per bank write bursts
system.physmem.perBankRdBursts::14 8709 # Per bank write bursts
system.physmem.perBankRdBursts::15 9068 # Per bank write bursts
system.physmem.perBankWrBursts::0 6188 # Per bank write bursts
system.physmem.perBankWrBursts::1 6094 # Per bank write bursts
system.physmem.perBankWrBursts::2 6004 # Per bank write bursts
system.physmem.perBankWrBursts::3 5817 # Per bank write bursts
system.physmem.perBankWrBursts::4 6158 # Per bank write bursts
system.physmem.perBankWrBursts::5 6168 # Per bank write bursts
system.physmem.perBankWrBursts::6 6012 # Per bank write bursts
system.physmem.perBankWrBursts::7 5489 # Per bank write bursts
system.physmem.perBankWrBursts::8 5725 # Per bank write bursts
system.physmem.perBankWrBursts::9 5819 # Per bank write bursts
system.physmem.perBankWrBursts::10 5961 # Per bank write bursts
system.physmem.perBankWrBursts::11 6448 # Per bank write bursts
system.physmem.perBankWrBursts::12 6304 # Per bank write bursts
system.physmem.perBankWrBursts::13 6266 # Per bank write bursts
system.physmem.perBankWrBursts::14 5996 # Per bank write bursts
system.physmem.perBankWrBursts::15 6043 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 361825986500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 144074 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 96516 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 143606 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5676 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5658 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5685 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5655 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5675 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5648 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5690 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5726 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5661 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 64715 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 237.790435 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 157.392081 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 243.201287 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 24444 37.77% 37.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18161 28.06% 65.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6768 10.46% 76.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7845 12.12% 88.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2212 3.42% 91.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1114 1.72% 93.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 793 1.23% 94.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 596 0.92% 95.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 2782 4.30% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 64715 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 25.855065 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 382.360630 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 5564 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.329741 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.226111 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 2.490816 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17 2624 47.13% 47.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19 2801 50.31% 97.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21 48 0.86% 98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23 25 0.45% 98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25 21 0.38% 99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27 12 0.22% 99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29 8 0.14% 99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31 6 0.11% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33 3 0.05% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35 4 0.07% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37 1 0.02% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39 5 0.09% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51 1 0.02% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53 1 0.02% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-57 1 0.02% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59 1 0.02% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-69 2 0.04% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads
system.physmem.totQLat 1536727500 # Total ticks spent queuing
system.physmem.totMemAccLat 4236127500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 719840000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 25.47 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.33 # Data bus utilization in percentage
system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing
system.physmem.readRowHits 111270 # Number of row buffer hits during reads
system.physmem.writeRowHits 64468 # Number of row buffer hits during writes
system.physmem.readRowHitRate 77.29 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes
system.physmem.avgGap 1503911.16 # Average gap between requests
system.physmem.pageHitRate 73.08 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 254085865250 # Time in different power states
system.physmem.memoryStateTime::REF 12081940000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 95653103250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 42555702 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 43212 # Transaction distribution
system.membus.trans_dist::ReadResp 43212 # Transaction distribution
system.membus.trans_dist::Writeback 96516 # Transaction distribution
system.membus.trans_dist::ReadExReq 100862 # Transaction distribution
system.membus.trans_dist::ReadExResp 100862 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384664 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 384664 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15397760 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 15397760 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 15397760 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1075054000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 1362559750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 132256489 # Number of BP lookups
system.cpu.branchPred.condPredicted 98266035 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 6550672 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 68852239 # Number of BTB lookups
system.cpu.branchPred.BTBHits 64692489 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 93.958439 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 9992276 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17882 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 723652031 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506582155 # Number of instructions committed
system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed
system.cpu.discardedOps 14122871 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.428499 # CPI: cycles per instruction
system.cpu.ipc 0.700036 # IPC: instructions per cycle
system.cpu.tickCycles 687771211 # Number of cycles that the object actually ticked
system.cpu.idleCycles 35880820 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 17660 # number of replacements
system.cpu.icache.tags.tagsinuse 1187.686040 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 200323378 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 19531 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 10256.688239 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1187.686040 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.579925 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.579925 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 400705349 # Number of tag accesses
system.cpu.icache.tags.data_accesses 400705349 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 200323378 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 200323378 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 200323378 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 200323378 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 200323378 # number of overall hits
system.cpu.icache.overall_hits::total 200323378 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 19531 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 19531 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 19531 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 19531 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 19531 # number of overall misses
system.cpu.icache.overall_misses::total 19531 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 466485747 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 466485747 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 466485747 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 466485747 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 466485747 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 466485747 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 200342909 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 200342909 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 200342909 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 200342909 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 200342909 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 200342909 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23884.375966 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 23884.375966 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 23884.375966 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 23884.375966 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19531 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 19531 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 19531 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 19531 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 19531 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 19531 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426041253 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 426041253 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426041253 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 426041253 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426041253 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 426041253 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21813.591368 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21813.591368 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 394741942 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 806872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 806872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1068421 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 356393 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 356393 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39062 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355889 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3394951 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1249984 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141577920 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 142827904 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 142827904 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 2184264000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 29987747 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1744465986 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 111319 # number of replacements
system.cpu.l2cache.tags.tagsinuse 27632.304905 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1684536 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 142508 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 11.820642 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 162493519500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23524.678269 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4107.626636 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.717916 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125355 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.843271 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4925 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25872 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 18352389 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 18352389 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 763644 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 763644 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1068421 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1068421 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst 255531 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 255531 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1019175 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1019175 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1019175 # number of overall hits
system.cpu.l2cache.overall_hits::total 1019175 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 43228 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 43228 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst 100862 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 100862 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 144090 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 144090 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 144090 # number of overall misses
system.cpu.l2cache.overall_misses::total 144090 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3220977500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3220977500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7166346750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7166346750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 10387324250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10387324250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 10387324250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10387324250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 806872 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 806872 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1068421 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1068421 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356393 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 356393 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1163265 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1163265 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1163265 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1163265 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053575 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.053575 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283008 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.283008 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123867 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.123867 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123867 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.123867 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74511.369945 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74511.369945 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71051.007813 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71051.007813 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72089.140468 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72089.140468 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 96516 # number of writebacks
system.cpu.l2cache.writebacks::total 96516 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43212 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 43212 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100862 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 100862 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 144074 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 144074 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 144074 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 144074 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2672872000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2672872000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5889125250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5889125250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8561997250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8561997250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8561997250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8561997250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053555 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053555 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123853 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123853 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123853 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123853 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61854.855133 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61854.855133 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58387.948385 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58387.948385 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59427.774963 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59427.774963 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59427.774963 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59427.774963 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 1139638 # number of replacements
system.cpu.dcache.tags.tagsinuse 4071.125159 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 169305637 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1143734 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 148.028857 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 4807181250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.125159 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst 0.993927 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993927 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 342864800 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 342864800 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst 112789835 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 112789835 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst 53538720 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 53538720 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst 166328555 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 166328555 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst 166328555 # number of overall hits
system.cpu.dcache.overall_hits::total 166328555 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst 854310 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 854310 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst 700586 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 700586 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.inst 1554896 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1554896 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst 1554896 # number of overall misses
system.cpu.dcache.overall_misses::total 1554896 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13696134233 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 13696134233 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20619900500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20619900500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst 34316034733 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 34316034733 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst 34316034733 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 34316034733 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst 113644145 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 113644145 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst 167883451 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 167883451 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst 167883451 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 167883451 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007517 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.007517 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst 0.009262 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009262 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst 0.009262 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009262 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16031.808399 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16031.808399 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29432.361623 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29432.361623 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22069.665581 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22069.665581 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks
system.cpu.dcache.writebacks::total 1068421 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66718 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 66718 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344444 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 344444 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst 411162 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 411162 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst 411162 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 411162 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787592 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 787592 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356142 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 356142 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst 1143734 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1143734 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 1143734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1143734 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11245323264 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11245323264 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10075452250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10075452250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21320775514 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 21320775514 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21320775514 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 21320775514 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.107528 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.107528 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28290.547731 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28290.547731 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|