path: root/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.362632                       # Number of seconds simulated
sim_ticks                                362631828500                       # Number of ticks simulated
final_tick                               362631828500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 177215                       # Simulator instruction rate (inst/s)
host_op_rate                                   191948                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              126858592                       # Simulator tick rate (ticks/s)
host_mem_usage                                 271160                       # Number of bytes of host memory used
host_seconds                                  2858.55                       # Real time elapsed on the host
sim_insts                                   506579366                       # Number of instructions simulated
sim_ops                                     548692589                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            179456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9032064                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9211520                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       179456                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          179456                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6221440                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6221440                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2804                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             141126                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                143930                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97210                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97210                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               494871                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             24906981                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                25401852                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          494871                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             494871                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          17156354                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               17156354                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          17156354                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              494871                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            24906981                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               42558206                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        143930                       # Number of read requests accepted
system.physmem.writeReqs                        97210                       # Number of write requests accepted
system.physmem.readBursts                      143930                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97210                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9204736                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6784                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6219456                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9211520                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6221440                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      106                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9406                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8921                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8949                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8657                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9384                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9355                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8962                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8101                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8596                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8628                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8740                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9454                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9340                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9510                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8709                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9112                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6249                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6105                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6032                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5882                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6237                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6240                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6051                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5508                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5781                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5861                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5978                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6494                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6355                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6320                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6000                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6086                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    362631802500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  143930                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97210                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    143484                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       320                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5566                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5692                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5699                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5705                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5705                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5703                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5710                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5731                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5733                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5740                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5717                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5686                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5636                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5622                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65461                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      235.617299                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     156.242018                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     241.589954                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24858     37.97%     37.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18413     28.13%     66.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6961     10.63%     76.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7914     12.09%     88.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2009      3.07%     91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1136      1.74%     93.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          792      1.21%     94.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          657      1.00%     95.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         2721      4.16%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65461                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5611                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.630191                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      380.618779                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5609     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5611                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5611                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.319373                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.223479                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.351913                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            2643     47.10%     47.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            2820     50.26%     97.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              52      0.93%     98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              28      0.50%     98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              21      0.37%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27               8      0.14%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29               6      0.11%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31               9      0.16%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               4      0.07%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35               6      0.11%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               5      0.09%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41               1      0.02%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43               3      0.05%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45               2      0.04%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::70-71               1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-73               1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::90-91               1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5611                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1538291500                       # Total ticks spent queuing
system.physmem.totMemAccLat                4234991500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    719120000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10695.65                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29445.65                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          25.38                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          17.15                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       25.40                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       17.16                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        19.56                       # Average write queue length when enqueuing
system.physmem.readRowHits                     110801                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64737                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.04                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.60                       # Row buffer hit rate for writes
system.physmem.avgGap                      1503822.69                       # Average gap between requests
system.physmem.pageHitRate                      72.83                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  249185160                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  135964125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 559455000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                312906240                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            23685164880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            47417547600                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           175983265500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             248343488505                       # Total energy per rank (pJ)
system.physmem_0.averagePower              684.841129                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   292457177000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     12108980000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     58063198250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  245586600                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  134000625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 562138200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                316684080                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            23685164880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            46768401675                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           176552684250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             248264660310                       # Total energy per rank (pJ)
system.physmem_1.averagePower              684.623774                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   293406599500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     12108980000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     57113763250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               131880511                       # Number of BP lookups
system.cpu.branchPred.condPredicted          98032974                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           5909980                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             68420287                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                60518878                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             88.451658                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 9982385                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              18500                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         3889648                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            3881527                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             8121                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        53795                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        725263657                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   506579366                       # Number of instructions committed
system.cpu.committedOps                     548692589                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      12911806                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.431688                       # CPI: cycles per instruction
system.cpu.ipc                               0.698476                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu               375609862     68.46%     68.46% # Class of committed instruction
system.cpu.op_class_0::IntMult                 339219      0.06%     68.52% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                3      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::MemRead              115883283     21.12%     89.64% # Class of committed instruction
system.cpu.op_class_0::MemWrite              56860222     10.36%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                548692589                       # Class of committed instruction
system.cpu.tickCycles                       688919604                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        36344053                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           1141477                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4070.722142                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           170992714                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1145573                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            149.263918                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4896334500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4070.722142                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993829                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993829                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          553                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3497                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         346245015                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        346245015                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    114475063                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114475063                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     53537828                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53537828                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2741                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2741                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     168012891                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168012891                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    168015632                       # number of overall hits
system.cpu.dcache.overall_hits::total       168015632                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       855770                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        855770                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       701221                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       701221                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           16                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           16                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1556991                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1556991                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1557007                       # number of overall misses
system.cpu.dcache.overall_misses::total       1557007                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  14058873500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14058873500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  21921294000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  21921294000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  35980167500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  35980167500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  35980167500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  35980167500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    115330833                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    115330833                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2757                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2757                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    169569882                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    169569882                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    169572639                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    169572639                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007420                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007420                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012928                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012928                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005803                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.005803                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009182                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009182                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009182                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009182                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.331795                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.331795                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31261.605115                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31261.605115                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.783224                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23108.783224                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23108.545755                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      1069336                       # number of writebacks
system.cpu.dcache.writebacks::total           1069336                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66650                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        66650                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344781                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       344781                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       411431                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       411431                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       411431                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       411431                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       789120                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       789120                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356440                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356440                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           13                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           13                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1145560                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1145560                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1145573                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1145573                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12372328000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12372328000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11135047500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11135047500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1042000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1042000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23507375500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23507375500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23508417500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  23508417500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006842                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006842                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006572                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006572                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004715                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004715                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006756                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006756                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006756                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006756                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.639497                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.639497                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485                       # average overall mshr miss latency
system.cpu.icache.tags.replacements             18130                       # number of replacements
system.cpu.icache.tags.tagsinuse          1186.413401                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           198770599                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             20001                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           9938.033048                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1186.413401                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.579303                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.579303                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1871                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          312                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1397                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.913574                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         397601201                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        397601201                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    198770599                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       198770599                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     198770599                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        198770599                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    198770599                       # number of overall hits
system.cpu.icache.overall_hits::total       198770599                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        20001                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         20001                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        20001                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          20001                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        20001                       # number of overall misses
system.cpu.icache.overall_misses::total         20001                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    455038500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    455038500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    455038500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    455038500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    455038500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    455038500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    198790600                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    198790600                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    198790600                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    198790600                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    198790600                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    198790600                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000101                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000101                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000101                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000101                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000101                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000101                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22750.787461                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22750.787461                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22750.787461                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22750.787461                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22750.787461                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks        18130                       # number of writebacks
system.cpu.icache.writebacks::total             18130                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        20001                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        20001                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        20001                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        20001                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        20001                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        20001                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    435037500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    435037500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    435037500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    435037500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    435037500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    435037500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000101                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000101                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000101                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461                       # average overall mshr miss latency
system.cpu.l2cache.tags.replacements           112376                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27628.930561                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1772118                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           143588                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.341686                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     163251686000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   308.787313                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  3819.558908                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.717181                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009423                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.116564                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.843168                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31212                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          324                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4939                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25849                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.952515                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         19061751                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        19061751                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks      1069336                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      1069336                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        17893                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        17893                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       255742                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       255742                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        17196                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        17196                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       748691                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       748691                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        17196                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1004433                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1021629                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        17196                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1004433                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1021629                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       100949                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       100949                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2805                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         2805                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        40191                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        40191                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2805                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141140                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        143945                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2805                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141140                       # number of overall misses
system.cpu.l2cache.overall_misses::total       143945                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7917540500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7917540500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    223778500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    223778500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3305085000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   3305085000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    223778500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11222625500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11446404000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    223778500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11222625500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11446404000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      1069336                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      1069336                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        17893                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        17893                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       356691                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356691                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        20001                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        20001                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       788882                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       788882                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        20001                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1145573                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1165574                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        20001                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1145573                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1165574                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.283015                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.283015                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.140243                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.140243                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.050947                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.050947                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.140243                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.123205                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.123497                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.140243                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.123205                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.123497                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78431.093919                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78431.093919                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79778.431373                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79778.431373                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82234.455475                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82234.455475                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79778.431373                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79514.138444                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79519.288617                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79778.431373                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79519.288617                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        97210                       # number of writebacks
system.cpu.l2cache.writebacks::total            97210                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           14                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           14                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100949                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       100949                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2804                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2804                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        40177                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        40177                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2804                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141126                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       143930                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2804                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141126                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       143930                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6908050500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6908050500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    195670500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    195670500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2902356000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2902356000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    195670500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9810406500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  10006077000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    195670500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9810406500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  10006077000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283015                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283015                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.140193                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.140193                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050929                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050929                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.140193                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123192                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.123484                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.140193                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123192                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.123484                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68431.093919                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68431.093919                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69782.631954                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69782.631954                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      2325181                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159677                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4997                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2608                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2605                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp        808883                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      1166546                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        18130                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        87307                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       356691                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       356691                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        20001                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       788882                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58132                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3432623                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3490755                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2440384                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141754176                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          144194560                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      112376                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      1277950                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.006008                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.077309                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            1270275     99.40%     99.40% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               7672      0.60%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  3      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1277950                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2250056500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      30027947                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1718367983                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.membus.trans_dist::ReadResp              42981                       # Transaction distribution
system.membus.trans_dist::WritebackDirty        97210                       # Transaction distribution
system.membus.trans_dist::CleanEvict            12558                       # Transaction distribution
system.membus.trans_dist::ReadExReq            100949                       # Transaction distribution
system.membus.trans_dist::ReadExResp           100949                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         42981                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397628                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 397628                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15432960                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15432960                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            253698                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  253698    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              253698                       # Request fanout histogram
system.membus.reqLayer0.occupancy           685564500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy          763995250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------