path: root/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.365317                       # Number of seconds simulated
sim_ticks                                365317233000                       # Number of ticks simulated
final_tick                               365317233000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 241300                       # Simulator instruction rate (inst/s)
host_op_rate                                   261360                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              174011250                       # Simulator tick rate (ticks/s)
host_mem_usage                                 315696                       # Number of bytes of host memory used
host_seconds                                  2099.39                       # Real time elapsed on the host
sim_insts                                   506582155                       # Number of instructions simulated
sim_ops                                     548695378                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst           9226048                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9226048                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       222144                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          222144                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6179904                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6179904                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst             144157                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                144157                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           96561                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                96561                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             25254894                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                25254894                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          608085                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             608085                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          16916541                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               16916541                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          16916541                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            25254894                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               42171435                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        144157                       # Number of read requests accepted
system.physmem.writeReqs                        96561                       # Number of write requests accepted
system.physmem.readBursts                      144157                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      96561                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9219904                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6144                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6178688                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9226048                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6179904                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       96                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9347                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8970                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8998                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8695                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9455                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9342                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8947                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8101                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8578                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8679                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8774                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9477                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9374                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9525                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8712                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9087                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6196                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6092                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6006                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5813                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6163                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6172                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6014                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5493                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5728                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5823                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5962                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6445                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6308                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6282                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5997                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6048                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    365317203500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  144157                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  96561                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    143694                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       347                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2939                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5543                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5691                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5692                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5666                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5669                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5692                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5633                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5643                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5596                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5580                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65080                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      236.601352                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     156.588709                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     242.751381                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24737     38.01%     38.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18138     27.87%     65.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6930     10.65%     76.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7871     12.09%     88.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2125      3.27%     91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1134      1.74%     93.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          708      1.09%     94.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          644      0.99%     95.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         2793      4.29%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65080                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5572                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.854092                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      382.114973                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5569     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            2      0.04%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5572                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5572                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.326274                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.230410                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.286782                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            2628     47.16%     47.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            2789     50.05%     97.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              53      0.95%     98.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              30      0.54%     98.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              23      0.41%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27               9      0.16%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29               9      0.16%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31               6      0.11%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               7      0.13%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35               3      0.05%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               1      0.02%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39               4      0.07%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41               1      0.02%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43               2      0.04%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45               2      0.04%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47               2      0.04%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54-55               1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::70-71               1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::78-79               1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5572                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1534207250                       # Total ticks spent queuing
system.physmem.totMemAccLat                4235351000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    720305000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10649.71                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29399.71                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          25.24                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          16.91                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       25.25                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       16.92                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        20.29                       # Average write queue length when enqueuing
system.physmem.readRowHits                     111019                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64498                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.06                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.80                       # Row buffer hit rate for writes
system.physmem.avgGap                      1517614.82                       # Average gap between requests
system.physmem.pageHitRate                      72.94                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  247892400                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  135258750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 560445600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                310566960                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            23860618080                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            47138982615                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           177839337750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             250093102155                       # Total energy per rank (pJ)
system.physmem_0.averagePower              684.594758                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   295545266000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     12198680000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     57571800000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  244014120                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  133142625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 563058600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                314817840                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            23860618080                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            46734210225                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           178194401250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             250044262740                       # Total energy per rank (pJ)
system.physmem_1.averagePower              684.461067                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   296138902500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     12198680000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     56977968750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               132578917                       # Number of BP lookups
system.cpu.branchPred.condPredicted          98507789                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           6555100                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             69037584                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                64855119                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             93.941756                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                10014942                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              17500                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        730634466                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   506582155                       # Number of instructions committed
system.cpu.committedOps                     548695378                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      13461155                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.442282                       # CPI: cycles per instruction
system.cpu.ipc                               0.693346                       # IPC: instructions per cycle
system.cpu.tickCycles                       695780172                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        34854294                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           1139812                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4071.074819                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           171281876                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1143908                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            149.733961                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4867376000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.074819                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst     0.993915                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993915                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          545                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3506                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         346818362                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        346818362                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst    114766084                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114766084                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst     53538710                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53538710                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst     168304794                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168304794                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst    168304794                       # number of overall hits
system.cpu.dcache.overall_hits::total       168304794                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst       854755                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        854755                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst       700596                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       700596                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.inst      1555351                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1555351                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst      1555351                       # number of overall misses
system.cpu.dcache.overall_misses::total       1555351                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst  13707430482                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  13707430482                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20521575250                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  20521575250                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst  34229005732                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  34229005732                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst  34229005732                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  34229005732                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst    115620839                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    115620839                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst    169860145                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    169860145                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst    169860145                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    169860145                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.007393                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007393                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012917                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012917                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst     0.009157                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009157                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst     0.009157                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009157                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16036.677740                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16036.677740                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29291.596369                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29291.596369                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22007.254782                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22007.254782                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22007.254782                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22007.254782                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1068525                       # number of writebacks
system.cpu.dcache.writebacks::total           1068525                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        66991                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        66991                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       344452                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       344452                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst       411443                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       411443                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst       411443                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       411443                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       787764                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       787764                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       356144                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356144                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst      1143908                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1143908                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst      1143908                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1143908                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  11252029015                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  11252029015                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10073374750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10073374750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  21325403765                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  21325403765                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  21325403765                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  21325403765                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.006813                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006813                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.006566                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006566                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.006734                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006734                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.006734                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006734                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14283.502439                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14283.502439                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28284.555545                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28284.555545                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18642.586436                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18642.586436                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18642.586436                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18642.586436                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             17690                       # number of replacements
system.cpu.icache.tags.tagsinuse          1190.635807                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           200942292                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             19563                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          10271.547922                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1190.635807                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.581365                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.581365                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1873                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          309                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1406                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.914551                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         401943273                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        401943273                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    200942292                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       200942292                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     200942292                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        200942292                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    200942292                       # number of overall hits
system.cpu.icache.overall_hits::total       200942292                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        19563                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         19563                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        19563                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          19563                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        19563                       # number of overall misses
system.cpu.icache.overall_misses::total         19563                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    469537995                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    469537995                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    469537995                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    469537995                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    469537995                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    469537995                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    200961855                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    200961855                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    200961855                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    200961855                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    200961855                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    200961855                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000097                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000097                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000097                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000097                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000097                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000097                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24001.328784                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 24001.328784                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24001.328784                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 24001.328784                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24001.328784                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 24001.328784                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19563                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        19563                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        19563                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        19563                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        19563                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        19563                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    429024005                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    429024005                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    429024005                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    429024005                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    429024005                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    429024005                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000097                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000097                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000097                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21930.379032                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21930.379032                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21930.379032                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21930.379032                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21930.379032                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21930.379032                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111403                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27648.458293                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1684717                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           142590                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            11.815113                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     163177408500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23523.224801                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  4125.233493                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.717872                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.125892                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.843764                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31187                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          323                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4940                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25856                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951752                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         18354956                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        18354956                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst       763767                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         763767                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1068525                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1068525                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst       255530                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       255530                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst      1019297                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1019297                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      1019297                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1019297                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        43306                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        43306                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst       100868                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       100868                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst       144174                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        144174                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst       144174                       # number of overall misses
system.cpu.l2cache.overall_misses::total       144174                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   3229271000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3229271000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7164307250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7164307250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  10393578250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10393578250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  10393578250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10393578250                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst       807073                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       807073                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1068525                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1068525                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst       356398                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356398                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1163471                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1163471                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1163471                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1163471                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.053658                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.053658                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.283021                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.283021                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.123917                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.123917                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.123917                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.123917                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74568.674087                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74568.674087                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71026.561942                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71026.561942                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72090.517361                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72090.517361                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72090.517361                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72090.517361                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        96561                       # number of writebacks
system.cpu.l2cache.writebacks::total            96561                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           17                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        43289                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        43289                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       100868                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       100868                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       144157                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       144157                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       144157                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       144157                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2680290500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2680290500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   5883442250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5883442250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8563732750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8563732750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8563732750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8563732750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.053637                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053637                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.283021                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283021                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.123903                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.123903                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.123903                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.123903                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61916.202730                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61916.202730                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58328.134294                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59405.597716                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59405.597716                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59405.597716                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         807073                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        807073                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1068525                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       356398                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       356398                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        39126                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3356341                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3395467                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1252032                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141595712                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          142847744                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      2231996                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5            2231996    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2231996                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2184523000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      30038495                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1744651235                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.membus.trans_dist::ReadReq               43289                       # Transaction distribution
system.membus.trans_dist::ReadResp              43289                       # Transaction distribution
system.membus.trans_dist::Writeback             96561                       # Transaction distribution
system.membus.trans_dist::ReadExReq            100868                       # Transaction distribution
system.membus.trans_dist::ReadExResp           100868                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       384875                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 384875                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15405952                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15405952                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            240718                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  240718    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              240718                       # Request fanout histogram
system.membus.reqLayer0.occupancy          1081999000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1366864750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)

---------- End Simulation Statistics   ----------