path: root/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.365348                       # Number of seconds simulated
sim_ticks                                365347511000                       # Number of ticks simulated
final_tick                               365347511000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 224796                       # Simulator instruction rate (inst/s)
host_op_rate                                   243484                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              162123009                       # Simulator tick rate (ticks/s)
host_mem_usage                                 256924                       # Number of bytes of host memory used
host_seconds                                  2253.52                       # Real time elapsed on the host
sim_insts                                   506582155                       # Number of instructions simulated
sim_ops                                     548695378                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst           9224896                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9224896                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       221312                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          221312                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6179008                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6179008                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst             144139                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                144139                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           96547                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                96547                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             25249648                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                25249648                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          605758                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             605758                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          16912687                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               16912687                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          16912687                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            25249648                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               42162335                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        144139                       # Number of read requests accepted
system.physmem.writeReqs                        96547                       # Number of write requests accepted
system.physmem.readBursts                      144139                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      96547                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9218048                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6848                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6177856                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9224896                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6179008                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      107                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9344                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8969                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8998                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8704                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9453                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9341                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8940                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8101                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8571                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8677                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8772                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9476                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9379                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9523                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8710                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9074                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6191                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6093                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6006                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5817                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6161                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6171                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6013                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5494                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5728                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5821                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5961                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6446                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6308                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6280                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5994                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6045                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    365347483000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  144139                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  96547                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    143660                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       351                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3022                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5536                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5697                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5682                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5682                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5626                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5628                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5584                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        64866                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      237.344433                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     157.101707                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     243.291878                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24488     37.75%     37.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18300     28.21%     65.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6859     10.57%     76.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7791     12.01%     88.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2064      3.18%     91.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1161      1.79%     93.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          764      1.18%     94.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          681      1.05%     95.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         2758      4.25%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          64866                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5569                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.862992                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      382.285392                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5565     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            3      0.05%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5569                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5569                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.333273                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.210704                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        3.188900                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5418     97.29%     97.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              79      1.42%     98.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              23      0.41%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              20      0.36%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35               9      0.16%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               7      0.13%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               5      0.09%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               5      0.09%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5569                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1570268250                       # Total ticks spent queuing
system.physmem.totMemAccLat                4270868250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    720160000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10902.22                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29652.22                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          25.23                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          16.91                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       25.25                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       16.91                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        19.86                       # Average write queue length when enqueuing
system.physmem.readRowHits                     110988                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64704                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.06                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  67.02                       # Row buffer hit rate for writes
system.physmem.avgGap                      1517942.39                       # Average gap between requests
system.physmem.pageHitRate                      73.03                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     256543365500                       # Time in different power states
system.physmem.memoryStateTime::REF       12199720000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       96603610750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 246584520                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 243719280                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 134545125                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 132981750                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                560422200                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                562972800                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               310625280                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               314778960                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0           23862652320                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1           23862652320                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           47112370740                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           46678345380                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          177881368500                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          178262092500                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            250108568685                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            250057542990                       # Total energy per rank (pJ)
system.physmem.averagePower::0             684.578732                       # Core power per rank (mW)
system.physmem.averagePower::1             684.439068                       # Core power per rank (mW)
system.cpu.branchPred.lookups               132580026                       # Number of BP lookups
system.cpu.branchPred.condPredicted          98506360                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           6554090                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             69003825                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                64853184                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             93.984912                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                10016062                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              17737                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        730695022                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   506582155                       # Number of instructions committed
system.cpu.committedOps                     548695378                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      13461717                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.442402                       # CPI: cycles per instruction
system.cpu.ipc                               0.693288                       # IPC: instructions per cycle
system.cpu.tickCycles                       695775254                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        34919768                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           1139848                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4071.076883                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           171283127                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1143944                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            149.730343                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4867376000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.076883                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst     0.993915                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993915                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          550                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3502                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         346820764                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        346820764                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst    114767369                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114767369                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst     53538676                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53538676                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst     168306045                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168306045                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst    168306045                       # number of overall hits
system.cpu.dcache.overall_hits::total       168306045                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst       854653                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        854653                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst       700630                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       700630                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.inst      1555283                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1555283                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst      1555283                       # number of overall misses
system.cpu.dcache.overall_misses::total       1555283                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst  13708895232                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  13708895232                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20586763000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  20586763000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst  34295658232                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  34295658232                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst  34295658232                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  34295658232                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst    115622022                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    115622022                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst    169861328                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    169861328                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst    169861328                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    169861328                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.007392                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007392                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012917                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012917                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst     0.009156                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009156                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst     0.009156                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009156                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16040.305518                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16040.305518                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29383.216534                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29383.216534                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22051.072526                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22051.072526                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22051.072526                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22051.072526                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1068569                       # number of writebacks
system.cpu.dcache.writebacks::total           1068569                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        66869                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        66869                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       344470                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       344470                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst       411339                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       411339                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst       411339                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       411339                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       787784                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       787784                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       356160                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356160                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst      1143944                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1143944                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst      1143944                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1143944                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  11256226015                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  11256226015                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10106063500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10106063500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  21362289515                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  21362289515                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  21362289515                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  21362289515                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.006813                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006813                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.006566                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006566                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.006735                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006735                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.006735                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006735                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14288.467416                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14288.467416                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28375.065982                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28375.065982                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18674.244119                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18674.244119                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18674.244119                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18674.244119                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             17642                       # number of replacements
system.cpu.icache.tags.tagsinuse          1190.521713                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           200940130                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             19514                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          10297.229169                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1190.521713                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.581309                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.581309                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           64                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          301                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1411                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         401938802                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        401938802                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    200940130                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       200940130                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     200940130                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        200940130                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    200940130                       # number of overall hits
system.cpu.icache.overall_hits::total       200940130                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        19514                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         19514                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        19514                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          19514                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        19514                       # number of overall misses
system.cpu.icache.overall_misses::total         19514                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    467407495                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    467407495                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    467407495                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    467407495                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    467407495                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    467407495                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    200959644                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    200959644                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    200959644                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    200959644                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    200959644                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    200959644                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000097                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000097                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000097                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000097                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000097                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000097                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23952.418520                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 23952.418520                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23952.418520                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 23952.418520                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23952.418520                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 23952.418520                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19514                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        19514                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        19514                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        19514                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        19514                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        19514                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    426999505                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    426999505                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    426999505                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    426999505                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    426999505                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    426999505                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000097                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000097                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000097                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21881.700574                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21881.700574                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21881.700574                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21881.700574                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21881.700574                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21881.700574                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111385                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27648.726753                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1684688                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           142574                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            11.816236                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     163201810500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23524.085448                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  4124.641306                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.717898                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.125874                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.843772                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31189                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          322                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4940                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25859                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951813                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         18355203                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        18355203                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst       763758                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         763758                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1068569                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1068569                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst       255544                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       255544                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst      1019302                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1019302                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      1019302                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1019302                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        43287                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        43287                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst       100869                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       100869                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst       144156                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        144156                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst       144156                       # number of overall misses
system.cpu.l2cache.overall_misses::total       144156                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   3231564500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3231564500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7196834000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7196834000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  10428398500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10428398500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  10428398500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10428398500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst       807045                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       807045                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1068569                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1068569                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst       356413                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356413                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1163458                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1163458                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1163458                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1163458                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.053636                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.053636                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.283012                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.283012                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.123903                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.123903                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.123903                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.123903                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74654.388153                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74654.388153                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71348.323072                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71348.323072                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72341.064541                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72341.064541                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72341.064541                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72341.064541                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        96547                       # number of writebacks
system.cpu.l2cache.writebacks::total            96547                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           17                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        43270                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        43270                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       100869                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       100869                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       144139                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       144139                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       144139                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       144139                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2682518500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2682518500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   5916082000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5916082000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8598600500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8598600500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8598600500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8598600500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.053615                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053615                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.283012                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283012                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.123888                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.123888                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.123888                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.123888                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61994.880980                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61994.880980                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58651.141580                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58651.141580                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59654.919904                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59654.919904                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59654.919904                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59654.919904                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         807045                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        807045                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1068569                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       356413                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       356413                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        39028                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3356457                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3395485                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1248896                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141600832                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          142849728                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      2232027                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5            2232027    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2232027                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2184582500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      29960995                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1744681985                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.membus.trans_dist::ReadReq               43270                       # Transaction distribution
system.membus.trans_dist::ReadResp              43270                       # Transaction distribution
system.membus.trans_dist::Writeback             96547                       # Transaction distribution
system.membus.trans_dist::ReadExReq            100869                       # Transaction distribution
system.membus.trans_dist::ReadExResp           100869                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       384825                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 384825                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15403904                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15403904                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            240686                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  240686    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              240686                       # Request fanout histogram
system.membus.reqLayer0.occupancy          1081853000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1366563500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)

---------- End Simulation Statistics   ----------