path: root/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.366030                       # Number of seconds simulated
sim_ticks                                366029674500                       # Number of ticks simulated
final_tick                               366029674500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 241467                       # Simulator instruction rate (inst/s)
host_op_rate                                   261540                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              174471263                       # Simulator tick rate (ticks/s)
host_mem_usage                                 317880                       # Number of bytes of host memory used
host_seconds                                  2097.94                       # Real time elapsed on the host
sim_insts                                   506582156                       # Number of instructions simulated
sim_ops                                     548695379                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            221440                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9008192                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9229632                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       221440                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          221440                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6182144                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6182144                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3460                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             140753                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                144213                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           96596                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                96596                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               604978                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             24610551                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                25215529                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          604978                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             604978                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          16889734                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               16889734                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          16889734                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              604978                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            24610551                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               42105264                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        144213                       # Number of read requests accepted
system.physmem.writeReqs                        96596                       # Number of write requests accepted
system.physmem.readBursts                      144213                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      96596                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9221696                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7936                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6180992                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9229632                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6182144                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      124                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9409                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9017                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8952                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8679                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9455                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9348                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8942                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8103                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8564                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8678                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8771                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9482                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9373                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9523                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8716                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9077                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6225                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6098                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6004                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5808                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6164                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6178                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6016                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5497                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5725                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5821                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5961                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6450                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6306                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6280                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5998                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6047                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    366029646000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  144213                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  96596                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    143718                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       350                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2919                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5530                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5692                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5661                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5676                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5675                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5679                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5663                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5657                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65352                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      235.682213                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     156.342104                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     241.346143                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24838     38.01%     38.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18259     27.94%     65.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6996     10.71%     76.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7952     12.17%     88.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2091      3.20%     92.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1098      1.68%     93.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          757      1.16%     94.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          602      0.92%     95.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         2759      4.22%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65352                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5574                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.850018                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      381.983730                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5570     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            3      0.05%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5574                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5574                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.326516                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.224346                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.427330                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            2648     47.51%     47.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            2778     49.84%     97.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              56      1.00%     98.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              28      0.50%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              12      0.22%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              10      0.18%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29               6      0.11%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31               9      0.16%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               4      0.07%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35               7      0.13%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               2      0.04%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41               4      0.07%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43               2      0.04%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45               1      0.02%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47               1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51               1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54-55               1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59               1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-65               1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::70-71               1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-81               1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5574                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1545997750                       # Total ticks spent queuing
system.physmem.totMemAccLat                4247666500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    720445000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10729.46                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29479.46                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          25.19                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          16.89                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       25.22                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       16.89                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        20.60                       # Average write queue length when enqueuing
system.physmem.readRowHits                     110923                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64387                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.98                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.66                       # Row buffer hit rate for writes
system.physmem.avgGap                      1519999.86                       # Average gap between requests
system.physmem.pageHitRate                      72.84                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  248708880                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  135704250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 560640600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                310761360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            23906897040                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            47751629445                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           177727049250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             250641390825                       # Total energy per rank (pJ)
system.physmem_0.averagePower              684.767505                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   295355626000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     12222340000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     58446120250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  245064960                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  133716000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 562816800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                314753040                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            23906897040                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            47056905180                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           178336456500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             250556609520                       # Total energy per rank (pJ)
system.physmem_1.averagePower              684.535877                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   296372694500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     12222340000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     57429294500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               132485545                       # Number of BP lookups
system.cpu.branchPred.condPredicted          98435425                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           6553959                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             68727443                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                64816198                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             94.309049                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                10006764                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              17617                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        732059349                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   506582156                       # Number of instructions committed
system.cpu.committedOps                     548695379                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      13911652                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.445095                       # CPI: cycles per instruction
system.cpu.ipc                               0.691996                       # IPC: instructions per cycle
system.cpu.tickCycles                       695000552                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        37058797                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           1139856                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4070.933719                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           171285318                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1143952                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            149.731211                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4900143250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4070.933719                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993880                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993880                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          552                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3500                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         346825504                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        346825504                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    114766819                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114766819                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     53538648                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53538648                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2769                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2769                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     168305467                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168305467                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    168308236                       # number of overall hits
system.cpu.dcache.overall_hits::total       168308236                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       854784                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        854784                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       700658                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       700658                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           16                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           16                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1555442                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1555442                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1555458                       # number of overall misses
system.cpu.dcache.overall_misses::total       1555458                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  14034932732                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14034932732                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  22036201250                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  22036201250                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  36071133982                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  36071133982                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  36071133982                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  36071133982                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    115621603                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    115621603                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2785                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2785                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    169860909                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    169860909                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    169863694                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    169863694                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007393                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007393                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012918                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012918                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005745                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.005745                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009157                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009157                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009157                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009157                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16419.274029                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16419.274029                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31450.723820                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31450.723820                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23190.279022                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23190.279022                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23190.040478                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23190.040478                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1068580                       # number of writebacks
system.cpu.dcache.writebacks::total           1068580                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        67006                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        67006                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344497                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       344497                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       411503                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       411503                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       411503                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       411503                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       787778                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       787778                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356161                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356161                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           13                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           13                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1143939                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1143939                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1143952                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1143952                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11938933765                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  11938933765                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10970217000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10970217000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1208500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1208500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22909150765                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  22909150765                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22910359265                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  22910359265                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006813                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006813                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006566                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006566                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004668                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004668                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006735                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006735                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006735                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006735                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15155.200786                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15155.200786                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30801.286497                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30801.286497                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 92961.538462                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92961.538462                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20026.549287                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20026.549287                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20027.378129                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20027.378129                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             17693                       # number of replacements
system.cpu.icache.tags.tagsinuse          1189.692945                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           200785966                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             19565                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          10262.507846                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1189.692945                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.580905                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.580905                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1410                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         401630627                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        401630627                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    200785966                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       200785966                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     200785966                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        200785966                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    200785966                       # number of overall hits
system.cpu.icache.overall_hits::total       200785966                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        19565                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         19565                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        19565                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          19565                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        19565                       # number of overall misses
system.cpu.icache.overall_misses::total         19565                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    492369746                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    492369746                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    492369746                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    492369746                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    492369746                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    492369746                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    200805531                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    200805531                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    200805531                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    200805531                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    200805531                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    200805531                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000097                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000097                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000097                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000097                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000097                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000097                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25165.844416                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 25165.844416                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25165.844416                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 25165.844416                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25165.844416                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25165.844416                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19565                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        19565                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        19565                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        19565                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        19565                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        19565                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    461635754                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    461635754                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    461635754                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    461635754                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    461635754                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    461635754                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000097                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000097                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000097                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23594.978482                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23594.978482                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23594.978482                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 23594.978482                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23594.978482                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23594.978482                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111459                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27647.084057                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1684517                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           142645                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            11.809156                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     163718172500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23519.494662                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   390.390983                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  3737.198412                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.717758                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011914                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.114050                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.843722                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31186                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          321                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4936                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25861                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951721                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         18355835                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        18355835                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        16103                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       747676                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         763779                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1068580                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1068580                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       255508                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       255508                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        16103                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1003184                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1019287                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        16103                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1003184                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1019287                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3462                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        39862                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        43324                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       100906                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       100906                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3462                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       140768                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        144230                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3462                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       140768                       # number of overall misses
system.cpu.l2cache.overall_misses::total       144230                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    272932750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3295008250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3567941000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7933719500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7933719500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    272932750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11228727750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11501660500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    272932750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11228727750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11501660500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        19565                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       787538                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       807103                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1068580                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1068580                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       356414                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356414                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        19565                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1143952                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1163517                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        19565                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1143952                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1163517                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.176949                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.050616                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.053678                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.283115                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.283115                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.176949                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.123054                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.123960                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.176949                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.123054                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.123960                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78836.727325                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82660.384577                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 82354.837965                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78624.853824                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78624.853824                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78836.727325                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79767.615864                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79745.271441                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78836.727325                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79767.615864                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79745.271441                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        96596                       # number of writebacks
system.cpu.l2cache.writebacks::total            96596                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           15                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           15                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3460                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        39847                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        43307                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100906                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       100906                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3460                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       140753                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       144213                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3460                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       140753                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       144213                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    229496250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2794594500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3024090750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6671817000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6671817000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    229496250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9466411500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9695907750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    229496250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9466411500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9695907750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.176846                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.050597                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053657                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283115                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283115                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.176846                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123041                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.123946                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.176846                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123041                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.123946                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66328.395954                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70133.121690                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69829.144249                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66119.130676                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66119.130676                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66328.395954                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67255.486562                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67233.243536                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66328.395954                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67255.486562                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67233.243536                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         807103                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        807103                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1068580                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       356414                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       356414                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        39130                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3356484                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3395614                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1252160                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141602048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          142854208                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      2232097                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            2232097    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2232097                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2184628500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      30040746                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1744732235                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.membus.trans_dist::ReadReq               43307                       # Transaction distribution
system.membus.trans_dist::ReadResp              43307                       # Transaction distribution
system.membus.trans_dist::Writeback             96596                       # Transaction distribution
system.membus.trans_dist::ReadExReq            100906                       # Transaction distribution
system.membus.trans_dist::ReadExResp           100906                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       385022                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 385022                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15411776                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15411776                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            240809                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  240809    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              240809                       # Request fanout histogram
system.membus.reqLayer0.occupancy           679106500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy          765494750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------