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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.363605 # Number of seconds simulated
sim_ticks 363605295500 # Number of ticks simulated
final_tick 363605295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 163495 # Simulator instruction rate (inst/s)
host_op_rate 177087 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 117350463 # Simulator tick rate (ticks/s)
host_mem_usage 312624 # Number of bytes of host memory used
host_seconds 3098.46 # Real time elapsed on the host
sim_insts 506582156 # Number of instructions simulated
sim_ops 548695379 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 219264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9004480 # Number of bytes read from this memory
system.physmem.bytes_read::total 9223744 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 219264 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 219264 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6189056 # Number of bytes written to this memory
system.physmem.bytes_written::total 6189056 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3426 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 140695 # Number of read requests responded to by this memory
system.physmem.num_reads::total 144121 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 96704 # Number of write requests responded to by this memory
system.physmem.num_writes::total 96704 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 603028 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 24764436 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 25367463 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 603028 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 603028 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 17021358 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 17021358 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 17021358 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 603028 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 24764436 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42388822 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 144121 # Number of read requests accepted
system.physmem.writeReqs 96704 # Number of write requests accepted
system.physmem.readBursts 144121 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 96704 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 9217792 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue
system.physmem.bytesWritten 6187328 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 9223744 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6189056 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 9327 # Per bank write bursts
system.physmem.perBankRdBursts::1 8969 # Per bank write bursts
system.physmem.perBankRdBursts::2 9002 # Per bank write bursts
system.physmem.perBankRdBursts::3 8675 # Per bank write bursts
system.physmem.perBankRdBursts::4 9455 # Per bank write bursts
system.physmem.perBankRdBursts::5 9352 # Per bank write bursts
system.physmem.perBankRdBursts::6 8946 # Per bank write bursts
system.physmem.perBankRdBursts::7 8102 # Per bank write bursts
system.physmem.perBankRdBursts::8 8582 # Per bank write bursts
system.physmem.perBankRdBursts::9 8671 # Per bank write bursts
system.physmem.perBankRdBursts::10 8765 # Per bank write bursts
system.physmem.perBankRdBursts::11 9475 # Per bank write bursts
system.physmem.perBankRdBursts::12 9349 # Per bank write bursts
system.physmem.perBankRdBursts::13 9515 # Per bank write bursts
system.physmem.perBankRdBursts::14 8723 # Per bank write bursts
system.physmem.perBankRdBursts::15 9120 # Per bank write bursts
system.physmem.perBankWrBursts::0 6189 # Per bank write bursts
system.physmem.perBankWrBursts::1 6094 # Per bank write bursts
system.physmem.perBankWrBursts::2 6010 # Per bank write bursts
system.physmem.perBankWrBursts::3 5821 # Per bank write bursts
system.physmem.perBankWrBursts::4 6183 # Per bank write bursts
system.physmem.perBankWrBursts::5 6186 # Per bank write bursts
system.physmem.perBankWrBursts::6 6015 # Per bank write bursts
system.physmem.perBankWrBursts::7 5498 # Per bank write bursts
system.physmem.perBankWrBursts::8 5738 # Per bank write bursts
system.physmem.perBankWrBursts::9 5829 # Per bank write bursts
system.physmem.perBankWrBursts::10 5965 # Per bank write bursts
system.physmem.perBankWrBursts::11 6463 # Per bank write bursts
system.physmem.perBankWrBursts::12 6313 # Per bank write bursts
system.physmem.perBankWrBursts::13 6285 # Per bank write bursts
system.physmem.perBankWrBursts::14 6005 # Per bank write bursts
system.physmem.perBankWrBursts::15 6083 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 363605269500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 144121 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 96704 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 143663 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 343 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2949 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5548 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5659 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5668 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5673 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5682 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5670 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5674 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5686 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5716 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5669 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5677 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5614 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 65251 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 236.074482 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 156.620272 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 241.651300 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 24697 37.85% 37.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18374 28.16% 66.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6917 10.60% 76.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7938 12.17% 88.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2038 3.12% 91.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1147 1.76% 93.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 769 1.18% 94.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 621 0.95% 95.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 2750 4.21% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 65251 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5585 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 25.786571 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 381.841879 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 5581 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5585 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5585 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.310116 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.217866 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 2.213646 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 2534 45.37% 45.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 92 1.65% 47.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 2660 47.63% 94.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 156 2.79% 97.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 36 0.64% 98.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 18 0.32% 98.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 16 0.29% 98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 9 0.16% 98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 7 0.13% 98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 10 0.18% 99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 4 0.07% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 4 0.07% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 4 0.07% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 6 0.11% 99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 2 0.04% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 4 0.07% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32 3 0.05% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33 4 0.07% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35 2 0.04% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37 2 0.04% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39 1 0.02% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40 1 0.02% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43 1 0.02% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44 1 0.02% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47 1 0.02% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50 2 0.04% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52 1 0.02% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::53 1 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::55 1 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::61 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::62 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5585 # Writes before turning the bus around for reads
system.physmem.totQLat 1541292750 # Total ticks spent queuing
system.physmem.totMemAccLat 4241817750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 720140000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10701.34 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29451.34 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 25.35 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 25.37 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.33 # Data bus utilization in percentage
system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
system.physmem.avgWrQLen 19.51 # Average write queue length when enqueuing
system.physmem.readRowHits 110876 # Number of row buffer hits during reads
system.physmem.writeRowHits 64571 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 66.77 # Row buffer hit rate for writes
system.physmem.avgGap 1509831.91 # Average gap between requests
system.physmem.pageHitRate 72.88 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 248028480 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 135333000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 560164800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 310884480 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 47382783300 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 176597692500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 248983621440 # Total energy per rank (pJ)
system.physmem_0.averagePower 684.768610 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 293478926000 # Time in different power states
system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 57982170250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 245080080 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 133724250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 563004000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 315375120 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 46983341835 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 176948079750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 248937339915 # Total energy per rank (pJ)
system.physmem_1.averagePower 684.641324 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 294063578500 # Time in different power states
system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 57397836750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 131896308 # Number of BP lookups
system.cpu.branchPred.condPredicted 98031712 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 6139352 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 68410049 # Number of BTB lookups
system.cpu.branchPred.BTBHits 64397752 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 94.134930 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 9981293 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 18014 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 727210591 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506582156 # Number of instructions committed
system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed
system.cpu.discardedOps 13199856 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.435524 # CPI: cycles per instruction
system.cpu.ipc 0.696610 # IPC: instructions per cycle
system.cpu.tickCycles 690727435 # Number of cycles that the object actually ticked
system.cpu.idleCycles 36483156 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1139971 # number of replacements
system.cpu.dcache.tags.tagsinuse 4070.789837 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 171168979 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1144067 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 149.614471 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789837 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 346593001 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 346593001 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 114650515 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114650515 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53538628 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 53538628 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 2754 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 2754 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168189143 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168189143 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168191897 # number of overall hits
system.cpu.dcache.overall_hits::total 168191897 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 854793 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 854793 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 700678 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 700678 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 17 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 17 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 1555471 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1555471 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1555488 # number of overall misses
system.cpu.dcache.overall_misses::total 1555488 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024452000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 14024452000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21892214000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 21892214000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 35916666000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35916666000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35916666000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35916666000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 115505308 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 115505308 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2771 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2771 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 169744614 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 169744614 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 169747385 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 169747385 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.006135 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.006135 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009164 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009164 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009164 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009164 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.840019 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.840019 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31244.329064 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31244.329064 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23090.540422 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23090.540422 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.288064 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23090.288064 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1068574 # number of writebacks
system.cpu.dcache.writebacks::total 1068574 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66907 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 66907 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344511 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 344511 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 411418 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 411418 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 411418 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 411418 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787886 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 787886 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356167 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 356167 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 14 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 14 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1144053 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1144053 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1144067 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1144067 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337562000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337562000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11120015500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11120015500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1028000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1028000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23457577500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23457577500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23458605500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23458605500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005052 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005052 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.069967 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.069967 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31221.352624 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31221.352624 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73428.571429 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73428.571429 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20503.925517 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20503.925517 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20504.573159 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20504.573159 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 17719 # number of replacements
system.cpu.icache.tags.tagsinuse 1188.326281 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 199317838 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 19591 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 10173.949160 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1188.326281 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.580237 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.580237 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1407 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 398694449 # Number of tag accesses
system.cpu.icache.tags.data_accesses 398694449 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 199317838 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 199317838 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 199317838 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 199317838 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 199317838 # number of overall hits
system.cpu.icache.overall_hits::total 199317838 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 19591 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 19591 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 19591 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 19591 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 19591 # number of overall misses
system.cpu.icache.overall_misses::total 19591 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 490899000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 490899000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 490899000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 490899000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 490899000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 490899000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 199337429 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 199337429 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 199337429 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 199337429 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 199337429 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 199337429 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25057.373284 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 25057.373284 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25057.373284 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 25057.373284 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25057.373284 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25057.373284 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19591 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 19591 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 19591 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 19591 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 19591 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 19591 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 471308000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 471308000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 471308000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 471308000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 471308000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 471308000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24057.373284 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24057.373284 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24057.373284 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 24057.373284 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24057.373284 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 24057.373284 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 111367 # number of replacements
system.cpu.l2cache.tags.tagsinuse 27634.082837 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1767150 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 142553 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 12.396442 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 163253470000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23457.963317 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.755870 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 3786.363650 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.715880 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011894 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.115551 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.843325 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31186 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4935 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25860 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 19030386 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 19030386 # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks 1068574 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1068574 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 255588 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 255588 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16163 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 16163 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 747770 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 747770 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 16163 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1003358 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1019521 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 16163 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1003358 # number of overall hits
system.cpu.l2cache.overall_hits::total 1019521 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 100829 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 100829 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3428 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3428 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39880 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 39880 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3428 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 140709 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 144137 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3428 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 140709 # number of overall misses
system.cpu.l2cache.overall_misses::total 144137 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7904552500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7904552500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 272166000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 272166000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3286207500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3286207500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 272166000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11190760000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 11462926000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 272166000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11190760000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 11462926000 # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks 1068574 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1068574 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356417 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 356417 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 19591 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 19591 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 787650 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 787650 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 19591 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1144067 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1163658 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 19591 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1144067 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1163658 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282896 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.282896 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.174978 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.174978 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050632 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050632 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.174978 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.122990 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.123865 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.174978 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.122990 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.123865 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78395.625267 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78395.625267 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79394.982497 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79394.982497 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82402.394684 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82402.394684 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79394.982497 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79531.231122 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79527.990731 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79394.982497 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79531.231122 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79527.990731 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 96704 # number of writebacks
system.cpu.l2cache.writebacks::total 96704 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1193 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 1193 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100829 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 100829 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3426 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3426 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39866 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39866 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3426 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 140695 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 144121 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3426 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 140695 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 144121 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6896262500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6896262500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 237598000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 237598000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2886048500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2886048500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 237598000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9782311000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 10019909000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 237598000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9782311000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 10019909000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282896 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282896 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.174876 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050614 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050614 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123852 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123852 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68395.625267 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68395.625267 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69351.430239 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69351.430239 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72393.731501 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72393.731501 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 807241 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1165278 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 98858 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 19591 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 787650 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56664 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423421 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3480085 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253824 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141609024 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 142862848 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 111367 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2432715 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.045779 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.209005 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2321348 95.42% 95.42% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 111367 4.58% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2432715 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2229248000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 29387997 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1716107486 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.trans_dist::ReadResp 43292 # Transaction distribution
system.membus.trans_dist::Writeback 96704 # Transaction distribution
system.membus.trans_dist::CleanEvict 13244 # Transaction distribution
system.membus.trans_dist::ReadExReq 100829 # Transaction distribution
system.membus.trans_dist::ReadExResp 100829 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 43292 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398190 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 398190 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15412800 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 15412800 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 254069 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 254069 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 254069 # Request fanout histogram
system.membus.reqLayer0.occupancy 683631500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 765040250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
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