path: root/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.366340                       # Number of seconds simulated
sim_ticks                                366339500500                       # Number of ticks simulated
final_tick                               366339500500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 174606                       # Simulator instruction rate (inst/s)
host_op_rate                                   189122                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              126268215                       # Simulator tick rate (ticks/s)
host_mem_usage                                 309684                       # Number of bytes of host memory used
host_seconds                                  2901.28                       # Real time elapsed on the host
sim_insts                                   506582156                       # Number of instructions simulated
sim_ops                                     548695379                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            222208                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9004736                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9226944                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       222208                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          222208                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6180224                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6180224                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3472                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             140699                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                144171                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           96566                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                96566                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               606563                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             24580303                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                25186866                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          606563                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             606563                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          16870209                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               16870209                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          16870209                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              606563                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            24580303                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               42057075                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        144171                       # Number of read requests accepted
system.physmem.writeReqs                        96566                       # Number of write requests accepted
system.physmem.readBursts                      144171                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      96566                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9220288                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6656                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6179072                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9226944                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6180224                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      104                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9343                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8971                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8989                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8699                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9456                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9348                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8947                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8105                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8575                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8682                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8775                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9479                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9376                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9525                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8707                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9090                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6188                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6094                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6005                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5814                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6162                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6175                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6015                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5497                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5730                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5822                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5962                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6449                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6307                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6278                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5993                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6057                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    366339471500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  144171                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  96566                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    143694                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       352                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2905                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5651                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5669                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5665                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5690                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5705                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5667                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5666                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5663                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65255                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      235.982530                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     156.409511                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     241.771416                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24814     38.03%     38.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18186     27.87%     65.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6968     10.68%     76.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7930     12.15%     88.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2060      3.16%     91.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1157      1.77%     93.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          782      1.20%     94.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          601      0.92%     95.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         2757      4.22%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65255                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5574                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.846071                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      382.003663                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5571     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            2      0.04%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5574                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5574                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.321134                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.221070                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.354740                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            2655     47.63%     47.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            2759     49.50%     97.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              73      1.31%     98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              16      0.29%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              14      0.25%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              15      0.27%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29               8      0.14%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31               5      0.09%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               9      0.16%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35               6      0.11%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               1      0.02%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39               2      0.04%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41               1      0.02%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43               1      0.02%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45               2      0.04%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47               1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49               1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54-55               1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59               1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-65               1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::66-67               1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::70-71               1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5574                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1547962750                       # Total ticks spent queuing
system.physmem.totMemAccLat                4249219000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    720335000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10744.74                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29494.74                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          25.17                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          16.87                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       25.19                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       16.87                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        20.02                       # Average write queue length when enqueuing
system.physmem.readRowHits                     110904                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64452                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.98                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.74                       # Row buffer hit rate for writes
system.physmem.avgGap                      1521741.45                       # Average gap between requests
system.physmem.pageHitRate                      72.87                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  247983120                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  135308250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 560305200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                310528080                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            23927239440                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            47721013605                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           177940783500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             250843161195                       # Total energy per rank (pJ)
system.physmem_0.averagePower              684.736086                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   295712636000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     12232740000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     58390260500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  245095200                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  133732500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 563066400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                314791920                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            23927239440                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            47027452140                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           178549170750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             250760548350                       # Total energy per rank (pJ)
system.physmem_1.averagePower              684.510574                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   296727601000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     12232740000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     57375209000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               132583064                       # Number of BP lookups
system.cpu.branchPred.condPredicted          98508784                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           6555218                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             69071756                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                64847878                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             93.884797                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                10016520                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              18156                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        732679001                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   506582156                       # Number of instructions committed
system.cpu.committedOps                     548695379                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      13461102                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.446318                       # CPI: cycles per instruction
system.cpu.ipc                               0.691411                       # IPC: instructions per cycle
system.cpu.tickCycles                       695769824                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        36909177                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           1139845                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4070.953673                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           171282385                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1143941                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            149.730087                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4900143250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4070.953673                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993885                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993885                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          544                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3507                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         346819443                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        346819443                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    114763887                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114763887                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     53538651                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53538651                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2765                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2765                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     168302538                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168302538                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    168305303                       # number of overall hits
system.cpu.dcache.overall_hits::total       168305303                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       854696                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        854696                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       700655                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       700655                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           15                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           15                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1555351                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1555351                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1555366                       # number of overall misses
system.cpu.dcache.overall_misses::total       1555366                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  14025171732                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14025171732                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  22048092000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  22048092000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  36073263732                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  36073263732                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  36073263732                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  36073263732                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    115618583                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    115618583                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2780                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2780                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    169857889                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    169857889                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    169860669                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    169860669                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007392                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007392                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012918                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012918                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005396                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.005396                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009157                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009157                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009157                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009157                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16409.544133                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16409.544133                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31467.829388                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31467.829388                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23193.005136                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23193.005136                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23192.781462                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23192.781462                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1068547                       # number of writebacks
system.cpu.dcache.writebacks::total           1068547                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66929                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        66929                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344493                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       344493                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       411422                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       411422                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       411422                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       411422                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       787767                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       787767                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356162                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356162                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1143929                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1143929                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1143941                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1143941                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11930909015                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  11930909015                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10976099750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10976099750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       986500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       986500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22907008765                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  22907008765                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22907995265                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  22907995265                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006813                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006813                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006566                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006566                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004317                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004317                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006735                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006735                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006735                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006735                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15145.225701                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15145.225701                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30817.717078                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30817.717078                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 82208.333333                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 82208.333333                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20024.851861                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20024.851861                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.504169                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.504169                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             17672                       # number of replacements
system.cpu.icache.tags.tagsinuse          1190.163457                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           200929857                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             19544                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          10280.897309                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1190.163457                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.581135                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.581135                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           62                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          306                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1407                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         401918346                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        401918346                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    200929857                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       200929857                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     200929857                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        200929857                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    200929857                       # number of overall hits
system.cpu.icache.overall_hits::total       200929857                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        19544                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         19544                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        19544                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          19544                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        19544                       # number of overall misses
system.cpu.icache.overall_misses::total         19544                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    494847996                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    494847996                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    494847996                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    494847996                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    494847996                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    494847996                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    200949401                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    200949401                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    200949401                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    200949401                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    200949401                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    200949401                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000097                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000097                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000097                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000097                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000097                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000097                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25319.688702                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 25319.688702                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25319.688702                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 25319.688702                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25319.688702                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25319.688702                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19544                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        19544                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        19544                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        19544                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        19544                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        19544                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    464144004                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    464144004                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    464144004                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    464144004                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    464144004                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    464144004                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000097                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000097                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000097                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23748.669873                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23748.669873                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23748.669873                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 23748.669873                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23748.669873                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23748.669873                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111417                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27648.763503                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1684506                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           142603                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            11.812557                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     163802727000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23521.944211                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   390.271354                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  3736.547938                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.717833                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011910                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.114030                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.843773                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31186                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          319                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4943                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25856                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951721                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         18355274                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        18355274                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        16070                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       747693                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         763763                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1068547                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1068547                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       255534                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       255534                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        16070                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1003227                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1019297                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        16070                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1003227                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1019297                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3474                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        39833                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        43307                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       100881                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       100881                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3474                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       140714                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        144188                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3474                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       140714                       # number of overall misses
system.cpu.l2cache.overall_misses::total       144188                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    275801500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3286544500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3562346000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7939327250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7939327250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    275801500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11225871750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11501673250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    275801500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11225871750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11501673250                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        19544                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       787526                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       807070                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1068547                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1068547                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       356415                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356415                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        19544                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1143941                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1163485                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        19544                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1143941                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1163485                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.177753                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.050580                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.053660                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.283044                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.283044                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.177753                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.123008                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.123928                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.177753                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.123008                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.123928                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79390.184226                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82508.083750                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 82257.972152                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78699.926151                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78699.926151                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79390.184226                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79777.930767                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79768.588579                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79390.184226                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79777.930767                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79768.588579                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        96566                       # number of writebacks
system.cpu.l2cache.writebacks::total            96566                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           15                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           15                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3472                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        39818                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        43290                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100881                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       100881                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3472                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       140699                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       144171                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3472                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       140699                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       144171                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    232222500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2786510500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3018733000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6677694250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6677694250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    232222500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9464204750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9696427250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    232222500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9464204750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9696427250                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.177650                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.050561                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053638                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283044                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283044                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.177650                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122995                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.123913                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.177650                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122995                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.123913                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66884.360599                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69981.176855                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69732.802033                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66193.775339                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66193.775339                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66884.360599                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67265.614894                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67256.433333                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66884.360599                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67265.614894                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67256.433333                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         807070                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        807070                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1068547                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       356415                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       356415                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        39088                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3356429                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3395517                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1250816                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141599232                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          142850048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      2232032                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            2232032    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2232032                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2184563000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      30009996                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1744692235                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.membus.trans_dist::ReadReq               43290                       # Transaction distribution
system.membus.trans_dist::ReadResp              43290                       # Transaction distribution
system.membus.trans_dist::Writeback             96566                       # Transaction distribution
system.membus.trans_dist::ReadExReq            100881                       # Transaction distribution
system.membus.trans_dist::ReadExResp           100881                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       384908                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 384908                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15407168                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15407168                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            240737                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  240737    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              240737                       # Request fanout histogram
system.membus.reqLayer0.occupancy           679133000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy          765318250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------