path: root/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.366439                       # Number of seconds simulated
sim_ticks                                366439129500                       # Number of ticks simulated
final_tick                               366439129500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 188596                       # Simulator instruction rate (inst/s)
host_op_rate                                   204275                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              136422977                       # Simulator tick rate (ticks/s)
host_mem_usage                                 271112                       # Number of bytes of host memory used
host_seconds                                  2686.05                       # Real time elapsed on the host
sim_insts                                   506579366                       # Number of instructions simulated
sim_ops                                     548692589                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            179840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9028544                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9208384                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       179840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          179840                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6219648                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6219648                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2810                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             141071                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                143881                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97182                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97182                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               490777                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             24638591                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                25129369                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          490777                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             490777                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          16973209                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               16973209                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          16973209                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              490777                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            24638591                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               42102578                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        143881                       # Number of read requests accepted
system.physmem.writeReqs                        97182                       # Number of write requests accepted
system.physmem.readBursts                      143881                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97182                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9201344                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7040                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6217600                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9208384                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6219648                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      110                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9364                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8912                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8949                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8655                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9392                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9355                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8959                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8100                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8596                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8629                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8739                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9451                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9334                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9512                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8707                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9117                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6231                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6102                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6028                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5879                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6243                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6239                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6050                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5507                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5786                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5859                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5978                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6493                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6351                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6319                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5995                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6090                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    366439104000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  143881                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97182                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    143447                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       307                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2945                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5546                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5708                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5717                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5721                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5718                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5715                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5728                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5691                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5629                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5618                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65604                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      235.015914                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     156.088937                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     241.071665                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24900     37.96%     37.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18453     28.13%     66.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7121     10.85%     76.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7867     11.99%     88.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1977      3.01%     91.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1093      1.67%     93.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          809      1.23%     94.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          630      0.96%     95.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         2754      4.20%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65604                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5611                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.620745                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      380.610137                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5609     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5611                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5611                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.314204                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.219748                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.335766                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            2654     47.30%     47.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            2805     49.99%     97.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              62      1.10%     98.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              24      0.43%     98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              17      0.30%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              10      0.18%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29              10      0.18%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31              10      0.18%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               2      0.04%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35               4      0.07%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               2      0.04%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39               1      0.02%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41               2      0.04%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45               1      0.02%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47               1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49               1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51               1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53               2      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::62-63               1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::98-99               1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5611                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1554447250                       # Total ticks spent queuing
system.physmem.totMemAccLat                4250153500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    718855000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10811.97                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29561.97                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          25.11                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          16.97                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       25.13                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       16.97                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        19.60                       # Average write queue length when enqueuing
system.physmem.readRowHits                     110522                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64789                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.87                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.67                       # Row buffer hit rate for writes
system.physmem.avgGap                      1520096.84                       # Average gap between requests
system.physmem.pageHitRate                      72.76                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  249842880                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  136323000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 559080600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                312783120                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            23933850720                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            47987220420                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           177768013500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             250947114240                       # Total energy per rank (pJ)
system.physmem_0.averagePower              684.830589                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   295423376000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     12236120000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     58777294250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  246017520                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  134235750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 562114800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                316645200                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            23933850720                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            47395195335                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           178287321750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             250875381075                       # Total energy per rank (pJ)
system.physmem_1.averagePower              684.634868                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   296291389000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     12236120000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     57909758500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups               132103761                       # Number of BP lookups
system.cpu.branchPred.condPredicted          98193255                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           5910050                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             68601566                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                60590451                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             88.322256                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                10017120                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              18743                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         3891572                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            3883027                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             8545                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        54138                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        732878259                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   506579366                       # Number of instructions committed
system.cpu.committedOps                     548692589                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      12939743                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.446720                       # CPI: cycles per instruction
system.cpu.ipc                               0.691219                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu               375609862     68.46%     68.46% # Class of committed instruction
system.cpu.op_class_0::IntMult                 339219      0.06%     68.52% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                3      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::MemRead              115883283     21.12%     89.64% # Class of committed instruction
system.cpu.op_class_0::MemWrite              56860222     10.36%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                548692589                       # Class of committed instruction
system.cpu.tickCycles                       694071941                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        38806318                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           1141337                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4070.313641                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           171083825                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1145433                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            149.361704                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        5033914500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4070.313641                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993729                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993729                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          549                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3501                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         346338115                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        346338115                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    114566020                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114566020                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     53537929                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53537929                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2794                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2794                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     168103949                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168103949                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    168106743                       # number of overall hits
system.cpu.dcache.overall_hits::total       168106743                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       811381                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        811381                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       701120                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       701120                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           15                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           15                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1512501                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1512501                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1512516                       # number of overall misses
system.cpu.dcache.overall_misses::total       1512516                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  13462011000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  13462011000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  21943272000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  21943272000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  35405283000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  35405283000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  35405283000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  35405283000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    115377401                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    115377401                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2809                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2809                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    169616450                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    169616450                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    169619259                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    169619259                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007032                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007032                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012926                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012926                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005340                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.005340                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.008917                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.008917                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.008917                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.008917                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16591.479219                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16591.479219                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31297.455500                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31297.455500                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23408.436094                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23408.436094                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23408.203946                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23408.203946                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      1069267                       # number of writebacks
system.cpu.dcache.writebacks::total           1069267                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22348                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        22348                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344732                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       344732                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       367080                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       367080                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       367080                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       367080                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       789033                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       789033                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356388                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356388                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1145421                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1145421                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1145433                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1145433                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12369658000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12369658000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11145800500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11145800500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1093500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1093500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23515458500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23515458500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23516552000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  23516552000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006839                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006839                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006571                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006571                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004272                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004272                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006753                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006753                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006753                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006753                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15676.984359                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15676.984359                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31274.342851                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31274.342851                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        91125                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        91125                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.969767                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.969767                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20530.709347                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20530.709347                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements             18175                       # number of replacements
system.cpu.icache.tags.tagsinuse          1187.153068                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           199148908                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             20047                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           9934.100264                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1187.153068                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.579665                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.579665                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          311                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1400                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         398357957                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        398357957                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    199148908                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       199148908                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     199148908                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        199148908                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    199148908                       # number of overall hits
system.cpu.icache.overall_hits::total       199148908                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        20047                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         20047                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        20047                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          20047                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        20047                       # number of overall misses
system.cpu.icache.overall_misses::total         20047                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    455856500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    455856500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    455856500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    455856500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    455856500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    455856500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    199168955                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    199168955                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    199168955                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    199168955                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    199168955                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    199168955                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000101                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000101                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000101                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000101                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000101                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000101                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.387440                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22739.387440                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.387440                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22739.387440                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.387440                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22739.387440                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks        18175                       # number of writebacks
system.cpu.icache.writebacks::total             18175                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        20047                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        20047                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        20047                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        20047                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        20047                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        20047                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    435809500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    435809500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    435809500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    435809500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    435809500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    435809500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000101                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000101                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000101                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.387440                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.387440                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.387440                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.387440                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.387440                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.387440                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements           112318                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27616.037174                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1771878                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           143528                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.345173                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     165163715500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23489.264935                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   308.326790                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  3818.445449                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.716835                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009409                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.116530                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.842775                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31210                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          318                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4934                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25858                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.952454                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         19060134                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        19060134                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks      1069267                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      1069267                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        17938                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        17938                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       255711                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       255711                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        17236                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        17236                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       748638                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       748638                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        17236                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1004349                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1021585                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        17236                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1004349                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1021585                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       100927                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       100927                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2811                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         2811                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        40157                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        40157                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2811                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141084                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        143895                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2811                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141084                       # number of overall misses
system.cpu.l2cache.overall_misses::total       143895                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7928727500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7928727500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    224093000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    224093000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3306674000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   3306674000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    224093000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11235401500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11459494500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    224093000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11235401500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11459494500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      1069267                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      1069267                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        17938                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        17938                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       356638                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356638                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        20047                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        20047                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       788795                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       788795                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        20047                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1145433                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1165480                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        20047                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1145433                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1165480                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282996                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.282996                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.140220                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.140220                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.050909                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.050909                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.140220                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.123171                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.123464                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.140220                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.123171                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.123464                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78559.032766                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78559.032766                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79720.028460                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79720.028460                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82343.651169                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82343.651169                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79720.028460                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79636.255706                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79637.892213                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79720.028460                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79636.255706                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79637.892213                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        97182                       # number of writebacks
system.cpu.l2cache.writebacks::total            97182                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           13                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           13                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           13                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           13                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100927                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       100927                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2810                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2810                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        40144                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        40144                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2810                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141071                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       143881                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2810                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141071                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       143881                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6919457500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6919457500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    195753000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    195753000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2904162000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2904162000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    195753000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9823619500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  10019372500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    195753000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9823619500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  10019372500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282996                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282996                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.140171                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.140171                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050893                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050893                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.140171                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123160                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.123452                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.140171                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123160                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.123452                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68559.032766                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68559.032766                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69662.989324                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69662.989324                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72343.612993                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72343.612993                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69662.989324                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.995350                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69636.522543                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69662.989324                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.995350                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69636.522543                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      2324992                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159582                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4996                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2610                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2607                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp        808842                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      1166449                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        18175                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        87206                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       356638                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       356638                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        20047                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       788795                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58269                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3432203                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3490472                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2446208                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141740800                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          144187008                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      112318                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               6219648                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      1277798                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.006010                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.077318                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            1270122     99.40%     99.40% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               7673      0.60%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  3      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1277798                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2249938000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      30093953                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1718157484                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.membus.pwrStateResidencyTicks::UNDEFINED 366439129500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp              42954                       # Transaction distribution
system.membus.trans_dist::WritebackDirty        97182                       # Transaction distribution
system.membus.trans_dist::CleanEvict            12526                       # Transaction distribution
system.membus.trans_dist::ReadExReq            100927                       # Transaction distribution
system.membus.trans_dist::ReadExResp           100927                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         42954                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397470                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 397470                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15428032                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15428032                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            253589                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  253589    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              253589                       # Request fanout histogram
system.membus.reqLayer0.occupancy           685523500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy          763755750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------