path: root/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
final_tick                               377848323500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
host_inst_rate                                 209721                       # Simulator instruction rate (inst/s)
host_mem_usage                                 298084                       # Number of bytes of host memory used
host_op_rate                                   236376                       # Simulator op (including micro ops) rate (op/s)
host_seconds                                  2415.51                       # Real time elapsed on the host
host_tick_rate                              156426000                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                   506582155                       # Number of instructions simulated
sim_ops                                     570968717                       # Number of ops (including micro ops) simulated
sim_seconds                                  0.377848                       # Number of seconds simulated
sim_ticks                                377848323500                       # Number of ticks simulated
system.clk_domain.clock                          1000                       # Clock period in ticks
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             88.099044                       # BTB Hit Percentage
system.cpu.branchPred.BTBHits                66115419                       # Number of BTB hits
system.cpu.branchPred.BTBLookups             75046693                       # Number of BTB lookups
system.cpu.branchPred.RASInCorrect              20332                       # Number of incorrect RAS predictions.
system.cpu.branchPred.condIncorrect           6724593                       # Number of conditional branches incorrect
system.cpu.branchPred.condPredicted         104577278                       # Number of conditional branches predicted
system.cpu.branchPred.lookups               137186083                       # Number of BP lookups
system.cpu.branchPred.usedRAS                 8950727                       # Number of times the RAS was used to get a target.
system.cpu.committedInsts                   506582155                       # Number of instructions committed
system.cpu.committedOps                     570968717                       # Number of ops (including micro ops) committed
system.cpu.cpi                               1.491755                       # CPI: cycles per instruction
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits::cpu.inst      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses::cpu.inst    123498792                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    123498792                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16388.035885                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16388.035885                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.902943                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.902943                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits::cpu.inst    122622654                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       122622654                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency::cpu.inst  14358180984                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14358180984                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.007094                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007094                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::cpu.inst       876138                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        876138                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        88069                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        88069                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  11252760763                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  11252760763                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.006381                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006381                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       788069                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       788069                       # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses::cpu.inst      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::cpu.inst      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses::cpu.inst     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29400.581233                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29400.581233                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28261.554772                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28261.554772                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits::cpu.inst     53538382                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53538382                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20607573000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  20607573000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.012923                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012923                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::cpu.inst       700924                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       700924                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       344621                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       344621                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10069676750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10069676750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.006569                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006569                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       356303                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356303                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses::cpu.inst    177738098                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    177738098                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22171.451715                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22171.451715                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18632.435531                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18632.435531                       # average overall mshr miss latency
system.cpu.dcache.demand_hits::cpu.inst     176161036                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        176161036                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency::cpu.inst  34965753984                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  34965753984                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate::cpu.inst     0.008873                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.008873                       # miss rate for demand accesses
system.cpu.dcache.demand_misses::cpu.inst      1577062                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1577062                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits::cpu.inst       432690                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       432690                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  21322437513                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  21322437513                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.006439                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006439                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses::cpu.inst      1144372                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1144372                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses::cpu.inst    177738098                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    177738098                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22171.451715                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22171.451715                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18632.435531                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18632.435531                       # average overall mshr miss latency
system.cpu.dcache.overall_hits::cpu.inst    176161036                       # number of overall hits
system.cpu.dcache.overall_hits::total       176161036                       # number of overall hits
system.cpu.dcache.overall_miss_latency::cpu.inst  34965753984                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  34965753984                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate::cpu.inst     0.008873                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.008873                       # miss rate for overall accesses
system.cpu.dcache.overall_misses::cpu.inst      1577062                       # number of overall misses
system.cpu.dcache.overall_misses::total       1577062                       # number of overall misses
system.cpu.dcache.overall_mshr_hits::cpu.inst       432690                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       432690                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  21322437513                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  21322437513                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.006439                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006439                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses::cpu.inst      1144372                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1144372                       # number of overall MSHR misses
system.cpu.dcache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          541                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3508                       # Occupied blocks per task id
system.cpu.dcache.tags.avg_refs            156.538362                       # Average number of references to valid blocks.
system.cpu.dcache.tags.data_accesses        362574732                       # Number of data accesses
system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.496497                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst     0.994018                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.994018                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.replacements           1140276                       # number of replacements
system.cpu.dcache.tags.sampled_refs           1144372                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.tag_accesses         362574732                       # Number of tag accesses
system.cpu.dcache.tags.tagsinuse          4071.496497                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           179138118                       # Total number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4941909250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks::writebacks      1068741                       # number of writebacks
system.cpu.dcache.writebacks::total           1068741                       # number of writebacks
system.cpu.discardedOps                      18127434                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.icache.ReadReq_accesses::cpu.inst    204480200                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    204480200                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23608.753898                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 23608.753898                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.715773                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.715773                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits::cpu.inst    204459741                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       204459741                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency::cpu.inst    483011496                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    483011496                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000100                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000100                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::cpu.inst        20459                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         20459                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    440701504                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    440701504                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000100                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000100                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        20459                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        20459                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses::cpu.inst    204480200                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    204480200                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23608.753898                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 23608.753898                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.715773                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.715773                       # average overall mshr miss latency
system.cpu.icache.demand_hits::cpu.inst     204459741                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        204459741                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency::cpu.inst    483011496                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    483011496                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::cpu.inst     0.000100                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000100                       # miss rate for demand accesses
system.cpu.icache.demand_misses::cpu.inst        20459                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          20459                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    440701504                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    440701504                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000100                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000100                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses::cpu.inst        20459                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        20459                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses::cpu.inst    204480200                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    204480200                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23608.753898                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 23608.753898                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.715773                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.715773                       # average overall mshr miss latency
system.cpu.icache.overall_hits::cpu.inst    204459741                       # number of overall hits
system.cpu.icache.overall_hits::total       204459741                       # number of overall hits
system.cpu.icache.overall_miss_latency::cpu.inst    483011496                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    483011496                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate::cpu.inst     0.000100                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000100                       # miss rate for overall accesses
system.cpu.icache.overall_misses::cpu.inst        20459                       # number of overall misses
system.cpu.icache.overall_misses::total         20459                       # number of overall misses
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    440701504                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    440701504                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000100                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000100                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses::cpu.inst        20459                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        20459                       # number of overall MSHR misses
system.cpu.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          315                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1399                       # Occupied blocks per task id
system.cpu.icache.tags.avg_refs           9993.633169                       # Average number of references to valid blocks.
system.cpu.icache.tags.data_accesses        408980859                       # Number of data accesses
system.cpu.icache.tags.occ_blocks::cpu.inst  1204.301311                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.588038                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.588038                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1881                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.918457                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.replacements             18578                       # number of replacements
system.cpu.icache.tags.sampled_refs             20459                       # Sample count of references to valid blocks.
system.cpu.icache.tags.tag_accesses         408980859                       # Number of tag accesses
system.cpu.icache.tags.tagsinuse          1204.301311                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           204459741                       # Total number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.idleCycles                        36857312                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.ipc                               0.670351                       # IPC: instructions per cycle
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses::cpu.inst       356556                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356556                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70944.376455                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70944.376455                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58283.052569                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58283.052569                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits::cpu.inst       255641                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       255641                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7159351750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7159351750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.283027                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.283027                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses::cpu.inst       100915                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       100915                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   5881634250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5881634250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.283027                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283027                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       100915                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       100915                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses::cpu.inst       808275                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       808275                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74397.741148                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74397.741148                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61739.381683                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61739.381683                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits::cpu.inst       764868                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         764868                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   3229382750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3229382750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.053703                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.053703                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses::cpu.inst        43407                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        43407                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           15                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           15                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2678995250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2678995250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.053685                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.053685                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        43392                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        43392                       # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses::writebacks      1068741                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1068741                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits::writebacks      1068741                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1068741                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses::cpu.inst      1164831                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1164831                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71983.027536                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71983.027536                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59322.344030                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59322.344030                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits::cpu.inst      1020509                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1020509                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency::cpu.inst  10388734500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10388734500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.123900                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.123900                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses::cpu.inst       144322                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        144322                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits::cpu.inst           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8560629500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8560629500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.123887                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.123887                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       144307                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       144307                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses::cpu.inst      1164831                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1164831                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71983.027536                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71983.027536                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59322.344030                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59322.344030                       # average overall mshr miss latency
system.cpu.l2cache.overall_hits::cpu.inst      1020509                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1020509                       # number of overall hits
system.cpu.l2cache.overall_miss_latency::cpu.inst  10388734500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10388734500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.123900                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.123900                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses::cpu.inst       144322                       # number of overall misses
system.cpu.l2cache.overall_misses::total       144322                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits::cpu.inst           15                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8560629500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8560629500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.123887                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.123887                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       144307                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       144307                       # number of overall MSHR misses
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          321                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4944                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25858                       # Occupied blocks per task id
system.cpu.l2cache.tags.avg_refs            11.811039                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.data_accesses        18367876                       # Number of data accesses
system.cpu.l2cache.tags.occ_blocks::writebacks 23534.473696                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  4154.581244                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.718215                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.126788                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.845003                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31193                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951935                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.replacements           111551                       # number of replacements
system.cpu.l2cache.tags.sampled_refs           142744                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.tag_accesses         18367876                       # Number of tag accesses
system.cpu.l2cache.tags.tagsinuse        27689.054939                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1685955                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     168523988500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks::writebacks        96655                       # number of writebacks
system.cpu.l2cache.writebacks::total            96655                       # number of writebacks
system.cpu.numCycles                        755696647                       # number of cpu cycles simulated
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.tickCycles                       718839335                       # Number of cycles that the CPU actually ticked
system.cpu.toL2Bus.data_through_bus         142948608                       # Total data (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40918                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3357485                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3398403                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     2185527000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      31384496                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1745291987                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.throughput               378322727                       # Throughput (bytes/s)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1309376                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141639232                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      142948608                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.trans_dist::ReadReq         808275                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        808275                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1068741                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       356556                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       356556                       # Transaction distribution
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.membus.data_through_bus               15421568                       # Total data (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       385269                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 385269                       # Packet count per connected master and slave (bytes)
system.membus.reqLayer0.occupancy          1076098500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1364495500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.throughput                     40814176                       # Throughput (bytes/s)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15421568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            15421568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadReq               43392                       # Transaction distribution
system.membus.trans_dist::ReadResp              43392                       # Transaction distribution
system.membus.trans_dist::Writeback             96655                       # Transaction distribution
system.membus.trans_dist::ReadExReq            100915                       # Transaction distribution
system.membus.trans_dist::ReadExResp           100915                       # Transaction distribution
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgGap                      1568082.50                       # Average gap between requests
system.physmem.avgMemAccLat                  29316.89                       # Average memory access latency per DRAM burst
system.physmem.avgQLat                       10566.89                       # Average queueing delay per DRAM burst
system.physmem.avgRdBW                          24.43                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgRdBWSys                       24.44                       # Average system read bandwidth in MiByte/s
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrBW                          16.37                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgWrBWSys                       16.37                       # Average system write bandwidth in MiByte/s
system.physmem.avgWrQLen                        19.41                       # Average write queue length when enqueuing
system.physmem.busUtil                           0.32                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.19                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
system.physmem.bw_inst_read::cpu.inst          599436                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             599436                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst             24442739                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                24442739                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          16371437                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            24442739                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               40814176                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks          16371437                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               16371437                       # Write bandwidth from this memory (bytes/s)
system.physmem.bytesPerActivate::samples        65344                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      235.879530                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     156.532408                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     241.691059                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24749     37.87%     37.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18254     27.94%     65.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7150     10.94%     76.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7883     12.06%     88.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2042      3.12%     91.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1102      1.69%     93.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          756      1.16%     94.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          612      0.94%     95.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         2796      4.28%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65344                       # Bytes accessed per row activation
system.physmem.bytesReadDRAM                  9229248                       # Total number of bytes read from DRAM
system.physmem.bytesReadSys                   9235648                       # Total read bytes from the system interface side
system.physmem.bytesReadWrQ                      6400                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6184768                       # Total number of bytes written to DRAM
system.physmem.bytesWrittenSys                6185920                       # Total written bytes from the system interface side
system.physmem.bytes_inst_read::cpu.inst       226496                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          226496                       # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu.inst           9235648                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9235648                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks      6185920                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6185920                       # Number of bytes written to this memory
system.physmem.memoryStateTime::IDLE     265986637250                       # Time in different power states
system.physmem.memoryStateTime::REF       12617020000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       99239970250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.num_reads::cpu.inst             144307                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                144307                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           96655                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                96655                       # Number of write requests responded to by this memory
system.physmem.pageHitRate                      72.86                       # Row buffer hit rate, read and write combined
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.perBankRdBursts::0                9328                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8986                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9010                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8718                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9475                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9358                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8951                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8100                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8572                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8669                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8784                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9499                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9376                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9538                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8741                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9102                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6202                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6099                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6021                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5821                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6172                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6184                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6018                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5493                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5732                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5815                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5965                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6456                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6307                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6282                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6014                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6056                       # Per bank write bursts
system.physmem.rdPerTurnAround::samples          5563                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.922344                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      382.692234                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5559     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            3      0.05%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5563                       # Reads before turning the bus around for writes
system.physmem.rdQLenPdf::0                    143841                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       346                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.readBursts                      144307                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  144307                       # Read request sizes (log2)
system.physmem.readReqs                        144307                       # Number of read requests accepted
system.physmem.readRowHitRate                   76.88                       # Row buffer hit rate for reads
system.physmem.readRowHits                     110862                       # Number of row buffer hits during reads
system.physmem.servicedByWrQ                      100                       # Number of DRAM read bursts serviced by the write queue
system.physmem.totBusLat                    721035000                       # Total ticks spent in databus transfers
system.physmem.totGap                    377848294500                       # Total gap between requests
system.physmem.totMemAccLat                4227701250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat                     1523820000                       # Total ticks spent queuing
system.physmem.wrPerTurnAround::samples          5563                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.371382                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.273622                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.337365                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            2499     44.92%     44.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            2925     52.58%     97.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              45      0.81%     98.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              18      0.32%     98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              19      0.34%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              16      0.29%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29              12      0.22%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31               7      0.13%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               2      0.04%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35               3      0.05%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               1      0.02%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39               4      0.07%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41               4      0.07%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43               2      0.04%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47               1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49               1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53               1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::70-71               2      0.04%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-73               1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5563                       # Writes before turning the bus around for reads
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3052                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5530                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5663                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5657                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5657                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5655                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5632                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5620                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5645                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5589                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.writeBursts                      96655                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  96655                       # Write request sizes (log2)
system.physmem.writeReqs                        96655                       # Number of write requests accepted
system.physmem.writeRowHitRate                  66.87                       # Row buffer hit rate for writes
system.physmem.writeRowHits                     64630                       # Number of row buffer hits during writes
system.voltage_domain.voltage                       1                       # Voltage in Volts

---------- End Simulation Statistics   ----------