path: root/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.363600                       # Number of seconds simulated
sim_ticks                                363599502500                       # Number of ticks simulated
final_tick                               363599502500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 226144                       # Simulator instruction rate (inst/s)
host_op_rate                                   244944                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              162315109                       # Simulator tick rate (ticks/s)
host_mem_usage                                 321124                       # Number of bytes of host memory used
host_seconds                                  2240.08                       # Real time elapsed on the host
sim_insts                                   506582156                       # Number of instructions simulated
sim_ops                                     548695379                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            219456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9004480                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9223936                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       219456                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          219456                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6189376                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6189376                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3429                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             140695                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                144124                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           96709                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                96709                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               603565                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             24764830                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                25368396                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          603565                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             603565                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          17022510                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               17022510                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          17022510                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              603565                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            24764830                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               42390905                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        144124                       # Number of read requests accepted
system.physmem.writeReqs                        96709                       # Number of write requests accepted
system.physmem.readBursts                      144124                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      96709                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9217920                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6016                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6188224                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9223936                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6189376                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       94                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9331                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8969                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9003                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8675                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9453                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9352                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8945                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8102                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8582                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8674                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8765                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9476                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9348                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9513                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8719                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9123                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6195                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6094                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6011                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5821                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6181                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6188                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6015                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5499                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5743                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5830                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5965                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6463                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6312                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6285                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6003                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6086                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    363599476500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  144124                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  96709                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    143660                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       349                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2957                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5541                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5659                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5679                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5666                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5666                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5691                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5712                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5675                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5613                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5596                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65302                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      235.912652                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     156.372535                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     241.914583                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24788     37.96%     37.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18406     28.19%     66.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6849     10.49%     76.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7905     12.11%     88.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2084      3.19%     91.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1111      1.70%     93.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          761      1.17%     94.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          643      0.98%     95.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         2755      4.22%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65302                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5583                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.797421                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      381.883100                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5579     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            3      0.05%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5583                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5583                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.318825                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.224966                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.238810                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               2516     45.07%     45.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 99      1.77%     46.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               2663     47.70%     94.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                163      2.92%     97.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 38      0.68%     98.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 18      0.32%     98.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 14      0.25%     98.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  8      0.14%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  6      0.11%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  9      0.16%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  5      0.09%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  4      0.07%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  4      0.07%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  6      0.11%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  2      0.04%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                  3      0.05%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  2      0.04%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33                  4      0.07%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  2      0.04%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  2      0.04%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  2      0.04%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                  1      0.02%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40                  1      0.02%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41                  1      0.02%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43                  1      0.02%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44                  1      0.02%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47                  1      0.02%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50                  2      0.04%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52                  1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::53                  1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::55                  1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::61                  1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::62                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5583                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1538433000                       # Total ticks spent queuing
system.physmem.totMemAccLat                4238995500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    720150000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10681.34                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29431.34                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          25.35                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          17.02                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       25.37                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       17.02                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        19.80                       # Average write queue length when enqueuing
system.physmem.readRowHits                     110870                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64542                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.98                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.74                       # Row buffer hit rate for writes
system.physmem.avgGap                      1509757.70                       # Average gap between requests
system.physmem.pageHitRate                      72.86                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  248293080                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  135477375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 560086800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                310832640                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            23748226320                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            47486002320                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           176502477750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             248991396285                       # Total energy per rank (pJ)
system.physmem_0.averagePower              684.804658                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   293320694250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     12141220000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     58133810750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  245148120                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  133761375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 562957200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                315401040                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            23748226320                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            46957937220                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           176965692750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             248929124025                       # Total energy per rank (pJ)
system.physmem_1.averagePower              684.633389                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   294092512000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     12141220000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     57361058000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               131895360                       # Number of BP lookups
system.cpu.branchPred.condPredicted          98029927                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           6139026                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             68388068                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                64396789                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             94.163779                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 9981632                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              18119                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        727199005                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   506582156                       # Number of instructions committed
system.cpu.committedOps                     548695379                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      13199573                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.435501                       # CPI: cycles per instruction
system.cpu.ipc                               0.696621                       # IPC: instructions per cycle
system.cpu.tickCycles                       690715590                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        36483415                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           1139984                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4070.789434                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           171168644                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1144080                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            149.612478                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4896334500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4070.789434                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993845                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993845                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          551                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3499                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         346592332                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        346592332                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    114650184                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114650184                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     53538625                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53538625                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2753                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2753                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     168188809                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168188809                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    168191562                       # number of overall hits
system.cpu.dcache.overall_hits::total       168191562                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       854786                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        854786                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       700681                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       700681                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           15                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           15                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1555467                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1555467                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1555482                       # number of overall misses
system.cpu.dcache.overall_misses::total       1555482                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  14024022500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14024022500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  21893600500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  21893600500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  35917623000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  35917623000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  35917623000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  35917623000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    115504970                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    115504970                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2768                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2768                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    169744276                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    169744276                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    169747044                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    169747044                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007400                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007400                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012918                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012918                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005419                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.005419                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009164                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009164                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009164                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009164                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.471912                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.471912                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31246.174079                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31246.174079                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23091.215050                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23091.215050                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.992374                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23090.992374                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1068583                       # number of writebacks
system.cpu.dcache.writebacks::total           1068583                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66886                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        66886                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344513                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       344513                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       411399                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       411399                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       411399                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       411399                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       787900                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       787900                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356168                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356168                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1144068                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1144068                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1144080                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1144080                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12337991000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12337991000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11121217500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11121217500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       946000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       946000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23459208500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23459208500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23460154500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  23460154500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006821                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006821                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006567                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006567                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004335                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004335                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006740                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006740                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006740                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006740                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.336210                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.336210                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31224.639777                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31224.639777                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78833.333333                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78833.333333                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20505.082303                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20505.082303                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20505.694095                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20505.694095                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             17702                       # number of replacements
system.cpu.icache.tags.tagsinuse          1188.317648                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           199314883                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             19574                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          10182.634260                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1188.317648                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.580233                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.580233                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          306                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1404                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         398688488                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        398688488                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    199314883                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       199314883                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     199314883                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        199314883                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    199314883                       # number of overall hits
system.cpu.icache.overall_hits::total       199314883                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        19574                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         19574                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        19574                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          19574                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        19574                       # number of overall misses
system.cpu.icache.overall_misses::total         19574                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    491333500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    491333500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    491333500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    491333500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    491333500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    491333500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    199334457                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    199334457                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    199334457                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    199334457                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    199334457                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    199334457                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000098                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000098                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000098                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000098                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000098                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000098                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25101.333401                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 25101.333401                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25101.333401                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 25101.333401                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25101.333401                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25101.333401                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19574                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        19574                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        19574                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        19574                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        19574                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        19574                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    471759500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    471759500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    471759500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    471759500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    471759500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    471759500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000098                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000098                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000098                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24101.333401                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24101.333401                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24101.333401                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 24101.333401                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24101.333401                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 24101.333401                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111370                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27634.033642                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1767249                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           142558                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.396702                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     163253473000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23457.713364                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   389.652620                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  3786.667658                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.715873                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011891                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.115560                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.843324                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31188                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          323                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4939                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25857                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951782                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         19030322                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        19030322                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      1068583                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1068583                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       255591                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       255591                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        16143                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        16143                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       747780                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       747780                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        16143                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1003371                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1019514                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        16143                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1003371                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1019514                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       100829                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       100829                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3431                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         3431                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        39880                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        39880                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3431                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       140709                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        144140                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3431                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       140709                       # number of overall misses
system.cpu.l2cache.overall_misses::total       144140                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7905743000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7905743000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    272299500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    272299500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3282195500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   3282195500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    272299500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11187938500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11460238000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    272299500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11187938500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11460238000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      1068583                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1068583                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       356420                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356420                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        19574                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        19574                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       787660                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       787660                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        19574                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1144080                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1163654                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        19574                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1144080                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1163654                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282894                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.282894                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.175284                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.175284                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.050631                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.050631                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.175284                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.122989                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.123868                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.175284                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.122989                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.123868                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78407.432386                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78407.432386                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79364.471000                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79364.471000                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82301.792879                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82301.792879                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79364.471000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79511.179100                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79507.686971                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79364.471000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79511.179100                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79507.686971                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        96709                       # number of writebacks
system.cpu.l2cache.writebacks::total            96709                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           14                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           14                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1197                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         1197                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100829                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       100829                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3429                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3429                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        39866                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        39866                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3429                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       140695                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       144124                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3429                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       140695                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       144124                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6897453000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6897453000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    237701500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    237701500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2882229000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2882229000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    237701500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9779682000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  10017383500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    237701500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9779682000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  10017383500                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282894                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282894                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.175181                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.175181                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050613                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050613                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.175181                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122977                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.123855                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.175181                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122977                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.123855                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68407.432386                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68407.432386                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69320.939049                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69320.939049                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72297.923042                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72297.923042                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69320.939049                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69509.804897                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69505.311399                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69320.939049                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69509.804897                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69505.311399                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      2321340                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      1157756                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4922                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2616                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2613                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp        807234                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1165292                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        98842                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       356420                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       356420                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        19574                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       787660                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56613                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3423459                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3480072                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1252736                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141610432                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          142863168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      111370                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      2432710                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.005152                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.071609                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2420180     99.48%     99.48% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              12527      0.51%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  3      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2432710                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2229253000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      29379463                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1716126986                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.membus.trans_dist::ReadResp              43295                       # Transaction distribution
system.membus.trans_dist::Writeback             96709                       # Transaction distribution
system.membus.trans_dist::CleanEvict            13242                       # Transaction distribution
system.membus.trans_dist::ReadExReq            100829                       # Transaction distribution
system.membus.trans_dist::ReadExResp           100829                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         43295                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       398199                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 398199                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15413312                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15413312                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            254075                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  254075    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              254075                       # Request fanout histogram
system.membus.reqLayer0.occupancy           683661500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy          765035500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------