path: root/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.365934                       # Number of seconds simulated
sim_ticks                                365934171500                       # Number of ticks simulated
final_tick                               365934171500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 236242                       # Simulator instruction rate (inst/s)
host_op_rate                                   255881                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              170651382                       # Simulator tick rate (ticks/s)
host_mem_usage                                 317968                       # Number of bytes of host memory used
host_seconds                                  2144.34                       # Real time elapsed on the host
sim_insts                                   506582156                       # Number of instructions simulated
sim_ops                                     548695379                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            218560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           8996480                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9215040                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       218560                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          218560                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6186432                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6186432                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3415                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             140570                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                143985                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           96663                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                96663                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               597266                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             24584968                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                25182234                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          597266                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             597266                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          16905860                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               16905860                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          16905860                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              597266                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            24584968                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               42088095                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        143985                       # Number of read requests accepted
system.physmem.writeReqs                        96663                       # Number of write requests accepted
system.physmem.readBursts                      143985                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      96663                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9208192                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6848                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6184704                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9215040                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6186432                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      107                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9335                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8992                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8932                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8655                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9455                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9355                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8940                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8097                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8569                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8673                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8766                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9474                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9347                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9510                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8717                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9061                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6192                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6097                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6005                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5812                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6185                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6187                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6017                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5496                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5731                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5829                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5965                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6464                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6313                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6284                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6001                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6058                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    365934145500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  143985                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  96663                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    143524                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       334                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2938                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5699                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5666                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5660                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5679                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5704                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5694                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5642                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5663                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5606                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5586                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65249                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      235.897316                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     156.545884                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     241.443874                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24707     37.87%     37.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18339     28.11%     65.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7015     10.75%     76.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7835     12.01%     88.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2110      3.23%     91.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1145      1.75%     93.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          725      1.11%     94.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          601      0.92%     95.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         2772      4.25%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65249                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5581                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.778176                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      381.924168                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5576     99.91%     99.91% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            4      0.07%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5581                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5581                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.315176                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.217549                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.442698                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            2634     47.20%     47.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            2799     50.15%     97.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              58      1.04%     98.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              24      0.43%     98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              19      0.34%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              10      0.18%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29               9      0.16%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31               9      0.16%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               3      0.05%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35               4      0.07%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               3      0.05%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41               4      0.07%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49               1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-73               1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::74-75               2      0.04%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-93               1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5581                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1559327000                       # Total ticks spent queuing
system.physmem.totMemAccLat                4257039500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    719390000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10837.84                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29587.84                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          25.16                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          16.90                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       25.18                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       16.91                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        20.48                       # Average write queue length when enqueuing
system.physmem.readRowHits                     110804                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64456                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.01                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.68                       # Row buffer hit rate for writes
system.physmem.avgGap                      1520619.93                       # Average gap between requests
system.physmem.pageHitRate                      72.86                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  248300640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  135481500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 559572000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                310819680                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            23900794320                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            47511748935                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           177881418000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             250548135075                       # Total energy per rank (pJ)
system.physmem_0.averagePower              684.687479                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   295615195000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     12219220000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     58096250000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  244785240                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  133563375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 562356600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                315174240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            23900794320                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            46698412230                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           178594871250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             250449957255                       # Total energy per rank (pJ)
system.physmem_1.averagePower              684.419183                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   296806540250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     12219220000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     56906569250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               132492243                       # Number of BP lookups
system.cpu.branchPred.condPredicted          98438822                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           6555205                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             68897926                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                64816869                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             94.076662                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                10008233                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              17907                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        731868343                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   506582156                       # Number of instructions committed
system.cpu.committedOps                     548695379                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      13915585                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.444718                       # CPI: cycles per instruction
system.cpu.ipc                               0.692177                       # IPC: instructions per cycle
system.cpu.tickCycles                       695013398                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        36854945                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           1139741                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4070.950270                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           171285752                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1143837                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            149.746644                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4896340500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4070.950270                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993884                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993884                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          549                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3503                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         346825855                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        346825855                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    114767186                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114767186                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     53538711                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53538711                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2773                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2773                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     168305897                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168305897                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    168308670                       # number of overall hits
system.cpu.dcache.overall_hits::total       168308670                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       854648                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        854648                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       700595                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       700595                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           14                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           14                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1555243                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1555243                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1555257                       # number of overall misses
system.cpu.dcache.overall_misses::total       1555257                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  14022869000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14022869000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  21909880500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  21909880500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  35932749500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  35932749500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  35932749500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  35932749500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    115621834                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    115621834                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2787                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2787                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    169861140                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    169861140                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    169863927                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    169863927                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007392                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007392                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012917                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012917                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005023                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.005023                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009156                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009156                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009156                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009156                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16407.771387                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16407.771387                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31273.247026                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31273.247026                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23104.266986                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23104.266986                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23104.059008                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23104.059008                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1068492                       # number of writebacks
system.cpu.dcache.writebacks::total           1068492                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66944                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        66944                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344474                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       344474                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       411418                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       411418                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       411418                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       411418                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       787704                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       787704                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356121                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356121                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1143825                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1143825                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1143837                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1143837                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12336256500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12336256500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11129164500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11129164500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1374500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1374500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23465421000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23465421000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23466795500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  23466795500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006813                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006813                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006566                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006566                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004306                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004306                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006734                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006734                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006734                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006734                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15661.030666                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15661.030666                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31251.076179                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31251.076179                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 114541.666667                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 114541.666667                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20514.869845                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20514.869845                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20515.856280                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20515.856280                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             17695                       # number of replacements
system.cpu.icache.tags.tagsinuse          1189.845505                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           200793682                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             19567                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          10261.853222                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1189.845505                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.580979                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.580979                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          298                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1411                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         401646065                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        401646065                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    200793682                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       200793682                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     200793682                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        200793682                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    200793682                       # number of overall hits
system.cpu.icache.overall_hits::total       200793682                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        19567                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         19567                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        19567                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          19567                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        19567                       # number of overall misses
system.cpu.icache.overall_misses::total         19567                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    488802000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    488802000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    488802000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    488802000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    488802000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    488802000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    200813249                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    200813249                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    200813249                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    200813249                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    200813249                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    200813249                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000097                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000097                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000097                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000097                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000097                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000097                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24980.937292                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 24980.937292                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24980.937292                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 24980.937292                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24980.937292                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 24980.937292                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19567                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        19567                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        19567                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        19567                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        19567                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        19567                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    469235000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    469235000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    469235000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    469235000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    469235000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    469235000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000097                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000097                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000097                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23980.937292                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23980.937292                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23980.937292                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 23980.937292                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23980.937292                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23980.937292                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111231                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27646.288282                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1766920                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           142419                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.406491                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     163672087500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23475.151417                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   389.993821                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  3781.143044                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.716405                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011902                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.115391                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.843698                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31188                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          322                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4931                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25867                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951782                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         19026681                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        19026681                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      1068492                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1068492                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       255561                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       255561                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        16150                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        16150                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       747691                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       747691                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        16150                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1003252                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1019402                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        16150                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1003252                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1019402                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       100813                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       100813                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3417                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         3417                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        39772                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        39772                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3417                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       140585                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        144002                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3417                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       140585                       # number of overall misses
system.cpu.l2cache.overall_misses::total       144002                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7914075500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7914075500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    270270000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    270270000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3286332500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   3286332500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    270270000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11200408000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11470678000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    270270000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11200408000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11470678000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      1068492                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1068492                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       356374                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356374                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        19567                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        19567                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       787463                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       787463                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        19567                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1143837                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1163404                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        19567                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1143837                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1163404                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282885                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.282885                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.174631                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.174631                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.050506                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.050506                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.174631                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.122906                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.123776                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.174631                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.122906                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.123776                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78502.529436                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78502.529436                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79095.697981                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79095.697981                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82629.299507                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82629.299507                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79095.697981                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79670.007469                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79656.379773                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79095.697981                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79670.007469                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79656.379773                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        96663                       # number of writebacks
system.cpu.l2cache.writebacks::total            96663                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           15                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           15                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           15                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1183                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         1183                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100813                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       100813                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3415                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3415                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        39757                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        39757                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3415                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       140570                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       143985                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3415                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       140570                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       143985                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6905945500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6905945500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    235984000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    235984000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2887628500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2887628500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    235984000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9793574000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  10029558000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    235984000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9793574000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  10029558000                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282885                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282885                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.174529                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.174529                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050487                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050487                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.174529                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122893                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.123762                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.174529                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122893                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.123762                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68502.529436                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68502.529436                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69102.196193                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69102.196193                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72631.951606                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72631.951606                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69102.196193                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69670.441773                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69656.964267                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69102.196193                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69670.441773                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69656.964267                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp        807030                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1165155                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        98658                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       356374                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       356374                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        19567                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       787463                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56593                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3422797                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3479390                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1252288                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141589056                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          142841344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      111231                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      2432071                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.045735                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.208910                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            2320840     95.43%     95.43% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2             111231      4.57%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2432071                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2228912000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      29351498                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1715762985                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.membus.trans_dist::ReadResp              43172                       # Transaction distribution
system.membus.trans_dist::Writeback             96663                       # Transaction distribution
system.membus.trans_dist::CleanEvict            13165                       # Transaction distribution
system.membus.trans_dist::ReadExReq            100813                       # Transaction distribution
system.membus.trans_dist::ReadExResp           100813                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         43172                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397798                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 397798                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15401472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15401472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            253813                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  253813    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              253813                       # Request fanout histogram
system.membus.reqLayer0.occupancy           683218000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy          764295250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------