path: root/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.199845                       # Number of seconds simulated
sim_ticks                                199845137000                       # Number of ticks simulated
final_tick                               199845137000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 125858                       # Simulator instruction rate (inst/s)
host_op_rate                                   141897                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               49782690                       # Simulator tick rate (ticks/s)
host_mem_usage                                 271600                       # Number of bytes of host memory used
host_seconds                                  4014.35                       # Real time elapsed on the host
sim_insts                                   505237723                       # Number of instructions simulated
sim_ops                                     569624283                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            216832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9264064                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9480896                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       216832                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          216832                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6248064                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6248064                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3388                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             144751                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                148139                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97626                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97626                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              1085000                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             46356214                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                47441214                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1085000                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1085000                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          31264529                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               31264529                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          31264529                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1085000                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            46356214                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               78705743                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        148141                       # Total number of read requests seen
system.physmem.writeReqs                        97626                       # Total number of write requests seen
system.physmem.cpureqs                         245778                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                      9480896                       # Total number of bytes read from memory
system.physmem.bytesWritten                   6248064                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                9480896                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6248064                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       60                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                 11                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                  9221                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                  9186                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                  9345                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                  8810                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                  9230                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                  8975                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                  9245                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                  9467                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                  9113                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 10253                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                 9691                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                 9704                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                 9106                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                 8950                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                 9023                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                 8762                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  5976                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  6117                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  6116                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  5944                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  6131                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  5962                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  6022                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  6376                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  5947                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  6637                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 6290                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 6316                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 6036                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 6064                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 5905                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 5787                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    199845120000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  148141                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  97626                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                   11                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    138213                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      9240                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       554                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        66                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4242                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     1637260686                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                4709936686                       # Sum of mem lat for all requests
system.physmem.totBusLat                    592324000                       # Total cycles spent in databus access
system.physmem.totBankLat                  2480352000                       # Total cycles spent in bank access
system.physmem.avgQLat                       11056.52                       # Average queueing delay per request
system.physmem.avgBankLat                    16749.97                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  31806.49                       # Average memory access latency
system.physmem.avgRdBW                          47.44                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          31.26                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  47.44                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                  31.26                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.49                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.02                       # Average read queue length over time
system.physmem.avgWrQLen                         8.64                       # Average write queue length over time
system.physmem.readRowHits                     128534                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     35160                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   86.80                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  36.01                       # Row buffer hit rate for writes
system.physmem.avgGap                       813148.71                       # Average gap between requests
system.cpu.branchPred.lookups               182820446                       # Number of BP lookups
system.cpu.branchPred.condPredicted         143128871                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           7268870                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             92944153                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                87230072                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             93.852135                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                12684982                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             116077                       # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        399690275                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          119371931                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      761680364                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   182820446                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           99915054                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     170174199                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                35702256                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               75350704                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   22                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           616                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           26                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 114527354                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2441016                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          392530086                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.176527                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.990721                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                222368477     56.65%     56.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 14183765      3.61%     60.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 22901577      5.83%     66.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 22747664      5.80%     71.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 20903604      5.33%     77.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 11591587      2.95%     80.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 13062137      3.33%     83.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 11992821      3.06%     86.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 52778454     13.45%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            392530086                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.457405                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.905676                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                129024913                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              70885415                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 158884550                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               6176695                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               27558513                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             26126183                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 76772                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              825683046                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                296199                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               27558513                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                135608190                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 9588825                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       46459719                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158300780                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              15014059                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              800754331                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  1065                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                3044118                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               8771537                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              204                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           954467105                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3501224581                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3501223353                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              1228                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             666252291                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                288214814                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            2293021                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        2293019                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  41499614                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            170286842                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            73502565                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          28542432                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         15757224                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  755181384                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             3775400                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 665429696                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1394216                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       187494219                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    479993782                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         797768                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     392530086                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.695232                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.736006                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           137153831     34.94%     34.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            69768231     17.77%     52.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            71497423     18.21%     70.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            53360624     13.59%     84.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            31181551      7.94%     92.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            16101363      4.10%     96.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             8735003      2.23%     98.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             2914770      0.74%     99.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1817290      0.46%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       392530086                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  481185      5.01%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                6545421     68.20%     73.22% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2570325     26.78%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             447832117     67.30%     67.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               383268      0.06%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  86      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            153411814     23.05%     90.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            63802408      9.59%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              665429696                       # Type of FU issued
system.cpu.iq.rate                           1.664863                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     9596931                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014422                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1734380418                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         947258082                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    646140584                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 207                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                274                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              675026522                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     105                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          8582869                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     44257287                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        42197                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       811123                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     16642088                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        19492                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          4090                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               27558513                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 4987467                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                372691                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           760516980                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1117257                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             170286842                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             73502565                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            2286858                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 219486                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 11052                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         811123                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        4340984                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4003792                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8344776                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             656001968                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             150122200                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           9427728                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       1560196                       # number of nop insts executed
system.cpu.iew.exec_refs                    212633148                       # number of memory reference insts executed
system.cpu.iew.exec_branches                138504923                       # Number of branches executed
system.cpu.iew.exec_stores                   62510948                       # Number of stores executed
system.cpu.iew.exec_rate                     1.641276                       # Inst execution rate
system.cpu.iew.wb_sent                      651119979                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     646140600                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 374813030                       # num instructions producing a value
system.cpu.iew.wb_consumers                 646558310                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.616603                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.579705                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       189575186                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           7194795                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    364971573                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.564418                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.233675                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    157304822     43.10%     43.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     98491978     26.99%     70.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     33807803      9.26%     79.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     18748044      5.14%     84.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     16202992      4.44%     88.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7453577      2.04%     90.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      6993904      1.92%     92.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3174450      0.87%     93.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     22794003      6.25%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    364971573                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            506581607                       # Number of instructions committed
system.cpu.commit.committedOps              570968167                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      182890032                       # Number of memory references committed
system.cpu.commit.loads                     126029555                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  121548301                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 470727693                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              22794003                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1102713785                       # The number of ROB reads
system.cpu.rob.rob_writes                  1548767048                       # The number of ROB writes
system.cpu.timesIdled                          306858                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         7160189                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   505237723                       # Number of Instructions Simulated
system.cpu.committedOps                     569624283                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             505237723                       # Number of Instructions Simulated
system.cpu.cpi                               0.791093                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.791093                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.264073                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.264073                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3059184222                       # number of integer regfile reads
system.cpu.int_regfile_writes               752090779                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.misc_regfile_reads               210880028                       # number of misc regfile reads
system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
system.cpu.icache.replacements                  15058                       # number of replacements
system.cpu.icache.tagsinuse               1101.681539                       # Cycle average of tags in use
system.cpu.icache.total_refs                114506253                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  16915                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                6769.509489                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1101.681539                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.537930                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.537930                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    114506253                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       114506253                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     114506253                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        114506253                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    114506253                       # number of overall hits
system.cpu.icache.overall_hits::total       114506253                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        21101                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         21101                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        21101                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          21101                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        21101                       # number of overall misses
system.cpu.icache.overall_misses::total         21101                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    452371500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    452371500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    452371500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    452371500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    452371500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    452371500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    114527354                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    114527354                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    114527354                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    114527354                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    114527354                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    114527354                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000184                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000184                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000184                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000184                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000184                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000184                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21438.391545                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21438.391545                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21438.391545                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21438.391545                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21438.391545                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21438.391545                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          357                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                10                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    35.700000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4104                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         4104                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         4104                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         4104                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         4104                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         4104                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        16997                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        16997                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        16997                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        16997                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        16997                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        16997                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    339326500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    339326500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    339326500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    339326500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    339326500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    339326500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000148                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000148                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000148                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19963.905395                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19963.905395                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19963.905395                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 19963.905395                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19963.905395                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19963.905395                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                115392                       # number of replacements
system.cpu.l2cache.tagsinuse             27104.061391                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1781385                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                146645                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 12.147601                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          100645092000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 23030.603679                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    365.807656                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   3707.650056                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.702838                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.011164                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.113149                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.827150                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        13507                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       804164                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         817671                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1110730                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1110730                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           70                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           70                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       247532                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       247532                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        13507                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1051696                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1065203                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        13507                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1051696                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1065203                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3394                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        43490                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        46884                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           11                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           11                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       101287                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       101287                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3394                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       144777                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        148171                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3394                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       144777                       # number of overall misses
system.cpu.l2cache.overall_misses::total       148171                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    186700000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2546099500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2732799500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5401014000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5401014000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    186700000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7947113500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8133813500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    186700000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7947113500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8133813500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        16901                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       847654                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       864555                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1110730                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1110730                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           81                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           81                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       348819                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       348819                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        16901                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1196473                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1213374                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        16901                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1196473                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1213374                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.200817                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.051306                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.054229                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.135802                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.135802                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.290371                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.290371                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200817                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.121003                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.122115                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200817                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.121003                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.122115                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55008.839128                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58544.481490                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 58288.531269                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53323.861897                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53323.861897                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55008.839128                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54892.099574                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 54894.773606                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55008.839128                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54892.099574                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54894.773606                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97626                       # number of writebacks
system.cpu.l2cache.writebacks::total            97626                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           25                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           30                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           25                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           30                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           25                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           30                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3389                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        43465                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        46854                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           11                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           11                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101287                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       101287                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3389                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       144752                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       148141                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3389                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       144752                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       148141                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    143453810                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1990470119                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2133923929                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       115510                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       115510                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4113084396                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4113084396                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    143453810                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6103554515                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6247008325                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    143453810                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6103554515                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6247008325                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.200521                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.051277                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.054194                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.135802                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.135802                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.290371                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.290371                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200521                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.120982                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.122090                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200521                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.120982                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.122090                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42329.244615                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45794.780145                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45544.114249                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10500.909091                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10500.909091                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.216217                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.216217                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42329.244615                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42165.597125                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42169.340864                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42329.244615                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42165.597125                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42169.340864                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1192376                       # number of replacements
system.cpu.dcache.tagsinuse               4058.257289                       # Cycle average of tags in use
system.cpu.dcache.total_refs                190193687                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1196472                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 158.962088                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             4128824000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4058.257289                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.990785                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.990785                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    136223717                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       136223717                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     50992367                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       50992367                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488803                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488803                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     187216084                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        187216084                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    187216084                       # number of overall hits
system.cpu.dcache.overall_hits::total       187216084                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1697690                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1697690                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3246939                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3246939                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           35                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           35                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      4944629                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4944629                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4944629                       # number of overall misses
system.cpu.dcache.overall_misses::total       4944629                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  26054770000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  26054770000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  58807860452                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  58807860452                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       537000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       537000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  84862630452                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  84862630452                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  84862630452                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  84862630452                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    137921407                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    137921407                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488838                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488838                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    192160713                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    192160713                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    192160713                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    192160713                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012309                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.012309                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.059863                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.059863                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000024                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000024                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.025732                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.025732                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.025732                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.025732                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15347.189416                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15347.189416                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18111.784808                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 18111.784808                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15342.857143                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15342.857143                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17162.588023                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17162.588023                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17162.588023                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17162.588023                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        16266                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        14829                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1654                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             595                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.834341                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    24.922689                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1110730                       # number of writebacks
system.cpu.dcache.writebacks::total           1110730                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       849485                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       849485                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2898590                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2898590                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           35                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           35                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3748075                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3748075                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3748075                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3748075                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       848205                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       848205                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348349                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       348349                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1196554                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1196554                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1196554                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1196554                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11474356500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  11474356500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8274514996                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8274514996                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19748871496                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  19748871496                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19748871496                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  19748871496                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006150                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006150                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006422                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006422                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006227                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006227                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006227                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006227                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13527.810494                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13527.810494                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23753.520165                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23753.520165                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16504.789166                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16504.789166                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16504.789166                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16504.789166                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------