path: root/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.234108                       # Number of seconds simulated
sim_ticks                                234107886500                       # Number of ticks simulated
final_tick                               234107886500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 148403                       # Simulator instruction rate (inst/s)
host_op_rate                                   167177                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               68261843                       # Simulator tick rate (ticks/s)
host_mem_usage                                 232040                       # Number of bytes of host memory used
host_seconds                                  3429.56                       # Real time elapsed on the host
sim_insts                                   508954871                       # Number of instructions simulated
sim_ops                                     573341432                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read                    15193216                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                 241280                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                 10938560                       # Number of bytes written to this memory
system.physmem.num_reads                       237394                       # Number of read requests responded to by this memory
system.physmem.num_writes                      170915                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                       64898352                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                   1030636                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write                      46724440                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total                     111622792                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        468215774                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                200061766                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted          161279268                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect           13261114                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups             110371027                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 98350021                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                 10012114                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect             2451761                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles          136559610                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      898175750                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   200061766                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          108362135                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     197576941                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                54094157                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               91756620                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   80                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         71734                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                 126283016                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               3812130                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          464400798                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.257289                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.102621                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                266835612     57.46%     57.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 16224757      3.49%     60.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 21301662      4.59%     65.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 22971866      4.95%     70.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 24200733      5.21%     75.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 13160700      2.83%     78.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 13387272      2.88%     81.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 12932496      2.78%     84.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 73385700     15.80%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            464400798                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.427285                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.918295                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                151819691                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              87315779                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 182356495                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               4679019                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               38229814                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             32058950                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                208727                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              978247672                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                304018                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               38229814                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                165098123                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 6680773                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       67210378                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 173611976                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13569734                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              900335199                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  1400                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2808611                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               7742666                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents               62                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          1050683608                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3921835451                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3921830870                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              4581                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             672199728                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                378483880                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            6257639                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        6252483                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  74230305                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            187204403                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            74981295                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          17030714                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         11234948                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  805916100                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             7086662                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 700681614                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1544151                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       236754435                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    596849341                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        3208414                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     464400798                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.508786                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.706470                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           194454987     41.87%     41.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            75651609     16.29%     58.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            69485384     14.96%     73.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            61139015     13.17%     86.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            35296693      7.60%     93.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            15466096      3.33%     97.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             7603561      1.64%     98.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             3924050      0.84%     99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1379403      0.30%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       464400798                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  453814      4.63%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.63% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                6693711     68.30%     72.93% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2653315     27.07%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             472302081     67.41%     67.41% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               386521      0.06%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 170      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.46% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            162598638     23.21%     90.67% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            65394201      9.33%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              700681614                       # Type of FU issued
system.cpu.iq.rate                           1.496493                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     9800840                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.013988                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1877108639                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1049814796                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    668235184                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 378                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                790                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              710482264                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     190                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          9094204                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     60431419                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        43883                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        61918                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     17377390                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        20851                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           399                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               38229814                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 2886721                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                175953                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           821878596                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           9525062                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             187204403                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             74981295                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            5597916                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  86243                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  8756                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          61918                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       10539331                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      7737636                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             18276967                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             681941706                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             155293366                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          18739908                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       8875834                       # number of nop insts executed
system.cpu.iew.exec_refs                    219203468                       # number of memory reference insts executed
system.cpu.iew.exec_branches                142018558                       # Number of branches executed
system.cpu.iew.exec_stores                   63910102                       # Number of stores executed
system.cpu.iew.exec_rate                     1.456469                       # Inst execution rate
system.cpu.iew.wb_sent                      673034239                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     668235200                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 381399199                       # num instructions producing a value
system.cpu.iew.wb_consumers                 655303832                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.427195                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.582019                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      510298755                       # The number of committed instructions
system.cpu.commit.commitCommittedOps        574685316                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts       247211019                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         3878248                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          15402240                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    426170985                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.348485                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.065618                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    207821757     48.76%     48.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    103278684     24.23%     73.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     40154361      9.42%     82.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     19502589      4.58%     87.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     17446456      4.09%     91.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7236627      1.70%     92.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      7721645      1.81%     94.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3779614      0.89%     95.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     19229252      4.51%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    426170985                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            510298755                       # Number of instructions committed
system.cpu.commit.committedOps              574685316                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      184376889                       # Number of memory references committed
system.cpu.commit.loads                     126772984                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  120192169                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 473701413                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              19229252                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1228830930                       # The number of ROB reads
system.cpu.rob.rob_writes                  1682168121                       # The number of ROB writes
system.cpu.timesIdled                           98147                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         3814976                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   508954871                       # Number of Instructions Simulated
system.cpu.committedOps                     573341432                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             508954871                       # Number of Instructions Simulated
system.cpu.cpi                               0.919955                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.919955                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.087009                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.087009                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3163894948                       # number of integer regfile reads
system.cpu.int_regfile_writes               777442018                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.misc_regfile_reads              1131493621                       # number of misc regfile reads
system.cpu.misc_regfile_writes                4463940                       # number of misc regfile writes
system.cpu.icache.replacements                  16054                       # number of replacements
system.cpu.icache.tagsinuse               1101.947975                       # Cycle average of tags in use
system.cpu.icache.total_refs                126263236                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  17918                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                7046.725974                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1101.947975                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.538061                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.538061                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    126263236                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       126263236                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     126263236                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        126263236                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    126263236                       # number of overall hits
system.cpu.icache.overall_hits::total       126263236                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        19780                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         19780                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        19780                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          19780                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        19780                       # number of overall misses
system.cpu.icache.overall_misses::total         19780                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    264112500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    264112500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    264112500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    264112500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    264112500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    264112500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    126283016                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    126283016                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    126283016                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    126283016                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    126283016                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    126283016                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000157                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000157                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000157                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13352.502528                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13352.502528                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13352.502528                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1738                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1738                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1738                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1738                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1738                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1738                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        18042                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        18042                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        18042                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        18042                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        18042                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        18042                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    168794500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    168794500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    168794500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    168794500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    168794500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    168794500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000143                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000143                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000143                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9355.642390                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9355.642390                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9355.642390                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1204439                       # number of replacements
system.cpu.dcache.tagsinuse               4053.213241                       # Cycle average of tags in use
system.cpu.dcache.total_refs                197393966                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1208535                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 163.333264                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             5508997000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4053.213241                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.989554                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.989554                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    140143872                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       140143872                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     52777243                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       52777243                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      2240634                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      2240634                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      2231969                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      2231969                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     192921115                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        192921115                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    192921115                       # number of overall hits
system.cpu.dcache.overall_hits::total       192921115                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1321702                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1321702                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1462063                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1462063                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           79                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           79                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      2783765                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2783765                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2783765                       # number of overall misses
system.cpu.dcache.overall_misses::total       2783765                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  15361891000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  15361891000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  24945206993                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  24945206993                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       848000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       848000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  40307097993                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  40307097993                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  40307097993                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  40307097993                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    141465574                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    141465574                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2240713                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      2240713                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      2231969                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      2231969                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    195704880                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    195704880                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    195704880                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    195704880                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009343                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026956                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000035                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.014224                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.014224                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11622.809832                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17061.649869                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10734.177215                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14479.346494                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14479.346494                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       557000                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              92                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets  6054.347826                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1073316                       # number of writebacks
system.cpu.dcache.writebacks::total           1073316                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       452437                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       452437                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1122680                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1122680                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           79                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           79                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1575117                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1575117                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1575117                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1575117                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       869265                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       869265                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       339383                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       339383                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1208648                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1208648                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1208648                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1208648                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6267661500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6267661500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4319283499                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   4319283499                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10586944999                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  10586944999                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10586944999                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  10586944999                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006145                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006257                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006176                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006176                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7210.300081                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12726.870524                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8759.328604                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8759.328604                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                218164                       # number of replacements
system.cpu.l2cache.tagsinuse             21000.033728                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1558335                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                238544                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  6.532694                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          171274972000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 13326.233145                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    198.028961                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   7475.771622                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.406684                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.006043                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.228142                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.640870                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        14176                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       742295                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         756471                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1073316                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1073316                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           79                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           79                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       232581                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       232581                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        14176                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       974876                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          989052                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        14176                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       974876                       # number of overall hits
system.cpu.l2cache.overall_hits::total         989052                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3773                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       126291                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       130064                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           30                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           30                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       107358                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       107358                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3773                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       233649                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        237422                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3773                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       233649                       # number of overall misses
system.cpu.l2cache.overall_misses::total       237422                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    129366000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   4319010500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4448376500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       170500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       170500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3675900000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   3675900000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    129366000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7994910500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8124276500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    129366000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7994910500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8124276500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        17949                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       868586                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       886535                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1073316                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1073316                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          109                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          109                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       339939                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       339939                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        17949                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1208525                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1226474                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        17949                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1208525                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1226474                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.210207                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.145398                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.275229                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.315815                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.210207                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.193334                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.210207                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.193334                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.304532                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.877988                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  5683.333333                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34239.646789                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.304532                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34217.610604                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.304532                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34217.610604                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       170915                       # number of writebacks
system.cpu.l2cache.writebacks::total           170915                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           24                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           27                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           24                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           27                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           24                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           27                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3770                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       126267                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       130037                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           30                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           30                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       107358                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       107358                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3770                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       233625                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       237395                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3770                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       233625                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       237395                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    117154500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   3918910500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   4036065000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       933000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       933000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3328751000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3328751000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    117154500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7247661500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   7364816000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    117154500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7247661500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   7364816000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.210040                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.145371                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.275229                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.315815                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.210040                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.193314                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.210040                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.193314                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31075.464191                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.696049                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31100                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31006.082453                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31075.464191                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31022.628143                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31075.464191                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31022.628143                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------