path: root/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.210036                       # Number of seconds simulated
sim_ticks                                210036334500                       # Number of ticks simulated
final_tick                               210036334500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 177312                       # Simulator instruction rate (inst/s)
host_op_rate                                   199743                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               73173320                       # Simulator tick rate (ticks/s)
host_mem_usage                                 239056                       # Number of bytes of host memory used
host_seconds                                  2870.40                       # Real time elapsed on the host
sim_insts                                   508955243                       # Number of instructions simulated
sim_ops                                     573341803                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            219136                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10020416                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10239552                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       219136                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          219136                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6682560                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6682560                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3424                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             156569                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                159993                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          104415                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               104415                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              1043324                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             47708012                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                48751336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1043324                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1043324                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          31816209                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               31816209                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          31816209                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1043324                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            47708012                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               80567546                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        420072670                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                180017694                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted          142687184                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            7729396                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              94339767                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 87293897                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                 12415335                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect              116774                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles          120382403                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      794428106                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   180017694                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           99709232                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     176656328                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                41234330                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               91071148                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   14                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           358                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                 113830042                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2509224                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          418577617                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.181681                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.031530                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                241934136     57.80%     57.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 14312407      3.42%     61.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 20602450      4.92%     66.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 22857238      5.46%     71.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 20951996      5.01%     76.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 13135363      3.14%     79.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 13267726      3.17%     82.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 12107850      2.89%     85.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 59408451     14.19%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            418577617                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.428539                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.891168                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                132749600                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              85626153                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 165029361                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               4780262                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               30392241                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             26480489                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 78151                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              870641905                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                312699                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               30392241                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                142822329                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 6003622                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       66002577                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 159587024                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13769824                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              815822534                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   858                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2869085                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               7326440                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents               62                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           963278183                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3562240909                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3562236360                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              4549                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             672200323                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                291077860                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            5318003                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        5317721                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  67395600                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            171954811                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            74969765                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          27370082                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         14835909                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  760687253                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             6768595                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 671184661                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1545827                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       191893024                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    487573539                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        3047459                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     418577617                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.603489                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.725201                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           157194444     37.55%     37.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            77339610     18.48%     56.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            70514833     16.85%     72.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            51630225     12.33%     85.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            31661646      7.56%     92.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            16095104      3.85%     96.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             9461042      2.26%     98.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             3409350      0.81%     99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1271363      0.30%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       418577617                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  446687      4.54%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.54% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                6731982     68.43%     72.97% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2658540     27.03%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             450868550     67.18%     67.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               385779      0.06%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 220      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.23% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            154882510     23.08%     90.31% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            65047599      9.69%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              671184661                       # Type of FU issued
system.cpu.iq.rate                           1.597782                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     9837209                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014656                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1772329499                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         960150284                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    650772394                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 476                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                942                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              681021630                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     240                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          8403522                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     45181752                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        43422                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       806126                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     17365784                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        19422                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          1337                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               30392241                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 2471437                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                146089                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           773606723                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1210159                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             171954811                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             74969765                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            5279868                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  67842                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  6482                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         806126                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        4698240                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      6420025                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             11118265                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             661214126                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             151365480                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           9970535                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       6150875                       # number of nop insts executed
system.cpu.iew.exec_refs                    214988835                       # number of memory reference insts executed
system.cpu.iew.exec_branches                137027568                       # Number of branches executed
system.cpu.iew.exec_stores                   63623355                       # Number of stores executed
system.cpu.iew.exec_rate                     1.574047                       # Inst execution rate
system.cpu.iew.wb_sent                      655977937                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     650772410                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 374973371                       # num instructions producing a value
system.cpu.iew.wb_consumers                 645025945                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.549190                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.581331                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      510299127                       # The number of committed instructions
system.cpu.commit.commitCommittedOps        574685687                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts       198937259                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         3721136                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           9897053                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    388185377                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.480441                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.160280                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    174260848     44.89%     44.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    102323189     26.36%     71.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     36274304      9.34%     80.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     18231179      4.70%     85.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     17368323      4.47%     89.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      8208578      2.11%     91.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      6882791      1.77%     93.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3781895      0.97%     94.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     20854270      5.37%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    388185377                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            510299127                       # Number of instructions committed
system.cpu.commit.committedOps              574685687                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      184377040                       # Number of memory references committed
system.cpu.commit.loads                     126773059                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  120192244                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 473701709                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              20854270                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1140946915                       # The number of ROB reads
system.cpu.rob.rob_writes                  1577778936                       # The number of ROB writes
system.cpu.timesIdled                           55077                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         1495053                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   508955243                       # Number of Instructions Simulated
system.cpu.committedOps                     573341803                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             508955243                       # Number of Instructions Simulated
system.cpu.cpi                               0.825363                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.825363                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.211589                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.211589                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3085576786                       # number of integer regfile reads
system.cpu.int_regfile_writes               758984284                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.misc_regfile_reads              1021861854                       # number of misc regfile reads
system.cpu.misc_regfile_writes                4464092                       # number of misc regfile writes
system.cpu.icache.replacements                  15860                       # number of replacements
system.cpu.icache.tagsinuse               1099.172767                       # Cycle average of tags in use
system.cpu.icache.total_refs                113810641                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  17722                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                6421.997574                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1099.172767                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.536705                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.536705                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    113810641                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       113810641                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     113810641                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        113810641                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    113810641                       # number of overall hits
system.cpu.icache.overall_hits::total       113810641                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        19401                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         19401                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        19401                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          19401                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        19401                       # number of overall misses
system.cpu.icache.overall_misses::total         19401                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    248637000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    248637000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    248637000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    248637000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    248637000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    248637000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    113830042                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    113830042                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    113830042                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    113830042                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    113830042                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    113830042                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000170                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000170                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000170                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000170                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000170                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000170                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12815.679604                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 12815.679604                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 12815.679604                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 12815.679604                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 12815.679604                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 12815.679604                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1635                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1635                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1635                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1635                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1635                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1635                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        17766                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        17766                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        17766                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        17766                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        17766                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        17766                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    157002000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    157002000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    157002000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    157002000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    157002000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    157002000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000156                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000156                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000156                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000156                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000156                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000156                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8837.217156                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  8837.217156                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8837.217156                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  8837.217156                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8837.217156                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  8837.217156                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1187572                       # number of replacements
system.cpu.dcache.tagsinuse               4054.018588                       # Cycle average of tags in use
system.cpu.dcache.total_refs                194536167                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1191668                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 163.246950                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             4842467000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4054.018588                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.989751                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.989751                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    137268360                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       137268360                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     52802735                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       52802735                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      2232908                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      2232908                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      2232045                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      2232045                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     190071095                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        190071095                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    190071095                       # number of overall hits
system.cpu.dcache.overall_hits::total       190071095                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1261511                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1261511                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1436571                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1436571                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           44                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           44                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      2698082                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2698082                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2698082                       # number of overall misses
system.cpu.dcache.overall_misses::total       2698082                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  11193325500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  11193325500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  24423594500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  24423594500                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       430500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       430500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  35616920000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  35616920000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  35616920000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  35616920000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    138529871                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    138529871                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2232952                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      2232952                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      2232045                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      2232045                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    192769177                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    192769177                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    192769177                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    192769177                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009106                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.009106                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026486                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.026486                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000020                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000020                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.013996                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.013996                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.013996                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.013996                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  8872.951167                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total  8872.951167                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17001.313893                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17001.313893                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9784.090909                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9784.090909                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13200.829330                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13200.829330                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13200.829330                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13200.829330                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      3248500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             559                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets  5811.270125                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1101877                       # number of writebacks
system.cpu.dcache.writebacks::total           1101877                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       417972                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       417972                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1088398                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1088398                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           44                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           44                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1506370                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1506370                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1506370                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1506370                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       843539                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       843539                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348173                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       348173                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1191712                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1191712                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1191712                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1191712                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3801302500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   3801302500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4208028500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   4208028500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8009331000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   8009331000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   8009331000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   8009331000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006089                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006089                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006419                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006419                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006182                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006182                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006182                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006182                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  4506.374335                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  4506.374335                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12086.027636                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12086.027636                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  6720.861248                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total  6720.861248                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  6720.861248                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total  6720.861248                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                128814                       # number of replacements
system.cpu.l2cache.tagsinuse             26521.071882                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1726136                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                160049                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 10.785047                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          108383253000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 22699.952079                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    308.453582                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   3512.666221                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.692748                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.009413                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.107198                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.809359                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        14292                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       789500                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         803792                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1101877                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1101877                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           38                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           38                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       245577                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       245577                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        14292                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1035077                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1049369                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        14292                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1035077                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1049369                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3428                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        53156                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        56584                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       103436                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       103436                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3428                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       156592                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        160020                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3428                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       156592                       # number of overall misses
system.cpu.l2cache.overall_misses::total       160020                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    117618500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1820625500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1938244000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3542483500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   3542483500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    117618500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   5363109000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   5480727500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    117618500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   5363109000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   5480727500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        17720                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       842656                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       860376                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1101877                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1101877                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           43                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           43                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       349013                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       349013                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        17720                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1191669                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1209389                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        17720                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1191669                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1209389                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.193454                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.063081                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.065767                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.116279                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.116279                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.296367                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.296367                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.193454                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.131406                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.132315                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.193454                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.131406                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.132315                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34311.114352                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34250.611408                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34254.276827                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34248.071271                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34248.071271                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34311.114352                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34248.933534                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34250.265592                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34311.114352                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34248.933534                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34250.265592                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       104415                       # number of writebacks
system.cpu.l2cache.writebacks::total           104415                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           22                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           26                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           26                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           26                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3424                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        53134                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        56558                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       103436                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       103436                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3424                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       156570                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       159994                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3424                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       156570                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       159994                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    106506000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1650725500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1757231500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       155000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       155000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3207102500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3207102500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    106506000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4857828000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   4964334000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    106506000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4857828000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   4964334000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.193228                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.063055                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.065736                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.116279                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.116279                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.296367                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.296367                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.193228                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.131387                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.132293                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.193228                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.131387                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.132293                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.724299                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31067.216848                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31069.548075                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31005.670173                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31005.670173                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.724299                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31026.556812                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31028.251059                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.724299                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31026.556812                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31028.251059                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------